f57d0dce95
S3_DATA_POS defines address where the whole S3 data is stored. Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/2438 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
66 lines
1.7 KiB
Plaintext
Executable File
66 lines
1.7 KiB
Plaintext
Executable File
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Advanced Micro Devices, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config SOUTHBRIDGE_AMD_CIMX_SB900
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bool
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default n
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select IOAPIC
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select AMD_SB_CIMX
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if SOUTHBRIDGE_AMD_CIMX_SB900
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config SATA_CONTROLLER_MODE
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hex
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default 0x0
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help
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0x0 = Native IDE mode.
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0x1 = RAID mode.
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0x2 = AHCI mode.
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0x3 = Legacy IDE mode.
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0x4 = IDE->AHCI mode.
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0x5 = AHCI mode as 7804 ID (AMD driver).
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0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
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config PCIB_ENABLE
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bool
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default n
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help
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n = Disable PCI Bridge Device 14 Function 4.
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y = Enable PCI Bridge Device 14 Function 4.
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config ACPI_SCI_IRQ
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hex
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default 0x9
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help
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Set SCI IRQ to 9.
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/amd/cimx/sb900/bootblock.c"
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config S3_DATA_POS
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hex "S3 volatile storage position"
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default 0xFFFF0000
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depends on HAVE_ACPI_RESUME
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help
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For a system with S3 feature, the BIOS needs to save some data to
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non-volatile storage at cold boot stage.
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endif #SOUTHBRIDGE_AMD_CIMX_SB900
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