f65c1e4088
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
108 lines
2.4 KiB
C
108 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define __SIMPLE_DEVICE__
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#include <assert.h>
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#include <stdint.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cbmem.h>
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#include <arch/bert_storage.h>
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#include <soc/northbridge.h>
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#include <soc/iomap.h>
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#include <amdblocks/acpimmio.h>
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#if CONFIG(ACPI_BERT)
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#if CONFIG_SMM_TSEG_SIZE == 0x0
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#define BERT_REGION_MAX_SIZE 0x100000
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#else
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/* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */
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#define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE
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#endif
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#else
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#define BERT_REGION_MAX_SIZE 0
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#endif
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void bert_reserved_region(void **start, size_t *size)
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{
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if (CONFIG(ACPI_BERT))
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*start = cbmem_top();
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else
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start = NULL;
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*size = BERT_REGION_MAX_SIZE;
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}
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void *cbmem_top_chipset(void)
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{
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msr_t tom = rdmsr(TOP_MEM);
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if (!tom.lo)
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return 0;
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/* 8MB alignment to keep MTRR usage low */
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return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
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- CONFIG_SMM_TSEG_SIZE
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- BERT_REGION_MAX_SIZE, 8*MiB);
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}
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static uintptr_t smm_region_start(void)
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{
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return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE;
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}
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static size_t smm_region_size(void)
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{
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return CONFIG_SMM_TSEG_SIZE;
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}
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/*
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* For data stored in TSEG, ensure TValid is clear so R/W access can reach
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* the DRAM when not in SMM.
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*/
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static void clear_tvalid(void)
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{
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msr_t hwcr = rdmsr(HWCR_MSR);
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msr_t mask = rdmsr(SMM_MASK_MSR);
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int tvalid = !!(mask.lo & SMM_TSEG_VALID);
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if (hwcr.lo & SMM_LOCK) {
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if (!tvalid) /* not valid but locked means still accessible */
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return;
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printk(BIOS_ERR, "Error: can't clear TValid, already locked\n");
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return;
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}
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mask.lo &= ~SMM_TSEG_VALID;
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wrmsr(SMM_MASK_MSR, mask);
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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static int once;
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*start = smm_region_start();
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*size = smm_region_size();
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if (!once) {
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clear_tvalid();
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once = 1;
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}
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}
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