16fe79048f
All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <southbridge/intel/common/smbus.h>
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#define SMBUS_IO_BASE 0x0f00
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static void enable_smbus(void)
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{
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pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
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printk(BIOS_SPEW, "SMBus controller enabled\n");
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pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
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pci_write_config8(dev, 0x40, 1);
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pci_write_config8(dev, 0x4, 1);
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/* SMBALERT_DIS */
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outb(4, SMBUS_IO_BASE + SMBSLVCMD);
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/* Disable interrupt generation */
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outb(0, SMBUS_IO_BASE + SMBHSTCTL);
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}
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static __attribute__((unused)) int smbus_read_byte(u32 device, u32 address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
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}
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static __attribute__((unused)) int smbus_write_byte(unsigned device, u8 address, u8 data)
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{
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return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
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}
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