f70bd99d2a
unused includes of <stdin.h> found using following commande: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\| uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\| u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\ |INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\ |INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/) |grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include "pch.h"
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void southbridge_configure_default_intmap(void)
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{
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/*
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* For the PCH internal PCI functions, provide a reasonable
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* default IRQ mapping that utilizes only PIRQ A to D. Higher
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* PIRQs are sometimes used for other on-board chips that
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* require an edge triggered interrupt which is not shareable.
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*/
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/*
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* We use a linear mapping for the pin numbers. They are not
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* physical pins, and thus, have no relation between the dif-
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* ferent devices. Only rule we must obey is that a single-
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* function device has to use pin A.
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*/
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RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) |
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(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
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RCBA32(D29IP) = (INTA << D29IP_E1P);
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RCBA32(D28IP) = (INTD << D28IP_P8IP) | (INTC << D28IP_P7IP) |
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(INTB << D28IP_P6IP) | (INTA << D28IP_P5IP) |
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(INTD << D28IP_P4IP) | (INTC << D28IP_P3IP) |
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(INTB << D28IP_P2IP) | (INTA << D28IP_P1IP);
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RCBA32(D27IP) = (INTA << D27IP_ZIP);
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RCBA32(D26IP) = (INTA << D26IP_E2P);
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RCBA32(D25IP) = (INTA << D25IP_LIP);
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RCBA32(D22IP) = (INTA << D22IP_MEI1IP);
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RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
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/*
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* For the PIRQ allocation the following was taken into
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* account:
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* o Interrupts of the PCIe root ports are only about
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* events at the ports, not downstream devices. So we
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* don't expect many interrupts there and ignore them.
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* o We don't expect to talk constantly to the ME either
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* so ignore that, too. Same for SMBus and the thermal
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* device.
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* o Second SATA interface is only used in non-AHCI mode
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* so unlikely to coexist with modern interfaces (e.g.
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* xHCI).
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* o An OS that knows USB3 will likely also know how to
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* use MSI.
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*
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* The functions that might matter first:
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*
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* D31IP_SIP SATA 1 -> PIRQ A (MSI capable in AHCI mode)
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* D31IP_SIP2 SATA 2 -> PIRQ B
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* D29IP_E1P EHCI 1 -> PIRQ C
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* D27IP_ZIP HDA -> PIRQ D (MSI capable)
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* D26IP_E2P EHCI 2 -> PIRQ D
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* D25IP_LIP GbE -> PIRQ B (MSI capable)
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* D20IP_XHCIIP xHCI -> PIRQ B (MSI capable)
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*
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* D31IP_TTIP Thermal -> PIRQ B
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* D31IP_SMIP SMBUS -> PIRQ A
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* D28IP_* PCIe RP -> PIRQ A-D (MSI capable)
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* D22IP_MEI1IP ME -> PIRQ A (MSI capable)
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*
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* Note, CPU-integrated functions seem to always use PIRQ A.
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*/
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#define _none 0
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DIR_ROUTE(D31IR, PIRQA, PIRQA, PIRQB, PIRQB);
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DIR_ROUTE(D29IR, PIRQC, _none, _none, _none);
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DIR_ROUTE(D28IR, PIRQA, PIRQB, PIRQC, PIRQD);
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DIR_ROUTE(D27IR, PIRQD, _none, _none, _none);
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DIR_ROUTE(D26IR, PIRQD, _none, _none, _none);
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DIR_ROUTE(D25IR, PIRQB, _none, _none, _none);
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DIR_ROUTE(D22IR, PIRQA, _none, _none, _none);
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DIR_ROUTE(D20IR, PIRQB, _none, _none, _none);
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#undef _none
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/* Enable IOAPIC (generic) */
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RCBA16(OIC) = 0x0100;
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/* PCH BWG says to read back the IOAPIC enable register */
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(void) RCBA16(OIC);
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}
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void southbridge_rcba_config(void)
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{
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RCBA32(FD) = PCH_DISABLE_ALWAYS;
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}
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