Mario Scheithauer f76acba3bf siemens/mc_apl3: Enable all PCIe root ports ...

Enable all PCIe root ports for this mainboard.

Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

2018-11-07 16:47:36 +00:00

..

acpi

arch/x86: Add common AMD ACPI hardware definitions

2017-11-10 19:15:38 +00:00

arch

x86/acpi.c: Be more verbose when finding the wakeup vector

2018-11-06 13:52:24 +00:00

commonlib

src: Remove unneeded whitespace

2018-10-23 15:52:09 +00:00

console

console: Set default loglevel to 8 (SPEW) for CONFIG_CHROMEOS

2018-10-18 12:50:41 +00:00

cpu

cpu/amd: Use common AMD's MSR

2018-11-05 09:05:51 +00:00

device

src: Remove unneeded whitespace

2018-10-23 15:52:09 +00:00

drivers

amd: Fix non-local header treated as local

2018-11-05 09:00:26 +00:00

ec

chromeec: Disable battery remaining capacity workaround

2018-11-06 17:38:43 +00:00

include

intel: Get rid of smm_get_pmbase

2018-11-07 07:05:23 +00:00

lib

src/lib/edid: avoid buffer overflow

2018-11-06 14:07:58 +00:00

mainboard

siemens/mc_apl3: Enable all PCIe root ports

2018-11-07 16:47:36 +00:00

northbridge

nb/intel/x4x/raminit: Add missing space

2018-11-05 09:16:07 +00:00

security

src: Add missing include <stdint.h>

2018-11-01 11:25:07 +00:00

soc

soc/amd/stoneyridge: Fix 81+ characters lines

2018-11-07 16:45:35 +00:00

southbridge

southbridge/amd/pi/hudson: Get rid of void pointer math

2018-11-07 16:43:15 +00:00

superio

src: Add missing include <stdint.h>

2018-11-01 11:25:07 +00:00

vendorcode

sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors

2018-11-01 22:24:24 +00:00

Kconfig

reset: Finalize move to new API

2018-10-31 15:29:42 +00:00