b79a04c716
Change-Id: I3d638febddbd88cd4870795f96dd1bbf123c7ba3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33537 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <fsp/soc_binding.h>
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#include <soc/romstage.h>
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#include <stdint.h>
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#include <string.h>
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#include "spd.h"
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static void mainboard_print_spd_info(uint8_t spd[])
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{
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const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
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const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
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const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
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const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
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const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
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const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
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char spd_name[SPD_PART_LEN+1] = { 0 };
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int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
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int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
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int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
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int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
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int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
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int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
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int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
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/* Module type */
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printk(BIOS_INFO, "SPD: module type is ");
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switch (spd[SPD_DRAM_TYPE]) {
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case SPD_DRAM_DDR3:
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printk(BIOS_INFO, "DDR3\n");
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break;
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case SPD_DRAM_LPDDR3:
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printk(BIOS_INFO, "LPDDR3\n");
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break;
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default:
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printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
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break;
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}
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/* Module Part Number */
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memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
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spd_name[SPD_PART_LEN] = 0;
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printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
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printk(BIOS_INFO,
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"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
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banks, ranks, rows, cols, capmb);
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printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
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devw, busw);
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if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
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/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
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printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
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capmb / 8 * busw / devw * ranks);
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}
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}
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/* Fill SPD pointers for on-board memory */
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void spd_memory_init_params(MEMORY_INIT_UPD *memory_params)
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{
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uintptr_t spd_data;
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spd_data = mainboard_get_spd_data();
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/* Make sure a valid SPD was found */
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if (*(uint8_t *)spd_data == 0)
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die("Invalid SPD data.");
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memory_params->MemorySpdPtr00 = spd_data;
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if (mainboard_has_dual_channel_mem())
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memory_params->MemorySpdPtr10 = spd_data;
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mainboard_print_spd_info((uint8_t *)spd_data);
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}
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