system76-coreboot

Files

Arthur Heymans 9d8a4558e3 soc/intel/xeon_sp: Skip locking down TXT related registers

When locking down TXT is skipped, e.g. to do error injection, locking
down DMI3 and IIO DFX related TXT registers should also be skipped.

Change-Id: Ieef25c02ec103eaef65d8b44467ccb9e6917bb6c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50238
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Rocky Phagura
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2021-05-20 16:22:11 +00:00

amd

soc/amd/common: Show espi init in log

2021-05-20 08:00:20 +00:00

cavium

cbfs: Simplify load/map API names, remove type arguments

2020-12-02 22:13:17 +00:00

example

arch/x86: Move prologue to .init section

2021-01-07 11:02:03 +00:00

intel

soc/intel/xeon_sp: Skip locking down TXT related registers