f8ee1806ac
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
68 lines
1.0 KiB
Plaintext
68 lines
1.0 KiB
Plaintext
/*
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* Memory map:
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*
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* _RAMBASE
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* : data segment
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* : bss segment
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* : heap
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* : stack
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* _ROMBASE
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* : coreboot text
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* : readonly text
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*/
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*
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*/
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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* Rewritten by Eric Biederman
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*/
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/*
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* We use ELF as output format. So that we can
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* debug the code in some form.
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/*
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ENTRY(_start)
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*/
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TARGET(binary)
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INPUT(coreboot_ram.rom)
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SECTIONS
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{
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. = _ROMBASE;
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.ram . : {
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_ram = . ;
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coreboot_ram.rom(*)
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_eram = . ;
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}
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/* This section might be better named .setup */
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.rom . : {
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_rom = .;
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*(.rom.text);
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*(.rom.data);
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*(.rom.data.*);
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. = ALIGN(16);
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_erom = .;
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}
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_lrom = LOADADDR(.rom);
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_elrom = LOADADDR(.rom) + SIZEOF(.rom);
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_iseg = _RAMBASE;
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_eiseg = _iseg + SIZEOF(.ram);
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_liseg = _ram;
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_eliseg = _eram;
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/DISCARD/ : {
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*(.comment)
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*(.note)
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}
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}
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