f8ee1806ac
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
65 lines
1.3 KiB
PHP
65 lines
1.3 KiB
PHP
/* For starting coreboot in protected mode */
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#include <arch/rom_segs.h>
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/* .section ".rom.text" */
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.code32
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.align 4
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.globl gdtptr
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/* This is the gdt for ROMCC/ASM part of coreboot.
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* It is different from the gdt in GCC part of coreboot
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* which is defined in c_start.S */
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gdt:
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gdtptr:
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.word gdt_end - gdt -1 /* compute the table limit */
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.long gdt /* we know the offset */
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
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/* selgdt 0x10,flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt_end:
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/*
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* When we come here we are in protected mode. We expand
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* the stack and copies the data segment from ROM to the
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* memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* NOTE aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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.globl protected_start
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protected_start:
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_start
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__protected_start:
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/* Save the BIST value */
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movl %eax, %ebp
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intel_chip_post_macro(0x10) /* post 10 */
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movw $ROM_DATA_SEG, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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/* Restore the BIST value to %eax */
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movl %ebp, %eax
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