f90224845d
Makes it a bit easier to implement mainboard-specific behaviour while executing the bootblock. Change-Id: I04e87f89efb4fad1c0e20b62ea6a50329a286205 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
69 lines
1.4 KiB
C
69 lines
1.4 KiB
C
#include <cpu/x86/lapic/boot_cpu.c>
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#include <arch/cbfs.h>
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#ifdef CONFIG_BOOTBLOCK_CPU_INIT
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#include CONFIG_BOOTBLOCK_CPU_INIT
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#endif
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#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
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#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
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#endif
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#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
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#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
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#endif
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static void bootblock_mainboard_init(void)
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{
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#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
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bootblock_northbridge_init();
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#endif
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#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
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bootblock_southbridge_init();
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#endif
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#ifdef CONFIG_BOOTBLOCK_CPU_INIT
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bootblock_cpu_init();
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#endif
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}
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#if CONFIG_USE_OPTION_TABLE
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#include <pc80/mc146818rtc.h>
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static void sanitize_cmos(void)
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{
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if (cmos_error() || !cmos_chksum_valid()) {
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unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default");
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if (cmos_default) {
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int i;
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cmos_disable_rtc();
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for (i = 14; i < 128; i++) {
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cmos_write(cmos_default[i], i);
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}
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cmos_enable_rtc();
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}
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}
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}
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#endif
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#if CONFIG_CMOS_POST
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#include <pc80/mc146818rtc.h>
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static void cmos_post_init(void)
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{
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u8 magic = CMOS_POST_BANK_0_MAGIC;
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/* Switch to the other bank */
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switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
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case CMOS_POST_BANK_1_MAGIC:
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break;
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case CMOS_POST_BANK_0_MAGIC:
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magic = CMOS_POST_BANK_1_MAGIC;
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break;
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default:
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/* Initialize to zero */
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cmos_write(0, CMOS_POST_BANK_0_OFFSET);
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cmos_write(0, CMOS_POST_BANK_1_OFFSET);
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}
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cmos_write(magic, CMOS_POST_BANK_OFFSET);
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}
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#endif
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