Files
system76-coreboot/src
Tim Wawrzynczak f94405219c soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs
The Alder Lake chip.h file has pcie_rp_config entries for the CPU PCIe
ports, but the UPDs are not set. This patch hooks up those config
structs to the appropriate FSP-S UPDs.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibb2375e66d53b4b7567dbe88b941cd720fdad927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-01-07 19:59:29 +00:00
..
2022-01-01 14:55:51 +00:00
2022-01-01 14:55:51 +00:00