1452c80ee9
Together with the "AMD_XMP" changes, now this board with Crucial BLT8G3D1869DT1TX0 sticks could run at 1600 MT/s CL8 (8-8-9-23) speeds. Earlier only 1333 MT/s CL9 (9-9-10-27) has been possible with coreboot. 1866 MT/s CL9 is impossible on f16kb without northbridge overclocking. tRP in "CL-tRCD-tRP-tRAS" gets set 1 point higher by AGESA because of Errata 638. See more info in a BKDG for AMD Family 16h Models 00h-0Fh. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I7e9f5120421221043f9f9dfe143b51bfa61936be Reviewed-on: https://review.coreboot.org/c/coreboot/+/44462 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
60 lines
2.3 KiB
C
60 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
|
|
#include <vendorcode/amd/agesa/f16kb/AGESA.h>
|
|
|
|
/* Include the files that instantiate the configuration definitions. */
|
|
#include <vendorcode/amd/agesa/f16kb/Include/AdvancedApi.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Include/GnbInterface.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuFamilyTranslation.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuRegisters.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Family/cpuFamRegisters.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuFeatures.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/Table.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.h>
|
|
/* AGESA nonsense: the next three headers depend on heapManager.h */
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/Common/CreateStruct.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEarlyInit.h>
|
|
#include <vendorcode/amd/agesa/f16kb/Proc/CPU/cpuLateInit.h>
|
|
|
|
/* Select the CPU family */
|
|
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
|
|
|
|
/* Select the CPU socket type */
|
|
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
|
|
|
|
//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
|
|
//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
|
|
//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
|
|
#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
|
|
//#define BLDOPT_REMOVE_SRAT FALSE
|
|
#define BLDOPT_REMOVE_WHEA FALSE
|
|
#define BLDOPT_REMOVE_CRAT TRUE
|
|
#define BLDOPT_REMOVE_CDIT TRUE
|
|
|
|
/* Build configuration values here. */
|
|
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_DESKTOP
|
|
|
|
#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY
|
|
#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
|
|
#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
|
|
#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
|
|
#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE
|
|
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
|
|
#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY
|
|
#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE
|
|
#define BLDCFG_ENABLE_ECC_FEATURE FALSE
|
|
#define BLDCFG_ECC_SYNC_FLOOD FALSE
|
|
|
|
/*
|
|
* Specify the default values for the VRM controlling the VDDNB plane.
|
|
* If not specified, the values used for the core VRM will be applied
|
|
*/
|
|
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
|
|
|
|
#define BLDCFG_IOMMU_SUPPORT FALSE
|
|
|
|
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
|
|
|
|
/* AGESA nonsense: this header depends on the definitions above */
|
|
#include <PlatformInstall.h>
|