fa2f793957
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
82 lines
2.1 KiB
Plaintext
82 lines
2.1 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <variant/ec.h>
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, /* DSDT revision: ACPI v2.0 and up */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20110725 /* OEM revision */
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)
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{
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/* Some generic macros */
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#include <soc/intel/cannonlake/acpi/platform.asl>
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/* global NVS and variables */
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#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
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/* CPU */
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#include <cpu/intel/common/acpi/cpu.asl>
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Scope (\_SB) {
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Device (PCI0)
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{
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#include <soc/intel/cannonlake/acpi/northbridge.asl>
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#include <soc/intel/cannonlake/acpi/southbridge.asl>
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}
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/* Per board variant mainboard hooks. */
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#include <variant/acpi/mainboard.asl>
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}
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#if CONFIG(CHROMEOS)
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/* Chrome OS specific */
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#include <vendorcode/google/chromeos/acpi/chromeos.asl>
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/* VPD support */
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#include <vendorcode/google/chromeos/acpi/vpd.asl>
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/* MAC address passthru */
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#include <vendorcode/google/chromeos/acpi/amac.asl>
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#endif
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/* Chipset specific sleep states */
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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/* Low power idle table */
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#include <soc/intel/cannonlake/acpi/lpit.asl>
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/* Chrome OS Embedded Controller */
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Scope (\_SB.PCI0.LPCB)
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{
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/wilco/acpi/superio.asl>
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/* ACPI code for EC functions */
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#include <ec/google/wilco/acpi/ec.asl>
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}
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/* Dynamic Platform Thermal Framework */
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Scope (\_SB)
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{
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/* Per board variant specific definitions. */
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#include <variant/acpi/dptf.asl>
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/* Include soc specific DPTF changes */
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#include <soc/intel/cannonlake/acpi/dptf.asl>
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/* Include common dptf ASL files */
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#include <soc/intel/common/acpi/dptf/dptf.asl>
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}
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}
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