fa2f793957
This patch creates a common instance of globalnvs.asl/nvs.h inside intel common code (soc/intel/common/block/) and ask cnl & icl soc code to refer globalnvs.asl and nvs.h from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify GNVS operation region presence after booting to OS. Change-Id: Ia9fb12a75557bd7dc38f6d22ba2b32065d18b3ee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
51 lines
1.3 KiB
Plaintext
51 lines
1.3 KiB
Plaintext
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2007-2009 coresystems GmbH
|
|
* Copyright (C) 2015 Google Inc.
|
|
* Copyright (C) 2017 Intel Corporation
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*/
|
|
|
|
#include <arch/acpi.h>
|
|
DefinitionBlock(
|
|
"dsdt.aml",
|
|
"DSDT",
|
|
0x02, // DSDT revision: ACPI v2.0 and up
|
|
OEM_ID,
|
|
ACPI_TABLE_CREATOR,
|
|
0x20110725 // OEM revision
|
|
)
|
|
{
|
|
// Some generic macros
|
|
#include <soc/intel/cannonlake/acpi/platform.asl>
|
|
|
|
// global NVS and variables
|
|
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
|
|
|
Scope (\_SB) {
|
|
Device (PCI0)
|
|
{
|
|
#include <soc/intel/cannonlake/acpi/northbridge.asl>
|
|
#include <soc/intel/cannonlake/acpi/southbridge.asl>
|
|
}
|
|
}
|
|
|
|
#if CONFIG(CHROMEOS)
|
|
// Chrome OS specific
|
|
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
|
#endif
|
|
|
|
// Chipset specific sleep states
|
|
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
|
|
|
}
|