fa5d0f835b
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Damien Zammit <damien@zamaudio.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8728f/it8728f.h>
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#define SUPERIO_BASE 0x2e
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#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
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#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
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#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
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void mainboard_pch_lpc_setup(void)
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{
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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}
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void bootblock_mainboard_early_init(void)
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{
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/* Initialize SuperIO */
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot
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/* FIXME: These values could be configured in ramstage */
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ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16
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ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34
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ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port
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ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00
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ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear!
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ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear!
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ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in
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ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable
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ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ?
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ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ?
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ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12)
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/* EC SIO settings */
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ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
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ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
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ite_reg_write(IT8728F_EC, 0xf9, 0x48);
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ite_reg_write(IT8728F_EC, 0x60, 0x0a);
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ite_reg_write(IT8728F_EC, 0x61, 0x30);
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ite_reg_write(IT8728F_EC, 0x62, 0x0a);
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ite_reg_write(IT8728F_EC, 0x63, 0x20);
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ite_reg_write(IT8728F_EC, 0x30, 0x01);
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 5, 0 },
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{ 1, 5, 0 },
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{ 1, 5, 1 },
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{ 1, 5, 1 },
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{ 1, 5, 2 },
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{ 1, 5, 2 },
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{ 1, 5, 3 },
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{ 1, 5, 3 },
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{ 1, 5, 4 },
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{ 1, 5, 4 },
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{ 1, 5, 6 },
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{ 1, 5, 5 },
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{ 1, 5, 5 },
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{ 1, 5, 6 },
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};
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/* FIXME: The GA-B75M-D3V only has two DIMM slots! */
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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read_spd(&spd[0], 0x50, id_only);
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read_spd(&spd[1], 0x51, id_only);
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read_spd(&spd[2], 0x52, id_only);
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read_spd(&spd[3], 0x53, id_only);
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}
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void mainboard_late_rcba_config(void)
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{
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/* Enable HECI */
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RCBA32(FD2) &= ~0x2;
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}
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