fa5d0f835b
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
60 lines
1.6 KiB
C
60 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <device/pci_ops.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <superio/ite/common/ite.h>
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#include <superio/ite/it8728f/it8728f.h>
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#define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO)
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#define SERIAL_DEV PNP_DEV(0x2e, 0x01)
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 0, 0 },
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{ 1, 0, 0 },
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{ 1, 0, 1 },
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{ 1, 0, 1 },
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{ 1, 0, 2 },
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{ 1, 0, 2 },
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{ 1, 0, 3 },
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{ 1, 0, 3 },
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{ 1, 0, 4 },
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{ 1, 0, 4 },
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{ 1, 0, 6 },
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{ 1, 0, 5 },
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{ 1, 0, 5 },
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{ 1, 0, 6 },
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};
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void bootblock_mainboard_early_init(void)
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{
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if (!CONFIG(NO_UART_ON_SUPERIO)) {
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/* Enable serial port */
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ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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/* Disable SIO WDT which kicks in DualBIOS */
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ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E);
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}
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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read_spd(&spd[0], 0x50, id_only);
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read_spd(&spd[2], 0x52, id_only);
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}
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