fa5d0f835b
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
103 lines
2.5 KiB
C
103 lines
2.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <string.h>
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#include <cbfs.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include "ec.h"
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#define SPD_LEN 256
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void mainboard_pch_lpc_setup(void)
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{
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pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
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/* Memory map KB9012 EC registers */
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pci_write_config32(
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PCH_LPC_DEV, LGMR,
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CONFIG_EC_BASE_ADDRESS | 1);
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pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0);
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/* Enable external USB port power. */
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if (CONFIG(USBDEBUG))
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ec_mm_set_bit(0x3b, 4);
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}
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void mainboard_late_rcba_config(void)
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{
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/* Disable devices. */
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RCBA32(BUC) = 0x00000020;
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 1, 0 },
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{ 1, 0, 0 },
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{ 1, 1, 1 },
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{ 1, 0, 1 },
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{ 1, 1, 2 },
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{ 1, 0, 2 },
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{ 0, 0, 3 },
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{ 0, 1, 3 },
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{ 1, 0, 4 },
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{ 1, 1, 4 },
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{ 1, 1, 5 },
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{ 1, 1, 5 },
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{ 1, 1, 6 },
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{ 1, 1, 6 },
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};
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static const char *mainboard_spd_names[9] = {
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"ELPIDA 4GB",
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"SAMSUNG 4GB",
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"HYNIX 4GB",
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"ELPIDA 8GB",
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"SAMSUNG 8GB",
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"HYNIX 8GB",
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"ELPIDA 2GB",
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"SAMSUNG 2GB",
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"HYNIX 2GB",
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};
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void mainboard_get_spd(spd_raw_data *spd, bool id_only)
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{
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void *spd_file;
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size_t spd_file_len = 0;
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const int spd_gpios[] = {71, 70, 16, 48, -1};
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u32 spd_index = get_gpios(spd_gpios);
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if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) {
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/* Fallback to pessimistic 2GB image (ELPIDA 2GB) */
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spd_index = 6;
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}
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printk(BIOS_INFO, "SPD index %d (%s)\n",
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spd_index, mainboard_spd_names[spd_index]);
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/* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */
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spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
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&spd_file_len);
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if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN)
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die("SPD data not found.");
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memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN);
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}
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