fb391fa24c
Add these parameters so that they can be specified in devicetree. BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and rush Change-Id: I77ee16263e1ce6a8c32b3cd203c1b8a499514a8e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3b254936e696f81ca7eeeb7f6968a5350352b59 Original-Change-Id: Iba47afe95c3889047a82582730be7a253fae76e7 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238940 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9611 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA132_CHIP_H__
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#define __SOC_NVIDIA_TEGRA132_CHIP_H__
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#include <soc/addressmap.h>
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#include <stdint.h>
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#include <soc/nvidia/tegra/dc.h>
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struct soc_nvidia_tegra132_config {
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/* Address to monitor if spintable employed. */
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uintptr_t spintable_addr;
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/*
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* panel resolution
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* The two parameters below provides dc about panel spec.
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*/
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u32 xres; /* the width of H display active area */
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u32 yres; /* the height of V display active area */
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u32 framebuffer_bits_per_pixel;
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u32 color_depth; /* color format */
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u64 display_controller; /* dc block base address */
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u32 framebuffer_base;
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/*
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* Technically, we can compute this. At the same time, some platforms
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* might want to specify a specific size for their own reasons. If it
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* is zero the soc code will compute it as
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* xres*yres*framebuffer_bits_per_pixel/8
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*/
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u32 framebuffer_size;
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/*
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* Framebuffer resolution
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* The two parameters below provides dc about framebuffer's sdram size.
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* When they are not the same as panel resolution, we need to program
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* dc's DDA_INCREMENT and some other registers to resize dc output.
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*/
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u32 display_xres;
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u32 display_yres;
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int href_to_sync; /* HSYNC position with respect to line start */
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int hsync_width; /* the width of HSYNC pulses */
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int hback_porch; /* the distance between HSYNC trailing edge to
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beginning of H display active area */
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int hfront_porch; /* the distance between end of H display active
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area to the leading edge of HSYNC */
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int vref_to_sync;
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int vsync_width;
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int vback_porch;
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int vfront_porch;
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int refresh; /* display refresh rate */
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int pixel_clock; /* dc pixel clock source rate */
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u32 panel_bits_per_pixel;
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/* dp specific fields */
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struct {
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/* pwm to use to set display contrast */
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int pwm;
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/* HPD related timing */
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int vdd_to_hpd_delay_ms;
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int hpd_unplug_min_us;
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int hpd_plug_min_us;
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int hpd_irq_min_us;
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/* The minimum link configuraton settings */
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u32 lane_count;
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u32 enhanced_framing;
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u32 link_bw;
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u32 drive_current;
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u32 preemphasis;
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u32 postcursor;
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} dp;
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int win_opt;
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void *dc_data;
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};
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#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */
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