fbdb085549
Change all PCI configuration accesses to MMIO on all boards with SandyBridge and IvyBridge. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: I8f957a80bf57df000897c5a080dd5ff131b1ec0d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3576 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
27 lines
943 B
C
27 lines
943 B
C
#include <arch/io.h>
|
|
|
|
/* Just re-define this instead of including sandybridge.h. It blows up romcc. */
|
|
#define PCIEXBAR 0x60
|
|
|
|
static void bootblock_northbridge_init(void)
|
|
{
|
|
uint32_t reg;
|
|
|
|
/*
|
|
* The "io" variant of the config access is explicitly used to
|
|
* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
|
|
* to true. That way all subsequent non-explicit config accesses use
|
|
* MCFG. This code also assumes that bootblock_northbridge_init() is
|
|
* the first thing called in the non-asm boot block code. The final
|
|
* assumption is that no assembly code is using the
|
|
* CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
|
|
*
|
|
* The PCIEXBAR is assumed to live in the memory mapped IO space under
|
|
* 4GiB.
|
|
*/
|
|
reg = 0;
|
|
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg);
|
|
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
|
|
pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
|
|
}
|