fc29afbdd4
Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
171 lines
3.4 KiB
Plaintext
171 lines
3.4 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Intel Storage Controllers */
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Device (EMMC)
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{
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Name (_ADR, 0x001E0004)
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Name (_DDN, "eMMC Controller")
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Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D"))
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Name (TEMP, 0)
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OperationRegion (EMCR, PCI_Config, 0x00, 0x100)
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Field (EMCR, WordAcc, NoLock, Preserve)
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{
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Offset (0x84), /* PMECTRLSTATUS */
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PMCR, 16,
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Offset (0xa2), /* PG_CONFIG */
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, 2,
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PGEN, 1, /* PG_ENABLE */
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}
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/*
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* Device Specific Method
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* Arg0 - UUID
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* Arg1 - Revision
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* Arg2 - Function Index
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*/
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Method (_DSM, 4)
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{
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If (Arg0 == ^UUID) {
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/*
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* Function 9: Device Readiness Durations
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* Returns a package of five integers covering
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* various device related delay in PCIe Base Spec.
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*/
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If (Arg2 == 9) {
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/*
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* Function 9 support for revision 3.
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* ECN link for function definitions
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* [https://pcisig.com/sites/default/files/
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* specification_documents/
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* ECN_fw_latency_optimization_final.pdf]
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*/
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If (Arg1 == 3) {
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/*
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* Integer 0: FW reset time.
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* Integer 1: FW data link up time.
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* Integer 2: FW functional level reset
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* time.
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* Integer 3: FW D3 hot to D0 time.
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* Integer 4: FW VF enable time.
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* set ACPI constant Ones for elements
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* where overriding the default value
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* is not desired.
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*/
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Return (Package (5) {0, Ones, Ones,
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Ones, Ones})
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}
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}
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}
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Return (Buffer() { 0x00 })
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}
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Method (_PS0, 0, Serialized)
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{
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/* Disable Power Gate */
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^PGEN = 0
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/* Clear bits 31, 6, 2, 0 */
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^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA)
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Sleep (2)
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/* Set bits 31, 6, 2, 0 */
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^^PCRO (PID_SCS, 0x600, 0x80000045)
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/* Set Power State to D0 */
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PMCR &= 0xFFFC
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^TEMP = PMCR
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}
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Method (_PS3, 0, Serialized)
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{
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/* Enable Power Gate */
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^PGEN = 1
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/* Set Power State to D3 */
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PMCR |= 0x0003
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^TEMP = PMCR
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (0)
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}
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}
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}
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#if !CONFIG(EXCLUDE_NATIVE_SD_INTERFACE)
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Device (SDXC)
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{
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Name (_ADR, 0x001E0006)
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Name (_DDN, "SD Controller")
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Name (TEMP, 0)
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OperationRegion (SDCR, PCI_Config, 0x00, 0x100)
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Field (SDCR, WordAcc, NoLock, Preserve)
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{
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Offset (0x84), /* PMECTRLSTATUS */
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PMCR, 16,
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Offset (0xa2), /* PG_CONFIG */
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, 2,
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PGEN, 1, /* PG_ENABLE */
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}
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Method (_PS0, 0, Serialized)
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{
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/* Disable 20K pull-down on CLK, CMD and DAT lines */
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^^PCRA (PID_GPIOCOM3, 0x4c4, 0xFFFFEFFF)
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^^PCRA (PID_GPIOCOM3, 0x4cc, 0xFFFFEFFF)
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^^PCRA (PID_GPIOCOM3, 0x4d4, 0xFFFFEFFF)
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^^PCRA (PID_GPIOCOM3, 0x4dc, 0xFFFFEFFF)
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^^PCRA (PID_GPIOCOM3, 0x4e4, 0xFFFFEFFF)
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^^PCRA (PID_GPIOCOM3, 0x4f4, 0xFFFFEFFF)
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/* Disable Power Gate */
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^PGEN = 0
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/* Clear bits 8, 7, 2, 0 */
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^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A)
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Sleep (2)
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/* Set bits 8, 7, 2, 0 */
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^^PCRO (PID_SCS, 0x600, 0x00000185)
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/* Set Power State to D0 */
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PMCR &= 0xFFFC
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^TEMP = PMCR
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}
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Method (_PS3, 0, Serialized)
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{
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/* Enable Power Gate */
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^PGEN = 1
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/* Set Power State to D3 */
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PMCR |= 0x0003
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^TEMP = PMCR
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/* Enable 20K pull-down on CLK, CMD and DAT lines */
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^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000)
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^^PCRO (PID_GPIOCOM3, 0x4cc, 0x00001000)
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^^PCRO (PID_GPIOCOM3, 0x4d4, 0x00001000)
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^^PCRO (PID_GPIOCOM3, 0x4dc, 0x00001000)
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^^PCRO (PID_GPIOCOM3, 0x4e4, 0x00001000)
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^^PCRO (PID_GPIOCOM3, 0x4f4, 0x00001000)
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}
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Device (CARD)
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{
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Name (_ADR, 0x00000008)
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Method (_RMV, 0, NotSerialized)
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{
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Return (1)
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}
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}
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}
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#endif
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