fc706437cb
On Broadwell, this reduces the number of 'remarks' in the IASL build
from 222 to 3.
Fixes these remarks:
Object is not referenced (Name is within method [_CRS])
The ACPI compiler is trying to be helpful in letting us know
that we're not using various fields in the MCRS ResourceTemplate
when we define it inside of the _CRS method. Since we're not
intending to use those objects in the method, it shouldn't be an
issue, but the warning is annoying and can mask real issues.
Moving the creation of the MCRS object to outside of the CRS
method and referencing it from there solves this problem.
This change was made for fsp_baytrail in commit 2eaa0d49
fsp_baytrail: Fix ACPI 'Object is not referenced' warnings
Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11268
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
213 lines
6.1 KiB
Plaintext
213 lines
6.1 KiB
Plaintext
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <soc/iomap.h>
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Name (_HID, EISAID ("PNP0A08")) // PCIe
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Name (_CID, EISAID ("PNP0A03")) // PCI
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Name (_ADR, 0)
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Name (_BBN, 0)
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Device (MCHC)
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{
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Name (_ADR, 0x00000000) // 0:0.0
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OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
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Field (MCHP, DWordAcc, NoLock, Preserve)
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{
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Offset (0x70), // ME Base Address
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MEBA, 64,
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Offset (0xa0), // Top of Used Memory
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TOM, 64,
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Offset (0xbc), // Top of Low Used Memory
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TLUD, 32,
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}
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}
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// Current Resource Settings
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Name (MCRS, ResourceTemplate()
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{
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// Bus Numbers
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WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
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0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
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// IO Region 0
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
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// PCI Config Space
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Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
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// IO Region 1
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DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
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// VGA memory (0xa0000-0xbffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
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0x00020000,,, ASEG)
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// OPROM reserved (0xc0000-0xc3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
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0x00004000,,, OPR0)
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// OPROM reserved (0xc4000-0xc7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
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0x00004000,,, OPR1)
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// OPROM reserved (0xc8000-0xcbfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
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0x00004000,,, OPR2)
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// OPROM reserved (0xcc000-0xcffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
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0x00004000,,, OPR3)
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// OPROM reserved (0xd0000-0xd3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
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0x00004000,,, OPR4)
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// OPROM reserved (0xd4000-0xd7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
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0x00004000,,, OPR5)
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// OPROM reserved (0xd8000-0xdbfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
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0x00004000,,, OPR6)
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// OPROM reserved (0xdc000-0xdffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
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0x00004000,,, OPR7)
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// BIOS Extension (0xe0000-0xe3fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
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0x00004000,,, ESG0)
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// BIOS Extension (0xe4000-0xe7fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
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0x00004000,,, ESG1)
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// BIOS Extension (0xe8000-0xebfff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
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0x00004000,,, ESG2)
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// BIOS Extension (0xec000-0xeffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000ec000, 0x000effff, 0x00000000,
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0x00004000,,, ESG3)
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// System BIOS (0xf0000-0xfffff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
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0x00010000,,, FSEG)
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// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x00000000,,, PM01)
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// TPM Area (0xfed40000-0xfed44fff)
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
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Cacheable, ReadWrite,
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0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
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0x00005000,,, TPMR)
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})
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Method (_CRS, 0, Serialized)
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{
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// Find PCI resource area in MCRS
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CreateDwordField(MCRS, ^PM01._MIN, PMIN)
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CreateDwordField(MCRS, ^PM01._MAX, PMAX)
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CreateDwordField(MCRS, ^PM01._LEN, PLEN)
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// Fix up PCI memory region
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// Start with Top of Lower Usable DRAM
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Store (^MCHC.TLUD, Local0)
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Store (^MCHC.MEBA, Local1)
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// Check if ME base is equal
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If (LEqual (Local0, Local1)) {
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// Use Top Of Memory instead
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Store (^MCHC.TOM, Local0)
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}
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Store (Local0, PMIN)
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Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
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Add(Subtract(PMAX, PMIN), 1, PLEN)
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Return (MCRS)
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}
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/* PCI Device Resource Consumption */
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Device (PDRC)
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{
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Name (_HID, EISAID("PNP0C02"))
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Name (_UID, 1)
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Name (PDRS, ResourceTemplate() {
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Memory32Fixed (ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
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Memory32Fixed (ReadWrite, MCH_BASE_ADDRESS, MCH_BASE_SIZE)
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Memory32Fixed (ReadWrite, DMI_BASE_ADDRESS, DMI_BASE_SIZE)
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Memory32Fixed (ReadWrite, EP_BASE_ADDRESS, EP_BASE_SIZE)
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Memory32Fixed (ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
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Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
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Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
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})
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// Current Resource Settings
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Method (_CRS, 0, Serialized)
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{
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Return (PDRS)
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}
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}
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/* PCI IRQ assignment */
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#include "pci_irqs.asl"
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/* Configurable TDP */
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#include "ctdp.asl"
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