fc709fee09
Instead of using the PSTATE SSDT generated by binaryPI, use the common AMD code by selecting SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE. To match the SSDT from binaryPI, set ACPI_SSDT_PSD_INDEPENDENT to n. There are two differences to the binaryPI SSDT: Now coreboot includes the C1 state in the _CST package instead of just having the kernel add this due to the ACPI_FADT_C1_SUPPORTED bit being set and the address of the PS_STS_REG P state status MSR is written to the corresponding field of the _PCT package instead of being 0. TEST=On Careena the new P and C state ACPI packages are nearly identical to the ones from the SSDT from binaryPI with the two functional differences mentioned above. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icdf6bc8f0e0363f185a294ab84edcb51322e7eb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* ACPI - create the Fixed ACPI Description Tables (FADT)
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*/
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#include <console/console.h>
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#include <acpi/acpi.h>
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#include <acpi/acpigen.h>
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#include <device/pci_ops.h>
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#include <arch/ioapic.h>
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#include <arch/smp/mpspec.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <gpio.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/cpu.h>
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#include <amdblocks/ioapic.h>
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#include <soc/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/southbridge.h>
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#include <soc/northbridge.h>
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#include <version.h>
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* create all subtables for processors */
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current = acpi_create_madt_lapics_with_nmis(current);
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/* Write Kern IOAPIC, only one */
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current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC_ADDR);
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current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR);
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/* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current,
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MP_BUS_ISA, 0, 2,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT);
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/* SCI IRQ type override */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current,
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MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ,
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MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
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return current;
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}
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/*
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* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
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* in the ACPI 3.0b specification.
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*/
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
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fadt->sci_int = ACPI_SCI_IRQ;
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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}
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fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
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fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
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fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
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fadt->gpe0_blk = ACPI_GPE0_BLK;
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fadt->pm1_evt_len = 4; /* 32 bits */
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fadt->pm1_cnt_len = 2; /* 16 bits */
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fadt->pm_tmr_len = 4; /* 32 bits */
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fadt->gpe0_blk_len = 8; /* 64 bits */
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fill_fadt_extended_pm_regs(fadt);
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/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
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overridden by the _CST packages in the PSTATE SSDT. */
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
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fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
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fadt->day_alrm = RTC_DATE_ALARM;
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fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */
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fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */
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ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_SLEEP_BUTTON |
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_32BIT_TIMER |
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ACPI_FADT_PCI_EXPRESS_WAKE |
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ACPI_FADT_PLATFORM_CLOCK |
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ACPI_FADT_S4_RTC_VALID |
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ACPI_FADT_REMOTE_POWER_ON;
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}
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const acpi_cstate_t cstate_cfg_table[] = {
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[0] = {
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.ctype = 1,
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.latency = 1,
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.power = 0,
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},
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[1] = {
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.ctype = 2,
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.latency = 400,
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.power = 0,
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},
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};
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const acpi_cstate_t *get_cstate_config_data(size_t *size)
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{
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*size = ARRAY_SIZE(cstate_cfg_table);
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return cstate_cfg_table;
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}
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