git-svn-id: svn://svn.coreboot.org/coreboot/trunk@783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
		
			
				
	
	
		
			253 lines
		
	
	
		
			3.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			253 lines
		
	
	
		
			3.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| void land_test(void)
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| {
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| 	int i;
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| 	i = 1 && 2;
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| }
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| void lor_test(void)
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| {
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| 	int i;
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| 	i = 1 || 2;
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| }
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| 
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| void outb(unsigned char value, unsigned short port)
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| {
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| 	__builtin_outb(value, port);
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| }
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| 
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| unsigned char inb(unsigned short port)
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| {
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| 	return __builtin_inb(port);
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| }
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| 
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| static unsigned int config_cmd2(unsigned char bus, unsigned devfn, unsigned where)
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| {
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| 	return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3)  ;
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| }
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| 
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| /* Base Address */
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| #ifndef TTYS0_BASE
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| #define TTYS0_BASE 0x3f8
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| #endif
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| 
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| #ifndef TTYS0_BAUD
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| #define TTYS0_BAUD 115200
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| #endif
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| 
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| #if ((115200%TTYS0_BAUD) != 0)
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| #error Bad ttys0 baud rate
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| #endif
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| 
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| #define TTYS0_DIV	(115200/TTYS0_BAUD)
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| 
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| /* Line Control Settings */
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| #ifndef TTYS0_LCS
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| /* Set 8bit, 1 stop bit, no parity */
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| #define TTYS0_LCS	0x3
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| #endif
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| 
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| #define UART_LCS	TTYS0_LCS
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| 
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| /* Data */
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| #define UART_RBR 0x00
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| #define UART_TBR 0x00
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| 
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| /* Control */
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| #define UART_IER 0x01
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| #define UART_IIR 0x02
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| #define UART_FCR 0x02
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| #define UART_LCR 0x03
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| #define UART_MCR 0x04
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| #define UART_DLL 0x00
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| #define UART_DLM 0x01
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| 
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| /* Status */
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| #define UART_LSR 0x05
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| #define UART_MSR 0x06
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| #define UART_SCR 0x07
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| 
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| int uart_can_tx_byte(void)
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| {
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| 	return inb(TTYS0_BASE + UART_LSR) & 0x20;
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| }
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| 
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| void uart_wait_to_tx_byte(void)
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| {
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| 	while(!uart_can_tx_byte())
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| 		;
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| }
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| 
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| void uart_wait_until_sent(void)
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| {
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| 	while(!(inb(TTYS0_BASE + UART_LSR) & 0x40)) 
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| 		;
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| }
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| 
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| void uart_tx_byte(unsigned char data)
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| {
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| 	uart_wait_to_tx_byte();
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| 	outb(data, TTYS0_BASE + UART_TBR);
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| 	/* Make certain the data clears the fifos */
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| 	uart_wait_until_sent();
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| }
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| 
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| void dummy(void)
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| {
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| 	uart_tx_byte(5);
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| }
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| 
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| #define PIIX4_DEVFN 0x90
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| #define SMBUS_MEM_DEVICE_START 0x50
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| #define SMBUS_MEM_DEVICE_END 0x53
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| #define SMBUS_MEM_DEVICE_INC 1
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| 
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| 
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| #define PM_BUS 0
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| #define PM_DEVFN (PIIX4_DEVFN+3)
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| 
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| #define SMBUS_IO_BASE 0x1000
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| #define SMBHSTSTAT 0
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| #define SMBHSTCTL  2
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| #define SMBHSTCMD  3
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| #define SMBHSTADD  4
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| #define SMBHSTDAT0 5
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| #define SMBHSTDAT1 6
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| #define SMBBLKDAT  7
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| 
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| static void smbus_wait_until_done(void)
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| {
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| 	unsigned char byte;
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| 	do {
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| 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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| 	}while((byte &1) == 1);
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| #if 1
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| 	while( (byte & ~1) == 0) {
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| 		byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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| 	}
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| #endif
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| }
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| 
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| #if 0
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| void ifthenelse(void)
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| {
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| 	int i;
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| 	if (5 > 2) {
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| 		i = 1;
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| 	}
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| 	else {
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| 		i = 2;
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| 	}
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| 	i = i + 3;
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| }
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| #endif
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| #if 0
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| static int add(int left, int right)
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| {
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| 	{
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| 		return left + right;
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| 	}
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| }
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| #else
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| #if 0
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| static int add(int left, int right)
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| {
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| 	return left + right;
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| }
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| #endif
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| #endif
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| 
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| #if 0
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| static void assign(void)
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| {
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| 	int i, j;
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| 	i = j = 1;
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| }
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| #endif
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| 
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| #if 0
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| static void and(void)
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| {
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| 	int i, j, k;
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| 	i = 1;
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| 	j = 2;
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| 	k = i && j;
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| 	
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| }
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| static void and_test(void)
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| {
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| 	and();
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| }
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| #endif
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| #if 0
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| #define INC_TEST 2
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| static void inc(void)
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| {
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| 	int i;
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| 	i = 5;
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| #if (INC_TEST == 1)
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| 	i += 7;
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| #endif
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| #if (INC_TEST == 2)
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| 	++i;
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| #endif
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| #if (INC_TEST == 3)
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| 	i++;
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| #endif
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| }
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| 
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| #if 0
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| static void inc_test(void)
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| {
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| 	inc();
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| }
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| #endif
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| #endif
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| #if 0
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| static void loop(void)
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| {
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| 	int i;
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| 	for(i = 0; i < 10; i++) {
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| 		;
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| 	} while(i < 10);
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| }
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| 
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| static void loop_test(void)
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| {
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| 	loop();
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| }
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| #endif
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| 
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| #if 0
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| static void simple(void)
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| {
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| 	add(1,2);
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| }
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| #endif
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| 
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| #if 0
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| static void fun(void)
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| {
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| 	int bar;
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| 	bar = add(1, 2);
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| }
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| #endif
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| 
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| 
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| #if 0
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| static void func(void)
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| {
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| 	int bar, baz;
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|  	int i; 
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|   
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| 	baz = add(1, 2); 
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| 	baz = add(1, 2);
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| 	bar = 1;
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| 	baz = 2;
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| 	for(i = 0; i < 10; i = i + 1) {
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| 		baz = i;
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| 	}
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| 	bar = 1 + 2 * 3;
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| 	bar = add(3, 4);
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| 	bar = add(bar, baz);
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| }
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| #endif
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