fd9defc0ca
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
105 lines
3.1 KiB
ArmAsm
105 lines
3.1 KiB
ArmAsm
/*
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* Early initialization code for ARMv7 architecture.
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*
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* This file is based off of the OMAP3530/ARM Cortex start.S file from Das
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* U-Boot, which itself got the file from armboot.
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*
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* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
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* Copyright (c) 2013 The Chromium OS Authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <arch/asm.h>
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.section ".start", "a", %progbits
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.arm
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ENTRY(_start)
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/*
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* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
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* aborts may happen early and crash before the abort handlers are
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* installed, but at least the problem will show up near the code that
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* causes it.
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*/
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msr cpsr_cxf, #0xdf
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bl _thumb_start
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ENDPROC(_start)
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.thumb
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ENTRY(_thumb_start)
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bl arm_init_caches
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/*
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* From Cortex-A Series Programmer's Guide:
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* Only CPU 0 performs initialization. Other CPUs go into WFI
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* to do this, first work out which CPU this is
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* this code typically is run before any other initialization step
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*/
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mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register
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and r1, r1, #0x3 @ Extract CPU ID bits
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cmp r1, #0
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bne wait_for_interrupt @ If this is not core0, wait
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/*
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* Initialize the stack to a known value. This is used to check for
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* stack overflow later in the boot process.
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*/
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ldr r0, .Stack
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ldr r1, .Stack_size
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sub r0, r0, r1
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ldr r1, .Stack
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ldr r2, =0xdeadbeef
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init_stack_loop:
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str r2, [r0]
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add r0, #4
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cmp r0, r1
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bne init_stack_loop
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/* Set stackpointer in internal RAM to call bootblock main() */
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call_bootblock:
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ldr sp, .Stack /* Set up stack pointer */
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ldr r0,=0x00000000
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/*
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* The current design of cpu_info places the struct at the top of the
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* stack. Free enough space to accomodate for that, but make sure it's
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* 8-byte aligned for ABI compliance.
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*/
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sub sp, sp, #16
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bl main
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wait_for_interrupt:
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wfi
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mov pc, lr @ back to my caller
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ENDPROC(_thumb_start)
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/* we do it this way because it's a 32-bit constant and
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* in some cases too far away to be loaded as just an offset
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* from IP
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*/
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.align 2
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.Stack:
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.word CONFIG_STACK_TOP
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.align 2
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/* create this size the same way we do in coreboot_ram.ld: top-bottom */
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.Stack_size:
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.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM
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