fe481eb3e5
Use a name consistent with the more recent soc/intel. Change-Id: Ie69583f28f384eb49517203e1c3867f27e6272de Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
133 lines
3.6 KiB
C
133 lines
3.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <device/pci_ops.h>
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#include <arch/cpu.h>
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#include <cbmem.h>
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#include "i945.h"
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#include <console/console.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include <stdint.h>
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#include <stage_cache.h>
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/* Decodes TSEG region size to bytes. */
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u32 decode_tseg_size(const u8 esmramc)
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{
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if (!(esmramc & 1))
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return 0;
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switch ((esmramc >> 1) & 3) {
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case 0:
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return 1 << 20;
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case 1:
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return 2 << 20;
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case 2:
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return 8 << 20;
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case 3:
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default:
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die("Bad TSEG setting.\n");
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}
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}
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u32 northbridge_get_tseg_base(void)
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{
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uintptr_t tom;
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if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
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/* IGD enabled, get top of Memory from BSM register */
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tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
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else
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tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
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/* subsctract TSEG size */
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tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC));
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return tom;
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}
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u32 northbridge_get_tseg_size(void)
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{
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const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
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return decode_tseg_size(esmramc);
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}
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/*
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* Depending of UMA and TSEG configuration, TSEG might start at any
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* 1 MiB alignment. As this may cause very greedy MTRR setup, push
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* CBMEM top downwards to 4 MiB boundary.
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*/
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void *cbmem_top(void)
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{
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uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
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return (void *) top_of_ram;
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}
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/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
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u32 decode_igd_memory_size(const u32 gms)
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{
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static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32,
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48, 64 };
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if (gms >= ARRAY_SIZE(ggc2uma))
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die("Bad Graphics Mode Select (GMS) setting.\n");
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return ggc2uma[gms] << 10;
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}
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void stage_cache_external_region(void **base, size_t *size)
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{
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/* The stage cache lives at the end of the TSEG region.
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* The top of RAM is defined to be the TSEG base address.
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*/
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)((uintptr_t)northbridge_get_tseg_base()
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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}
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/* platform_enter_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache 8 MiB region below the top of ram and 2 MiB above top of
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* ram to cover both cbmem as the TSEG region.
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*/
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
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northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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/* We do not return here. */
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}
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