Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
127 lines
3.5 KiB
Plaintext
127 lines
3.5 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/i945
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# IGD Displays
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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register "gpu_hotplug" = "0x00000220"
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register "gpu_lvds_use_spread_spectrum_clock" = "1"
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register "pwm_freq" = "180"
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register "gpu_panel_power_up_delay" = "250"
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register "gpu_panel_power_backlight_on_delay" = "2380"
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register "gpu_panel_power_down_delay" = "250"
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register "gpu_panel_power_backlight_off_delay" = "2380"
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register "gpu_panel_power_cycle_delay" = "2"
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device cpu_cluster 0 on
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chip cpu/intel/socket_m
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device lapic 0 on end
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end
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end
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register "pci_mmio_size" = "768"
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device domain 0 on
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device pci 00.0 on # Host bridge
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subsystemid 0x8086 0x7270
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end
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device pci 02.0 on # VGA controller
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subsystemid 0x8086 0x7270
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end
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device pci 02.1 on # display controller
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subsystemid 0x17aa 0x201a
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end
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x0b"
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi1_routing" = "2"
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register "gpi7_routing" = "2"
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register "sata_ports_implemented" = "0x04"
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register "gpe0_en" = "0x11000006"
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register "alt_gp_smi_en" = "0x1000"
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register "ide_enable_primary" = "1"
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register "ide_enable_secondary" = "1"
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register "c4onc3_enable" = "1"
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register "c3_latency" = "0x23"
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register "p_cnt_throttling_supported" = "1"
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register "gen1_dec" = "0x000c0681"
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register "gen2_dec" = "0x000c1641"
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register "gen4_dec" = "0x001c0301"
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device pci 1b.0 on # Audio Controller
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subsystemid 0x8384 0x7680
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end
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device pci 1c.0 on end # Ethernet
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device pci 1c.1 on end # Atheros WLAN
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device pci 1c.2 off end # PCIe #3
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device pci 1c.3 off end # PCIe #4
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device pci 1c.4 off end # PCIe #5
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device pci 1c.5 off end # PCIe #6
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device pci 1d.0 on # USB UHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1d.1 on # USB UHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1d.2 on # USB UHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1d.3 on # USB UHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1d.7 on # USB2 EHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1e.0 on end # PCI bridge
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device pci 1e.2 off end # AC'97 Audio
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device pci 1e.3 off end # AC'97 Modem
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device pci 1f.0 on # PCI-LPC bridge
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subsystemid 0x8086 0x7270
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end
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device pci 1f.1 on # IDE
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subsystemid 0x8086 0x7270
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end
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device pci 1f.2 on # SATA
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subsystemid 0x8086 0x7270
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end
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device pci 1f.3 on # SMBUS
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subsystemid 0x8086 0x7270
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end
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end
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end
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end
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