fee73df07a
The name is derived directly from the device path. Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1471 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
44 lines
2.0 KiB
C
44 lines
2.0 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _SOUTHBRIDGE_AMD_CS5536
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#define _SOUTHBRIDGE_AMD_CS5536
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#define MAX_UNWANTED_VPCI 8 /* increase if needed */
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struct southbridge_amd_cs5536_config {
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unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */
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unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */
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unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */
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unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
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unsigned char enable_ide_nand_flash; /* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */
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unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */
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unsigned int enable_USBP4_overcurrent; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */
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unsigned char com1_enable; /* enable COM1 */
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unsigned int com1_address; /* e.g. 0x3F8 */
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unsigned int com1_irq; /* e.g. 4 */
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unsigned char com2_enable; /* enable COM2 */
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unsigned int com2_address; /* e.g. 0x2F8 */
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unsigned int com2_irq; /* e.g. 3 */
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unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */
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};
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#endif /* _SOUTHBRIDGE_AMD_CS5536 */
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