Files
system76-coreboot/src/soc/intel/jasperlake/acpi/southbridge.asl
Tim Wawrzynczak 77b36abcf6 soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch jasperlake boards to this method.

soc/intel/jasperlake: Switch to acpigen PEPD

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-10 21:57:35 +00:00

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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <intelblocks/itss.h>
#include <intelblocks/pcr.h>
#include <soc/itss.h>
#include <soc/pcr_ids.h>
/* PCI IRQ assignment */
#include "pci_irqs.asl"
/* PCR access */
#include <soc/intel/common/acpi/pcr.asl>
/* PCH clock */
#include "camera_clock_ctl.asl"
/* GPIO controller */
#include "gpio.asl"
/* ESPI 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
/* PCH HDA */
#include "pch_hda.asl"
/* PCIE Ports */
#include "pcie.asl"
/* pmc 0:1f.2 */
#include "pmc.asl"
/* Serial IO */
#include "serialio.asl"
/* SMBus 0:1f.4 */
#include <soc/intel/common/block/acpi/acpi/smbus.asl>
/* ISH 0:12.0 */
#include <soc/intel/common/block/acpi/acpi/ish.asl>
/* USB XHCI 0:14.0 */
#include "xhci.asl"
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
/* EMMC/SD card */
#include "scs.asl"
/* GbE 0:1f.6 */
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>