77b36abcf6
The pep.asl file is being obsoleted by runtime generation, therefore switch jasperlake boards to this method. soc/intel/jasperlake: Switch to acpigen PEPD Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
120 lines
3.2 KiB
C
120 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootstate.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <intelblocks/acpi.h>
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#include <intelblocks/pmc.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/soc_chip.h>
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static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
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{
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uint32_t reg;
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uint8_t *pmcbase = pmc_mmio_regs();
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printk(BIOS_DEBUG, "%sabling Deep S%c\n",
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enable ? "En" : "Dis", sx + '0');
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reg = read32(pmcbase + offset);
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if (enable)
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reg |= mask;
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else
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reg &= ~mask;
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write32(pmcbase + offset, reg);
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}
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static void config_deep_s5(int on_ac, int on_dc)
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{
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/* Treat S4 the same as S5. */
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config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac);
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config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc);
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config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac);
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config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc);
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}
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static void config_deep_s3(int on_ac, int on_dc)
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{
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config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac);
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config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc);
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}
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static void config_deep_sx(uint32_t deepsx_config)
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{
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uint32_t reg;
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uint8_t *pmcbase = pmc_mmio_regs();
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reg = read32(pmcbase + DSX_CFG);
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reg &= ~DSX_CFG_MASK;
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reg |= deepsx_config;
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write32(pmcbase + DSX_CFG, reg);
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}
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static void pmc_init(struct device *dev)
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{
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const config_t *config = config_of_soc();
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rtc_init();
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pmc_set_power_failure_state(true);
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pmc_gpe_init();
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config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc);
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config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc);
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config_deep_sx(config->deep_sx_config);
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}
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static void soc_pmc_read_resources(struct device *dev)
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{
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struct resource *res;
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mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
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res = new_resource(dev, 1);
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res->base = (resource_t)ACPI_BASE_ADDRESS;
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res->size = (resource_t)ACPI_BASE_SIZE;
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res->limit = res->base + res->size + 1;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static void soc_acpi_mode_init(struct device *dev)
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{
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/*
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* pmc_set_acpi_mode() should be delayed until BS_DEV_INIT in order
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* to ensure the ordering does not break the assumptions that other
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* drivers make about ACPI mode (e.g. Chrome EC). Since it disables
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* ACPI mode, other drivers may take different actions based on this
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* (e.g. Chrome EC will flush any pending hostevent bits). Because
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* JSL has its PMC device available for device_operations, it can be
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* done from the "ops->init" callback.
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*/
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pmc_set_acpi_mode();
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}
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static void pm1_enable_pwrbtn_smi(void *unused)
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{
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/* Enable power button SMI after BS_DEV_INIT_CHIPS (FSP-S) is done. */
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pmc_update_pm1_enable(PWRBTN_EN);
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}
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
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static void pmc_fill_ssdt(const struct device *dev)
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{
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if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP))
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generate_acpi_power_engine();
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}
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struct device_operations pmc_ops = {
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.read_resources = soc_pmc_read_resources,
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.set_resources = noop_set_resources,
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.init = soc_acpi_mode_init,
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.enable = pmc_init,
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#if CONFIG(HAVE_ACPI_TABLES)
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.acpi_fill_ssdt = pmc_fill_ssdt,
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#endif
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};
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