IntelFsp2Pkg: FspSecCore support for X64

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893
1.Added FspSecCore support for X64.
2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported.
3.Corrected few typos.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>

IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm

@@ -1,12 +1,14 @@
 ;; @file
 ;  Provide FSP API entry points.
 ;
-; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>
 ; SPDX-License-Identifier: BSD-2-Clause-Patent
 ;;
 
     SECTION .text
 
+STACK_SAVED_EAX_OFFSET       EQU   4 * 7 ; size of a general purpose register * eax index
+
 ;
 ; Following functions will be provided in C
 ;
@@ -52,7 +54,7 @@ FspApiCommon1:
   add    esp, 8
   cmp    eax, 0
   jz     FspApiCommon2
-  mov    dword  [esp + (4 * 7)], eax
+  mov    dword  [esp + STACK_SAVED_EAX_OFFSET], eax
   popad
 exit:
   ret