IntelFsp2Pkg: FspSecCore support for X64
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Ted Kuo
mergify[bot]
@@ -2,11 +2,13 @@
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Intel FSP Header File definition from Intel Firmware Support Package External
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Architecture Specification v2.0 and above.
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Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#ifndef __FSP_HEADER_FILE_H__
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#define __FSP_HEADER_FILE_H__
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@@ -24,6 +26,12 @@
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#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
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#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0
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#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
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#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2
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#define FSP_IA32 0
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#define FSP_X64 1
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#pragma pack(1)
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///
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@@ -49,7 +57,7 @@ typedef struct {
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UINT8 SpecVersion;
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///
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/// Byte 0x0B: Revision of the FSP Information Header.
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/// The Current value for this field is 0x6.
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/// The Current value for this field is 0x7.
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///
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UINT8 HeaderRevision;
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///
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@@ -82,6 +90,10 @@ typedef struct {
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UINT32 ImageBase;
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///
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/// Byte 0x20: Attribute for the FSP binary.
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/// Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display.
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/// Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4.
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/// Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7.
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/// Bits 15:3 - Reserved
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///
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UINT16 ImageAttribute;
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///
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284
IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
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284
IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
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@@ -0,0 +1,284 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Abstract:
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;
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; Provide macro for register save/restore using SSE registers
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;
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;------------------------------------------------------------------------------
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;
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; Define SSE and AVX instruction set
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;
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;
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; Define SSE macros using SSE 4.1 instructions
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; args 1:XMM, 2:IDX, 3:REG
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;
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%macro SXMMN 3
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pinsrq %1, %3, (%2 & 3)
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%endmacro
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;
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; args 1:XMM, 2:REG, 3:IDX
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;
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%macro LXMMN 3
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pextrq %2, %1, (%3 & 3)
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%endmacro
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;
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; Define AVX macros using AVX instructions
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; Save XMM to YMM
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; args 1:YMM, 2:IDX (0 - lower 128bits, 1 - upper 128bits), 3:XMM
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;
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%macro SYMMN 3
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vinsertf128 %1, %1, %3, %2
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%endmacro
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;
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; Restore XMM from YMM
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; args 1:YMM, 2:XMM, 3:IDX (0 - lower 128bits, 1 - upper 128bits)
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;
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%macro LYMMN 3
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vextractf128 %2, %1, %3
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%endmacro
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;
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; Upper half of YMM7 to save RBP and RBX. Upper half of YMM8 to save RSI and RDI.
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; Modified: XMM5, YMM6, YMM7 and YMM8
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;
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%macro SAVE_REGS 0
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SXMMN xmm5, 0, rbp
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SXMMN xmm5, 1, rbx
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SYMMN ymm7, 1, xmm5
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SXMMN xmm5, 0, rsi
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SXMMN xmm5, 1, rdi
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SYMMN ymm8, 1, xmm5
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SAVE_RSP
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%endmacro
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;
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; Upper half of YMM7 to restore RBP and RBX. Upper half of YMM8 to restore RSI and RDI.
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; Modified: XMM5, RBP, RBX, RSI, RDI and RSP
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;
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%macro LOAD_REGS 0
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LYMMN ymm7, xmm5, 1
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LXMMN xmm5, rbp, 0
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LXMMN xmm5, rbx, 1
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LYMMN ymm8, xmm5, 1
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LXMMN xmm5, rsi, 0
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LXMMN xmm5, rdi, 1
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LOAD_RSP
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%endmacro
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;
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; Restore RBP from YMM7[128:191]
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; Modified: XMM5 and RBP
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;
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%macro LOAD_RBP 0
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LYMMN ymm7, xmm5, 1
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movq rbp, xmm5
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%endmacro
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;
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; Restore RBX from YMM7[192:255]
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; Modified: XMM5 and RBX
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;
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%macro LOAD_RBX 0
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LYMMN ymm7, xmm5, 1
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LXMMN xmm5, rbx, 1
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%endmacro
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;
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; Upper half of YMM6 to save/restore Time Stamp, RSP
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;
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;
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; Save Time Stamp to YMM6[192:255]
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; arg 1:general purpose register which holds time stamp
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; Modified: XMM5 and YMM6
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;
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%macro SAVE_TS 1
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LYMMN ymm6, xmm5, 1
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SXMMN xmm5, 1, %1
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SYMMN ymm6, 1, xmm5
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%endmacro
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;
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; Restore Time Stamp from YMM6[192:255]
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; arg 1:general purpose register where to save time stamp
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; Modified: XMM5 and %1
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;
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%macro LOAD_TS 1
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LYMMN ymm6, xmm5, 1
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LXMMN xmm5, %1, 1
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%endmacro
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;
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; Save RSP to YMM6[128:191]
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; Modified: XMM5 and YMM6
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;
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%macro SAVE_RSP 0
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LYMMN ymm6, xmm5, 1
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SXMMN xmm5, 0, rsp
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SYMMN ymm6, 1, xmm5
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%endmacro
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;
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; Restore RSP from YMM6[128:191]
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; Modified: XMM5 and RSP
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;
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%macro LOAD_RSP 0
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LYMMN ymm6, xmm5, 1
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movq rsp, xmm5
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%endmacro
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;
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; Upper half of YMM9 to save/restore UCODE status, BFV address
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;
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;
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; Save uCode status to YMM9[192:255]
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; arg 1:general purpose register which holds uCode status
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; Modified: XMM5 and YMM9
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;
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%macro SAVE_UCODE_STATUS 1
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LYMMN ymm9, xmm5, 1
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SXMMN xmm5, 0, %1
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SYMMN ymm9, 1, xmm5
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%endmacro
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;
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; Restore uCode status from YMM9[192:255]
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; arg 1:general purpose register where to save uCode status
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; Modified: XMM5 and %1
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;
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%macro LOAD_UCODE_STATUS 1
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LYMMN ymm9, xmm5, 1
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movq %1, xmm5
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%endmacro
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;
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; Save BFV address to YMM9[128:191]
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; arg 1:general purpose register which holds BFV address
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; Modified: XMM5 and YMM9
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;
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%macro SAVE_BFV 1
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LYMMN ymm9, xmm5, 1
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SXMMN xmm5, 1, %1
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SYMMN ymm9, 1, xmm5
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%endmacro
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;
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; Restore BFV address from YMM9[128:191]
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; arg 1:general purpose register where to save BFV address
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; Modified: XMM5 and %1
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;
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%macro LOAD_BFV 1
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LYMMN ymm9, xmm5, 1
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LXMMN xmm5, %1, 1
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%endmacro
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;
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; YMM7[128:191] for calling stack
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; arg 1:Entry
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; Modified: RSI, XMM5, YMM7
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;
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%macro CALL_YMM 1
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mov rsi, %%ReturnAddress
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LYMMN ymm7, xmm5, 1
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SXMMN xmm5, 0, rsi
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SYMMN ymm7, 1, xmm5
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mov rsi, %1
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jmp rsi
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%%ReturnAddress:
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%endmacro
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;
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; Restore RIP from YMM7[128:191]
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; Modified: RSI, XMM5
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;
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%macro RET_YMM 0
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LYMMN ymm7, xmm5, 1
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movq rsi, xmm5
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jmp rsi
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%endmacro
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%macro ENABLE_SSE 0
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;
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; Initialize floating point units
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;
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jmp NextAddress
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align 4
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;
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; Float control word initial value:
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; all exceptions masked, double-precision, round-to-nearest
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;
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FpuControlWord DW 027Fh
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;
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; Multimedia-extensions control word:
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; all exceptions masked, round-to-nearest, flush to zero for masked underflow
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;
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MmxControlWord DQ 01F80h
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SseError:
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;
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; Processor has to support SSE
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;
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jmp SseError
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NextAddress:
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finit
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mov rax, FpuControlWord
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fldcw [rax]
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;
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; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
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; whether the processor supports SSE instruction.
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;
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mov rax, 1
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cpuid
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bt rdx, 25
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jnc SseError
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;
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; SSE 4.1 support
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;
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bt ecx, 19
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jnc SseError
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;
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; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
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;
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mov rax, cr4
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or rax, 00000600h
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mov cr4, rax
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;
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; The processor should support SSE instruction and we can use
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; ldmxcsr instruction
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;
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mov rax, MmxControlWord
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ldmxcsr [rax]
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%endmacro
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%macro ENABLE_AVX 0
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mov eax, 1
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cpuid
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and ecx, 10000000h
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cmp ecx, 10000000h ; check AVX feature flag
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je EnableAvx
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AvxError:
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;
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; Processor has to support AVX
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;
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jmp AvxError
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EnableAvx:
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;
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; Set OSXSAVE bit (bit #18) to enable xgetbv/xsetbv instruction
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;
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mov rax, cr4
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or rax, 00040000h
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mov cr4, rax
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mov rcx, 0 ; index 0
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xgetbv ; result in edx:eax
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or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable SSE state and AVX state
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xsetbv
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%endmacro
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