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MdeModulePkg/PciBus: Shadow option ROM after BARs are programmed

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1376

Today's implementation reuses the 32bit MMIO resource requested by
all PCI devices MMIO BARs when shadowing the option ROM.
Take a simple example, a system has only one PCI device. It requires
8MB 32bit MMIO and contains a 4MB option ROM. Today's implementation
only requests 8MB (max of 4M and 8M) 32bit MMIO from
PciHostBridgeResourceAllocation protocol. Let's assume the MMIO range
[3GB, 3GB+8MB) is allocated. The 3GB base address is firstly
programmed to the option ROM BAR for option ROM shadow. Then the
option ROM decoding is turned off and 3GB base address is programmed
to the 32bit MMIO BAR.

It doesn't cause issues when the device doesn't request too much
MMIO.
But when the device contains a 64bit MMIO BAR which requests 4GB MMIO
and a 4MB option ROM. Let's assume [3GB, 3GB+8MB) 32bit MMIO range is
allocated for the option ROM. When the option ROM is being shadowed,
64bit MMIO BAR is programmed to value 0, which means [0, 4GB) MMIO is
given to the 64bit BAR.
The range overlaps with the option ROM range which may cause the
device malfunction (e.g.: option ROM cannot be read out) when the
device has two separate decoders: one for MMIO BAR, the other for
option ROM.

The patch requests dedicated MEM32 resource for Option ROMs and
moves the Option ROM shadow logic after all MMIO BARs are programmed.
The MMIO BAR setting to 0 when shadowing Option ROM is also skipped
because the MMIO BAR already contains the correct value.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Ruiyu Ni
2018-12-01 22:43:28 +08:00
parent f7f94ffe88
commit 0176af142e
4 changed files with 62 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
View File

@ -446,13 +446,14 @@ GetResourceFromDevice (
switch ((PciDev->PciBar)[Index].BarType) {
case PciBarTypeMem32:
case PciBarTypeOpRom:
Node = CreateResourceNode (
PciDev,
(PciDev->PciBar)[Index].Length,
(PciDev->PciBar)[Index].Alignment,
Index,
PciBarTypeMem32,
(PciDev->PciBar)[Index].BarType,
PciResUsageTypical
);
@ -1307,7 +1308,13 @@ ProgramBar (
1,
&Address
);
//
// Continue to the case PciBarTypeOpRom to set the BaseAddress.
// PciBarTypeOpRom is a virtual BAR only in root bridge, to capture
// the MEM32 resource requirement for Option ROM shadow.
//
case PciBarTypeOpRom:
Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;
break;
@ -1656,6 +1663,8 @@ ProgrameUpstreamBridgeForRom (
{
PCI_IO_DEVICE *Parent;
PCI_RESOURCE_NODE Node;
UINT64 Base;
UINT64 Length;
//
// For root bridge, just return.
//
@ -1667,7 +1676,6 @@ ProgrameUpstreamBridgeForRom (
}
Node.PciDev = Parent;
Node.Length = PciDevice->RomSize;
Node.Alignment = 0;
Node.Bar = PPB_MEM32_RANGE;
Node.ResType = PciBarTypeMem32;
@ -1677,10 +1685,33 @@ ProgrameUpstreamBridgeForRom (
// Program PPB to only open a single <= 16MB apperture
//
if (Enable) {
//
// Save the original PPB_MEM32_RANGE BAR.
// The values will be changed by ProgramPpbApperture().
//
Base = Parent->PciBar[Node.Bar].BaseAddress;
Length = Parent->PciBar[Node.Bar].Length;
//
// Only cover MMIO for Option ROM.
//
Node.Length = PciDevice->RomSize;
ProgramPpbApperture (OptionRomBase, &Node);
//
// Restore the original PPB_MEM32_RANGE BAR.
// So the MEM32 RANGE BAR register can be restored when disable the decoding.
//
Parent->PciBar[Node.Bar].BaseAddress = Base;
Parent->PciBar[Node.Bar].Length = Length;
PCI_ENABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);
} else {
InitializePpb (Parent);
//
// Cover 32bit MMIO for devices below the bridge.
//
Node.Length = Parent->PciBar[Node.Bar].Length;
ProgramPpbApperture (Parent->PciBar[Node.Bar].BaseAddress, &Node);
PCI_DISABLE_COMMAND_REGISTER (Parent, EFI_PCI_COMMAND_MEMORY_SPACE);
}