From 019c7b79a66488aeda83aae852eea89dd1920d4b Mon Sep 17 00:00:00 2001
From: Ruiyu Ni <ruiyu.ni@intel.com>
Date: Thu, 8 Feb 2018 14:43:20 +0800
Subject: [PATCH] UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's
 disabled

Today's McaInitialize() doesn't check State value before initialize
MCi_CTL and MCi_STATUS.
The patch fixes this issue by only initializing the two kinds of
MSRs when State is enabled.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
(cherry picked from commit dc7363f848158564d8404c415061acf8c51ceb45)
---
 .../CpuCommonFeaturesLib/MachineCheck.c       | 32 ++++++++++---------
 1 file changed, 17 insertions(+), 15 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index 58dc45aeda..cc64dbbf0a 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -1,7 +1,7 @@
 /** @file
   Machine Check features.
 
-  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -140,25 +140,27 @@ McaInitialize (
   MSR_IA32_MCG_CAP_REGISTER  McgCap;
   UINT32                     BankIndex;
 
-  McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
-  for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
-    CPU_REGISTER_TABLE_WRITE64 (
-      ProcessorNumber,
-      Msr,
-      MSR_IA32_MC0_CTL + BankIndex * 4,
-      MAX_UINT64
-      );
-  }
-
-  if (PcdGetBool (PcdIsPowerOnReset)) {
-    for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
+  if (State == TRUE) {
+    McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
+    for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {
       CPU_REGISTER_TABLE_WRITE64 (
         ProcessorNumber,
         Msr,
-        MSR_IA32_MC0_STATUS + BankIndex * 4,
-        0
+        MSR_IA32_MC0_CTL + BankIndex * 4,
+        MAX_UINT64
         );
     }
+
+    if (PcdGetBool (PcdIsPowerOnReset)) {
+      for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {
+        CPU_REGISTER_TABLE_WRITE64 (
+          ProcessorNumber,
+          Msr,
+          MSR_IA32_MC0_STATUS + BankIndex * 4,
+          0
+          );
+      }
+    }
   }
 
   return RETURN_SUCCESS;