From 01eb3f39bbcc5b6474d69cff3922be8eb1856636 Mon Sep 17 00:00:00 2001
From: Jeff Fan <jeff.fan@intel.com>
Date: Wed, 15 Mar 2017 09:47:52 +0800
Subject: [PATCH] UefiCpuPkg/CpuDxe: Remove MSR_IA32_MISC_ENABLE check

The architectural MSR MSR_IA32_MISC_ENABLE is not supported by AMD processors.
Because reading CPUID.80000001H:EDK[20] is enough to check if XD feature is
supported or not, we just remove checking MSR_IA32_MISC_ENABLE(0x1A0).

Cc: Anthony PERARD <anthony.perard@citrix.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Tested-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
---
 UefiCpuPkg/CpuDxe/CpuPageTable.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index 65f607a90c..ab664b47d6 100644
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -193,12 +193,9 @@ GetCurrentPagingContext (
     AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
     if ((RegEdx & BIT20) != 0) {
       // XD supported
-      if ((AsmReadMsr64 (0x000001A0) & BIT34) == 0) {
-        // XD enabled
-        if ((AsmReadMsr64 (0xC0000080) & BIT11) != 0) {
-          // XD activated
-          PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
-        }
+      if ((AsmReadMsr64 (0xC0000080) & BIT11) != 0) {
+        // XD activated
+        PagingContext->ContextData.Ia32.Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
       }
     }
     if ((RegEdx & BIT26) != 0) {