Updated Hardware Interrupt protocol to add an EOI member. Added ARM Data/Instruction syncronization barrier support to the ARM lib.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10063 6f19259b-4bc3-4df7-8a09-765794883524

ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c

@@ -116,3 +116,34 @@ ArmConfigureMmu (
   ArmEnableDataCache();
   ArmEnableMmu();  
 }
+
+
+VOID
+EFIAPI
+ArmDataMemoryBarrier (
+  VOID
+  )
+{
+  // Should move to assembly with the 
+}
+  
+VOID
+EFIAPI
+ArmDataSyncronizationBarrier (
+  VOID
+  )
+{
+// MOV R0, #0
+// MCR P15, #0, R0, C7, C10, #4}
+}
+
+
+VOID
+EFIAPI
+ArmInstructionSynchronizationBarrier (
+  VOID
+  )
+{
+}
+
+

ArmPkg/Library/ArmLib/Arm11/Arm11Support.S

@@ -30,6 +30,10 @@
 .globl ASM_PFX(ArmDisableInstructionCache)
 .globl ASM_PFX(ArmEnableBranchPrediction)
 .globl ASM_PFX(ArmDisableBranchPrediction)
+.globl ASM_PFX(ArmDataMemoryBarrier)
+.globl ASM_PFX(ArmDataSyncronizationBarrier) 
+.globl ASM_PFX(ArmInstructionSynchronizationBarrier)
+
 
 .set DC_ON, (0x1<<2)
 .set IC_ON, (0x1<<12)
@@ -132,4 +136,20 @@ ASM_PFX(ArmDisableBranchPrediction):
   mcr     p15, 0, r0, c1, c0, 0
   bx      LR
 
+ASM_PFX(ArmDataMemoryBarrier):
+  mov R0, #0
+  mcr P15, #0, R0, C7, C10, #5 
+  bx      LR
+  
+ASM_PFX(ArmDataSyncronizationBarrier):
+  mov R0, #0
+  mcr P15, #0, R0, C7, C10, #4 
+  bx      LR
+  
+ASM_PFX(ArmInstructionSynchronizationBarrier):
+  mov R0, #0
+  mcr P15, #0, R0, C7, C5, #4 
+  bx      LR
+  
+
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED

ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm

@@ -28,6 +28,9 @@
     EXPORT  ArmDisableInstructionCache
     EXPORT  ArmEnableBranchPrediction
     EXPORT  ArmDisableBranchPrediction
+    EXPORT  ArmDataMemoryBarrier
+    EXPORT  ArmDataSyncronizationBarrier
+    EXPORT  ArmInstructionSynchronizationBarrier
 
 
 DC_ON       EQU     ( 0x1:SHL:2 )
@@ -136,4 +139,19 @@ ArmDisableBranchPrediction
   mcr     p15, 0, r0, c1, c0, 0
   bx      LR
 
+ASM_PFX(ArmDataMemoryBarrier):
+  mov R0, #0
+  mcr P15, #0, R0, C7, C10, #5 
+  bx      LR
+  
+ASM_PFX(ArmDataSyncronizationBarrier):
+  mov R0, #0
+  mcr P15, #0, R0, C7, C10, #4 
+  bx      LR
+  
+ASM_PFX(ArmInstructionSynchronizationBarrier):
+  MOV R0, #0
+  MCR P15, #0, R0, C7, C5, #4 
+  bx      LR
+
     END

ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c

@@ -116,3 +116,30 @@ ArmConfigureMmu (
   ArmEnableDataCache();
   ArmEnableMmu();
 }
+
+
+VOID
+EFIAPI
+ArmDataMemoryBarrier (
+  VOID
+  )
+{
+}
+  
+VOID
+EFIAPI
+ArmDataSyncronizationBarrier (
+  VOID
+  )
+{
+}
+
+VOID
+EFIAPI
+ArmInstructionSynchronizationBarrier (
+  VOID
+  )
+{
+}
+
+

ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

@@ -34,6 +34,10 @@
 .globl ASM_PFX(ArmEnableBranchPrediction)
 .globl ASM_PFX(ArmDisableBranchPrediction)
 .globl ASM_PFX(ArmV7AllDataCachesOperation)
+.globl ASM_PFX(ArmDataMemoryBarrier)
+.globl ASM_PFX(ArmDataSyncronizationBarrier) 
+.globl ASM_PFX(ArmInstructionSynchronizationBarrier)
+
 
 .set DC_ON, (0x1<<2)
 .set IC_ON, (0x1<<12)
@@ -222,5 +226,17 @@ L_Finished:
   ldmfd SP!, {r4-r12, lr}
   bx    LR
 
+ASM_PFX(ArmDataMemoryBarrier):
+  dmb
+  bx      LR
+  
+ASM_PFX(ArmDataSyncronizationBarrier):
+  dsb
+  bx      LR
+  
+ASM_PFX(ArmInstructionSynchronizationBarrier):
+  isb
+  bx      LR
+ 
 
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED

ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

@@ -30,6 +30,10 @@
     EXPORT  ArmEnableBranchPrediction
     EXPORT  ArmDisableBranchPrediction
     EXPORT  ArmV7AllDataCachesOperation
+    EXPORT  ArmDataMemoryBarrier
+    EXPORT  ArmDataSyncronizationBarrier
+    EXPORT  ArmInstructionSynchronizationBarrier
+
 
 DC_ON       EQU     ( 0x1:SHL:2 )
 IC_ON       EQU     ( 0x1:SHL:12 )
@@ -217,4 +221,17 @@ Finished
   LDMFD SP!, {r4-r12, lr}
   BX    LR
 
+
+ArmDataMemoryBarrier
+  DMB
+  BX      LR
+  
+ArmDataSyncronizationBarrier
+  DSB
+  BX      LR
+  
+ArmInstructionSynchronizationBarrier
+  ISB
+  BX      LR
+
     END