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Cleanup SerailIO drivers to have a device path and use PCD settings for various stuff. Also clean up a few coding convention items.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10009 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2010-02-15 20:40:51 +00:00
parent 95572bd1b8
commit 026e30c4bb
13 changed files with 481 additions and 257 deletions
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77
Omap35xxPkg/Flash/Flash.c
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@@ -22,21 +22,36 @@ NAND_FLASH_INFO *gNandFlashInfo = NULL;
UINT8 *gEccCode;
UINTN gNum512BytesChunks = 0;
//
// Device path for SemiHosting. It contains our autogened Caller ID GUID.
//
typedef struct {
VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End;
} FLASH_DEVICE_PATH;
FLASH_DEVICE_PATH gDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
EFI_CALLER_ID_GUID
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
};
//
// Device path for SemiHosting. It contains our autogened Caller ID GUID.
//
typedef struct {
VENDOR_DEVICE_PATH Guid;
EFI_DEVICE_PATH_PROTOCOL End;
} FLASH_DEVICE_PATH;
FLASH_DEVICE_PATH gDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
EFI_CALLER_ID_GUID
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
};
//Actual page address = Column address + Page address + Block address.
@@ -110,26 +125,26 @@ GpmcInit (
)
{
//Enable Smart-idle mode.
MmioWrite32(GPMC_SYSCONFIG, SMARTIDLEMODE);
MmioWrite32 (GPMC_SYSCONFIG, SMARTIDLEMODE);
//Set IRQSTATUS and IRQENABLE to the reset value
MmioWrite32(GPMC_IRQSTATUS, 0x0);
MmioWrite32(GPMC_IRQENABLE, 0x0);
MmioWrite32 (GPMC_IRQSTATUS, 0x0);
MmioWrite32 (GPMC_IRQENABLE, 0x0);
//Disable GPMC timeout control.
MmioWrite32(GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
MmioWrite32 (GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
//Set WRITEPROTECT bit to enable write access.
MmioWrite32(GPMC_CONFIG, WRITEPROTECT_HIGH);
MmioWrite32 (GPMC_CONFIG, WRITEPROTECT_HIGH);
//NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
MmioWrite32(GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
MmioWrite32(GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
MmioWrite32(GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
MmioWrite32(GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
MmioWrite32(GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
MmioWrite32(GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
MmioWrite32(GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
MmioWrite32 (GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
MmioWrite32 (GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
MmioWrite32 (GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
MmioWrite32 (GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
MmioWrite32 (GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
MmioWrite32 (GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
MmioWrite32 (GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
}
EFI_STATUS
@@ -215,7 +230,7 @@ NandConfigureEcc (
)
{
//Define ECC size 0 and size 1 to 512 bytes
MmioWrite32(GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
MmioWrite32 (GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
}
VOID
@@ -224,10 +239,10 @@ NandEnableEcc (
)
{
//Clear all the ECC result registers and select ECC result register 1
MmioWrite32(GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
MmioWrite32 (GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
//Enable ECC engine on CS0
MmioWrite32(GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
MmioWrite32 (GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
}
VOID
@@ -236,7 +251,7 @@ NandDisableEcc (
)
{
//Turn off ECC engine.
MmioWrite32(GPMC_ECC_CONFIG, ECCDISABLE);
MmioWrite32 (GPMC_ECC_CONFIG, ECCDISABLE);
}
VOID