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Cleanup SerailIO drivers to have a device path and use PCD settings for various stuff. Also clean up a few coding convention items.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10009 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
2010-02-15 20:40:51 +00:00
parent 95572bd1b8
commit 026e30c4bb
13 changed files with 481 additions and 257 deletions
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6
BeagleBoardPkg/Sec/Clock.c
View File

@ -25,9 +25,9 @@ ClockInit (
//DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses. //DPLL1 - DPLL4 are configured part of Configuration header which OMAP3 ROM parses.
// Enable PLL5 and set to 120 MHz as a reference clock. // Enable PLL5 and set to 120 MHz as a reference clock.
MmioWrite32(CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13)); MmioWrite32 (CM_CLKSEL4_PLL, CM_CLKSEL_PLL_MULT(120) | CM_CLKSEL_PLL_DIV(13));
MmioWrite32(CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1)); MmioWrite32 (CM_CLKSEL5_PLL, CM_CLKSEL_DIV_120M(1));
MmioWrite32(CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE); MmioWrite32 (CM_CLKEN2_PLL, CM_CLKEN_FREQSEL_075_100 | CM_CLKEN_ENABLE);
// Turn on functional & interface clocks to the USBHOST power domain // Turn on functional & interface clocks to the USBHOST power domain
MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE MmioOr32(CM_FCLKEN_USBHOST, CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE

61
BeagleBoardPkg/Sec/Sec.c
View File

@ -63,19 +63,19 @@ TimerInit (
| CM_CLKSEL_PER_CLKSEL_GPT4_SYS); | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
// Set count & reload registers // Set count & reload registers
MmioWrite32(TimerBaseAddress + GPTIMER_TCRR, 0x00000000); MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
MmioWrite32(TimerBaseAddress + GPTIMER_TLDR, 0x00000000); MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
// Disable interrupts // Disable interrupts
MmioWrite32(TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE); MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
// Start Timer // Start Timer
MmioWrite32(TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
//Disable OMAP Watchdog timer (WDT2) //Disable OMAP Watchdog timer (WDT2)
MmioWrite32(WDTIMER2_BASE + WSPR, 0xAAAA); MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n")); DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
MmioWrite32(WDTIMER2_BASE + WSPR, 0x5555); MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
} }
VOID VOID
@ -87,26 +87,26 @@ UartInit (
UINT32 UartBaseAddress = UartBase(Uart); UINT32 UartBaseAddress = UartBase(Uart);
// Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers. // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers.
MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE); MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE);
// Put device in configuration mode. // Put device in configuration mode.
MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE); MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE);
// Programmable divisor N = 48Mhz/16/115200 = 26 // Programmable divisor N = 48Mhz/16/115200 = 26
MmioWrite32(UartBaseAddress + UART_DLL_REG, 26); // low divisor MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000/FixedPcdGet64 (PcdUartDefaultBaudRate)); // low divisor
MmioWrite32(UartBaseAddress + UART_DLH_REG, 0); // high divisor MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor
// Enter into UART operational mode. // Enter into UART operational mode.
MmioWrite32(UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8); MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8);
// Force DTR and RTS output to active // Force DTR and RTS output to active
MmioWrite32(UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE); MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE);
// Clear & enable fifos // Clear & enable fifos
MmioWrite32(UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE);
// Restore MODE_SELECT // Restore MODE_SELECT
MmioWrite32(UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X); MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X);
} }
VOID VOID
@ -185,30 +185,30 @@ CEntryPoint (
VOID *HobBase; VOID *HobBase;
//Set up Pin muxing. //Set up Pin muxing.
PadConfiguration(); PadConfiguration ();
// Set up system clocking // Set up system clocking
ClockInit(); ClockInit ();
// Build a basic HOB list // Build a basic HOB list
HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize)); HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize));
CreateHobList(MemoryBase, MemorySize, HobBase, StackBase); CreateHobList (MemoryBase, MemorySize, HobBase, StackBase);
// Enable program flow prediction, if supported. // Enable program flow prediction, if supported.
ArmEnableBranchPrediction(); ArmEnableBranchPrediction ();
// Initialize CPU cache // Initialize CPU cache
InitCache((UINT32)MemoryBase, (UINT32)MemorySize); InitCache ((UINT32)MemoryBase, (UINT32)MemorySize);
// Add memory allocation hob for relocated FD // Add memory allocation hob for relocated FD
BuildMemoryAllocationHob(FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData); BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData);
// Add the FVs to the hob list // Add the FVs to the hob list
BuildFvHob(PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize)); BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize));
// Start talking // Start talking
UartInit(); UartInit ();
DEBUG((EFI_D_ERROR, "UART Enabled\n")); DEBUG ((EFI_D_ERROR, "UART Enabled\n"));
DEBUG_CODE_BEGIN (); DEBUG_CODE_BEGIN ();
// //
@ -251,33 +251,32 @@ CEntryPoint (
} }
} }
DEBUG_CODE_END ();
DEBUG_CODE_END ();
// Start up a free running time so that the timer lib will work // Start up a free running time so that the timer lib will work
TimerInit(); TimerInit ();
// SEC phase needs to run library constructors by hand. // SEC phase needs to run library constructors by hand.
ExtractGuidedSectionLibConstructor(); ExtractGuidedSectionLibConstructor ();
LzmaDecompressLibConstructor(); LzmaDecompressLibConstructor ();
// Build HOBs to pass up our version of stuff the DXE Core needs to save space // Build HOBs to pass up our version of stuff the DXE Core needs to save space
#if 0
BuildPeCoffLoaderHob (); BuildPeCoffLoaderHob ();
BuildExtractSectionHob ( BuildExtractSectionHob (
&gLzmaCustomDecompressGuid, &gLzmaCustomDecompressGuid,
LzmaGuidedSectionGetInfo, LzmaGuidedSectionGetInfo,
LzmaGuidedSectionExtraction LzmaGuidedSectionExtraction
); );
#endif
DecompressFirstFv (); DecompressFirstFv ();
// Load the DXE Core and transfer control to it // Load the DXE Core and transfer control to it
LoadDxeCoreFromFv(NULL, 0); LoadDxeCoreFromFv (NULL, 0);
// DXE Core should always load and never return // DXE Core should always load and never return
ASSERT(FALSE); ASSERT (FALSE);
} }

1
BeagleBoardPkg/Sec/Sec.inf
View File

@ -53,6 +53,7 @@
gEmbeddedTokenSpaceGuid.PcdCacheEnable gEmbeddedTokenSpaceGuid.PcdCacheEnable
[FixedPcd] [FixedPcd]
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase

10
EmbeddedPkg/SerialDxe/SerialDxe.inf
View File

@ -1,6 +1,6 @@
#/** @file #/** @file
# #
# Component discription file for Bds module # Convert SerialLib into SerialIo protocol
# #
# Copyright (c) 2008, Intel Corporation. <BR> # Copyright (c) 2008, Intel Corporation. <BR>
# All rights reserved. This program and the accompanying materials # All rights reserved. This program and the accompanying materials
@ -47,7 +47,13 @@
[Protocols] [Protocols]
gEfiSerialIoProtocolGuid gEfiSerialIoProtocolGuid
gEfiDevicePathProtocolGuid gEfiDevicePathProtocolGuid
[FixedPcd]
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
[Depex] [Depex]
TRUE TRUE

41
EmbeddedPkg/SerialDxe/SerialIo.c
View File

@ -23,6 +23,7 @@
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/SerialPortLib.h> #include <Library/SerialPortLib.h>
#include <Library/PcdLib.h>
#include <Protocol/SerialIo.h> #include <Protocol/SerialIo.h>
@ -189,7 +190,7 @@ SerialRead (
{ {
UINTN Count; UINTN Count;
Count = SerialPortWrite (Buffer, *BufferSize); Count = SerialPortRead (Buffer, *BufferSize);
*BufferSize = Count; *BufferSize = Count;
return (Count == 0) ? EFI_DEVICE_ERROR : EFI_SUCCESS; return (Count == 0) ? EFI_DEVICE_ERROR : EFI_SUCCESS;
} }
@ -201,13 +202,13 @@ EFI_HANDLE gHandle = NULL;
// Template used to initailize the GDB Serial IO protocols // Template used to initailize the GDB Serial IO protocols
// //
EFI_SERIAL_IO_MODE gSerialIoMode = { EFI_SERIAL_IO_MODE gSerialIoMode = {
0, // ControlMask 0, // ControlMask
0, // Timeout 0, // Timeout
0, // BaudRate FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
1, // RceiveFifoDepth 1, // RceiveFifoDepth
0, // DataBits FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
0, // Parity FixedPcdGet8 (PcdUartDefaultParity), // Parity
0 // StopBits FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits
}; };
@ -222,6 +223,28 @@ EFI_SERIAL_IO_PROTOCOL gSerialIoTemplate = {
&gSerialIoMode &gSerialIoMode
}; };
typedef struct {
VENDOR_DEVICE_PATH Guid;
UART_DEVICE_PATH Uart;
EFI_DEVICE_PATH_PROTOCOL End;
} SIMPLE_TEXT_OUT_DEVICE_PATH;
SIMPLE_TEXT_OUT_DEVICE_PATH mDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0},
EFI_CALLER_ID_GUID // Use the drivers GUID
},
{
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (UART_DEVICE_PATH), 0},
0, // Reserved
FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
FixedPcdGet8 (PcdUartDefaultParity), // Parity (N)
FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
};
/** /**
Initialize the state information for the Serial Io Protocol Initialize the state information for the Serial Io Protocol
@ -248,7 +271,7 @@ SerialDxeInitialize (
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&gHandle, &gHandle,
&gEfiSerialIoProtocolGuid, &gSerialIoTemplate, &gEfiSerialIoProtocolGuid, &gSerialIoTemplate,
&gEfiDevicePathProtocolGuid, NULL, // BugBug: Need a device path &gEfiDevicePathProtocolGuid, &mDevicePath,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

34
EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOut.c
View File

@ -64,10 +64,12 @@
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/SerialPortLib.h> #include <Library/SerialPortLib.h>
#include <Library/PcdLib.h>
#include <Protocol/SerialIo.h> #include <Protocol/SerialIo.h>
#include <Protocol/SimpleTextIn.h> #include <Protocol/SimpleTextIn.h>
#include <Protocol/SimpleTextOut.h> #include <Protocol/SimpleTextOut.h>
#include <Protocol/DevicePath.h>
#define MODE0_COLUMN_COUNT 80 #define MODE0_COLUMN_COUNT 80
@ -198,7 +200,30 @@ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL mSimpleTextOut = {
&mSimpleTextOutMode &mSimpleTextOutMode
}; };
EFI_HANDLE mInstallHandle = NULL; EFI_HANDLE mInstallHandle = NULL;
typedef struct {
VENDOR_DEVICE_PATH Guid;
UART_DEVICE_PATH Uart;
EFI_DEVICE_PATH_PROTOCOL End;
} SIMPLE_TEXT_OUT_DEVICE_PATH;
SIMPLE_TEXT_OUT_DEVICE_PATH mDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0},
EFI_CALLER_ID_GUID
},
{
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (UART_DEVICE_PATH), 0},
0, // Reserved
FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
FixedPcdGet8 (PcdUartDefaultParity), // Parity (N)
FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
};
@ -271,6 +296,10 @@ ReadKeyStroke (
{ {
CHAR8 Char; CHAR8 Char;
if (!SerialPortPoll ()) {
return EFI_NOT_READY;
}
SerialPortRead ((UINT8 *)&Char, 1); SerialPortRead ((UINT8 *)&Char, 1);
// //
@ -660,7 +689,8 @@ SimpleTextInOutEntryPoint (
&mInstallHandle, &mInstallHandle,
&gEfiSimpleTextInProtocolGuid, &mSimpleTextIn, &gEfiSimpleTextInProtocolGuid, &mSimpleTextIn,
&gEfiSimpleTextOutProtocolGuid, &mSimpleTextOut, &gEfiSimpleTextOutProtocolGuid, &mSimpleTextOut,
NULL &gEfiDevicePathProtocolGuid, &mDevicePath,
NULL
); );
if (!EFI_ERROR (Status)) { if (!EFI_ERROR (Status)) {
gST->ConOut = &mSimpleTextOut; gST->ConOut = &mSimpleTextOut;

7
EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
View File

@ -51,5 +51,12 @@
gEfiSerialIoProtocolGuid gEfiSerialIoProtocolGuid
gEfiDevicePathProtocolGuid gEfiDevicePathProtocolGuid
[FixedPcd]
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
[depex] [depex]
TRUE TRUE

77
Omap35xxPkg/Flash/Flash.c
View File

@ -22,21 +22,36 @@ NAND_FLASH_INFO *gNandFlashInfo = NULL;
UINT8 *gEccCode; UINT8 *gEccCode;
UINTN gNum512BytesChunks = 0; UINTN gNum512BytesChunks = 0;
// //
// Device path for SemiHosting. It contains our autogened Caller ID GUID.
// // Device path for SemiHosting. It contains our autogened Caller ID GUID.
typedef struct {
VENDOR_DEVICE_PATH Guid; //
EFI_DEVICE_PATH_PROTOCOL End;
} FLASH_DEVICE_PATH; typedef struct {
FLASH_DEVICE_PATH gDevicePath = { VENDOR_DEVICE_PATH Guid;
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 }, EFI_DEVICE_PATH_PROTOCOL End;
EFI_CALLER_ID_GUID
}, } FLASH_DEVICE_PATH;
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
};
FLASH_DEVICE_PATH gDevicePath = {
{
{ HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },
EFI_CALLER_ID_GUID
},
{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}
};
//Actual page address = Column address + Page address + Block address. //Actual page address = Column address + Page address + Block address.
@ -110,26 +125,26 @@ GpmcInit (
) )
{ {
//Enable Smart-idle mode. //Enable Smart-idle mode.
MmioWrite32(GPMC_SYSCONFIG, SMARTIDLEMODE); MmioWrite32 (GPMC_SYSCONFIG, SMARTIDLEMODE);
//Set IRQSTATUS and IRQENABLE to the reset value //Set IRQSTATUS and IRQENABLE to the reset value
MmioWrite32(GPMC_IRQSTATUS, 0x0); MmioWrite32 (GPMC_IRQSTATUS, 0x0);
MmioWrite32(GPMC_IRQENABLE, 0x0); MmioWrite32 (GPMC_IRQENABLE, 0x0);
//Disable GPMC timeout control. //Disable GPMC timeout control.
MmioWrite32(GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE); MmioWrite32 (GPMC_TIMEOUT_CONTROL, TIMEOUTDISABLE);
//Set WRITEPROTECT bit to enable write access. //Set WRITEPROTECT bit to enable write access.
MmioWrite32(GPMC_CONFIG, WRITEPROTECT_HIGH); MmioWrite32 (GPMC_CONFIG, WRITEPROTECT_HIGH);
//NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump. //NOTE: Following GPMC_CONFIGi_0 register settings are taken from u-boot memory dump.
MmioWrite32(GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16); MmioWrite32 (GPMC_CONFIG1_0, DEVICETYPE_NAND | DEVICESIZE_X16);
MmioWrite32(GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME); MmioWrite32 (GPMC_CONFIG2_0, CSRDOFFTIME | CSWROFFTIME);
MmioWrite32(GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME); MmioWrite32 (GPMC_CONFIG3_0, ADVRDOFFTIME | ADVWROFFTIME);
MmioWrite32(GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME); MmioWrite32 (GPMC_CONFIG4_0, OEONTIME | OEOFFTIME | WEONTIME | WEOFFTIME);
MmioWrite32(GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME); MmioWrite32 (GPMC_CONFIG5_0, RDCYCLETIME | WRCYCLETIME | RDACCESSTIME | PAGEBURSTACCESSTIME);
MmioWrite32(GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN); MmioWrite32 (GPMC_CONFIG6_0, WRACCESSTIME | WRDATAONADMUXBUS | CYCLE2CYCLEDELAY | CYCLE2CYCLESAMECSEN);
MmioWrite32(GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS); MmioWrite32 (GPMC_CONFIG7_0, MASKADDRESS_128MB | CSVALID | BASEADDRESS);
} }
EFI_STATUS EFI_STATUS
@ -215,7 +230,7 @@ NandConfigureEcc (
) )
{ {
//Define ECC size 0 and size 1 to 512 bytes //Define ECC size 0 and size 1 to 512 bytes
MmioWrite32(GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES)); MmioWrite32 (GPMC_ECC_SIZE_CONFIG, (ECCSIZE0_512BYTES | ECCSIZE1_512BYTES));
} }
VOID VOID
@ -224,10 +239,10 @@ NandEnableEcc (
) )
{ {
//Clear all the ECC result registers and select ECC result register 1 //Clear all the ECC result registers and select ECC result register 1
MmioWrite32(GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1)); MmioWrite32 (GPMC_ECC_CONTROL, (ECCCLEAR | ECCPOINTER_REG1));
//Enable ECC engine on CS0 //Enable ECC engine on CS0
MmioWrite32(GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B)); MmioWrite32 (GPMC_ECC_CONFIG, (ECCENABLE | ECCCS_0 | ECC16B));
} }
VOID VOID
@ -236,7 +251,7 @@ NandDisableEcc (
) )
{ {
//Turn off ECC engine. //Turn off ECC engine.
MmioWrite32(GPMC_ECC_CONFIG, ECCDISABLE); MmioWrite32 (GPMC_ECC_CONFIG, ECCDISABLE);
} }
VOID VOID

4
Omap35xxPkg/Gpio/Gpio.c
View File

@ -79,12 +79,12 @@ Set (
break; break;
case GPIO_MODE_OUTPUT_0: case GPIO_MODE_OUTPUT_0:
MmioWrite32(ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin)); MmioWrite32 (ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin)); MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break; break;
case GPIO_MODE_OUTPUT_1: case GPIO_MODE_OUTPUT_1:
MmioWrite32(SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin)); MmioWrite32 (SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin));
MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin)); MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
break; break;

24
Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
View File

@ -54,10 +54,10 @@ ExitBootServicesEvent (
) )
{ {
// Disable all interrupts // Disable all interrupts
MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF); MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF); MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF); MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
} }
/** /**
@ -125,7 +125,7 @@ EnableInterruptSource (
Bank = Source / 32; Bank = Source / 32;
Bit = 1UL << (Source % 32); Bit = 1UL << (Source % 32);
MmioWrite32(INTCPS_MIR_CLEAR(Bank), Bit); MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -159,7 +159,7 @@ DisableInterruptSource(
Bank = Source / 32; Bank = Source / 32;
Bit = 1UL << (Source % 32); Bit = 1UL << (Source % 32);
MmioWrite32(INTCPS_MIR_SET(Bank), Bit); MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -235,7 +235,7 @@ IrqInterruptHandler (
Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK; Vector = MmioRead32(INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;
// Needed to prevent infinite nesting when Time Driver lowers TPL // Needed to prevent infinite nesting when Time Driver lowers TPL
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
InterruptHandler = gRegisteredInterruptHandlers[Vector]; InterruptHandler = gRegisteredInterruptHandlers[Vector];
if (InterruptHandler != NULL) { if (InterruptHandler != NULL) {
@ -244,7 +244,7 @@ IrqInterruptHandler (
} }
// Needed to clear after running the handler // Needed to clear after running the handler
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
} }
// //
@ -316,10 +316,10 @@ InterruptDxeInitialize (
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid); ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
// Make sure all interrupts are disabled by default. // Make sure all interrupts are disabled by default.
MmioWrite32(INTCPS_MIR(0), 0xFFFFFFFF); MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);
MmioWrite32(INTCPS_MIR(1), 0xFFFFFFFF); MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
MmioWrite32(INTCPS_MIR(2), 0xFFFFFFFF); MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
MmioWrite32(INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle, Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol, &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,

26
Omap35xxPkg/MMCHSDxe/MMCHS.c
View File

@ -113,22 +113,22 @@ SendCmd (
while ((MmioRead32(MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED); while ((MmioRead32(MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
//Provide the block size. //Provide the block size.
MmioWrite32(MMCHS_BLK, BLEN_512BYTES); MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);
//Setting Data timeout counter value to max value. //Setting Data timeout counter value to max value.
MmioAndThenOr32(MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL); MmioAndThenOr32(MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
//Clear Status register. //Clear Status register.
MmioWrite32(MMCHS_STAT, 0xFFFFFFFF); MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF);
//Set command argument register //Set command argument register
MmioWrite32(MMCHS_ARG, CmdArgument); MmioWrite32 (MMCHS_ARG, CmdArgument);
//Enable interrupt enable events to occur //Enable interrupt enable events to occur
MmioWrite32(MMCHS_IE, CmdInterruptEnableVal); MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal);
//Send a command //Send a command
MmioWrite32(MMCHS_CMD, Cmd); MmioWrite32 (MMCHS_CMD, Cmd);
//Check for the command status. //Check for the command status.
while (RetryCount < MAX_RETRY_COUNT) { while (RetryCount < MAX_RETRY_COUNT) {
@ -149,7 +149,7 @@ SendCmd (
//Check if command is completed. //Check if command is completed.
if ((MmcStatus & CC) == CC) { if ((MmcStatus & CC) == CC) {
MmioWrite32(MMCHS_STAT, CC); MmioWrite32 (MMCHS_STAT, CC);
break; break;
} }
@ -354,12 +354,12 @@ InitializeMMCHS (
MmioOr32(CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1)); MmioOr32(CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));
//Software reset of the MMCHS host controller. //Software reset of the MMCHS host controller.
MmioWrite32(MMCHS_SYSCONFIG, SOFTRESET); MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET);
gBS->Stall(1000); gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE); while ((MmioRead32(MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
//Soft reset for all. //Soft reset for all.
MmioWrite32(MMCHS_SYSCTL, SRA); MmioWrite32 (MMCHS_SYSCTL, SRA);
gBS->Stall(1000); gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSCTL) & SRA) != 0x0); while ((MmioRead32(MMCHS_SYSCTL) & SRA) != 0x0);
@ -373,7 +373,7 @@ InitializeMMCHS (
//MMCHS Controller default initialization //MMCHS Controller default initialization
MmioOr32(MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF)); MmioOr32(MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));
MmioWrite32(MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF)); MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
//Enable internal clock //Enable internal clock
MmioOr32(MMCHS_SYSCTL, ICE); MmioOr32(MMCHS_SYSCTL, ICE);
@ -403,12 +403,12 @@ PerformCardIdenfication (
BOOLEAN SDCmd8Supported = FALSE; BOOLEAN SDCmd8Supported = FALSE;
//Enable interrupts. //Enable interrupts.
MmioWrite32(MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN | MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN |
CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN)); CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN));
//Controller INIT procedure start. //Controller INIT procedure start.
MmioOr32(MMCHS_CON, INIT); MmioOr32(MMCHS_CON, INIT);
MmioWrite32(MMCHS_CMD, 0x00000000); MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32(MMCHS_STAT) & CC)); while (!(MmioRead32(MMCHS_STAT) & CC));
//Wait for 1 ms //Wait for 1 ms
@ -418,7 +418,7 @@ PerformCardIdenfication (
MmioOr32(MMCHS_STAT, CC); MmioOr32(MMCHS_STAT, CC);
//Retry INIT procedure. //Retry INIT procedure.
MmioWrite32(MMCHS_CMD, 0x00000000); MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32(MMCHS_STAT) & CC)); while (!(MmioRead32(MMCHS_STAT) & CC));
//End initialization sequence //End initialization sequence
@ -713,7 +713,7 @@ WriteBlockData(
//Write block worth of data. //Write block worth of data.
for (Count = 0; Count < DataSize; Count++) { for (Count = 0; Count < DataSize; Count++) {
MmioWrite32(MMCHS_DATA, *DataBuffer++); MmioWrite32 (MMCHS_DATA, *DataBuffer++);
} }
break; break;

6
Omap35xxPkg/PciEmulation/PciEmulation.c
View File

@ -63,12 +63,12 @@ ConfigureUSBHost (
UINT8 Data = 0; UINT8 Data = 0;
// Take USB host out of force-standby mode // Take USB host out of force-standby mode
MmioWrite32(UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON | UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN); | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
MmioWrite32(UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
@ -80,7 +80,7 @@ ConfigureUSBHost (
// USB reset (GPIO 147 - Port 5 pin 19) output high // USB reset (GPIO 147 - Port 5 pin 19) output high
MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19); MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
MmioWrite32(GPIO5_BASE + GPIO_SETDATAOUT, BIT19); MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
// Get the Power IC protocol. // Get the Power IC protocol.
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950); Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);

441
Omap35xxPkg/TimerDxe/Timer.c
View File

@ -54,15 +54,24 @@ volatile UINT32 TIER;
volatile UINTN gVector; volatile UINTN gVector;
/** /**
C Interrupt Handler calledin the interrupt context when Source interrupt is active.
C Interrupt Handler calledin the interrupt context when Source interrupt is active.
@param Source Source of the interrupt. Hardware routing off a specific platform defines
what source means.
@param SystemContext Pointer to system register context. Mostly used by debuggers and will
update the system context after the return from the interrupt if @param Source Source of the interrupt. Hardware routing off a specific platform defines
modified. Don't change these values unless you know what you are doing
what source means.
@param SystemContext Pointer to system register context. Mostly used by debuggers and will
update the system context after the return from the interrupt if
modified. Don't change these values unless you know what you are doing
**/ **/
VOID VOID
EFIAPI EFIAPI
@ -71,14 +80,22 @@ TimerInterruptHandler (
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
EFI_TPL OriginalTPL; EFI_TPL OriginalTPL;
//
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
// that raise to TPL_HIGH and then restore back to current level. Thus we need //
// to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
// // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
// that raise to TPL_HIGH and then restore back to current level. Thus we need
// to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
//
OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
if (mTimerPeriodicCallback) { if (mTimerPeriodicCallback) {
mTimerPeriodicCallback(SystemContext); mTimerPeriodicCallback(SystemContext);
@ -89,7 +106,7 @@ TimerInterruptHandler (
} }
// Clear all timer interrupts // Clear all timer interrupts
MmioWrite32(TISR, TISR_CLEAR_ALL); MmioWrite32 (TISR, TISR_CLEAR_ALL);
// Poll interrupt status bits to ensure clearing // Poll interrupt status bits to ensure clearing
while ((MmioRead32(TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING); while ((MmioRead32(TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
@ -97,35 +114,64 @@ TimerInterruptHandler (
gBS->RestoreTPL (OriginalTPL); gBS->RestoreTPL (OriginalTPL);
} }
/** /**
This function registers the handler NotifyFunction so it is called every time
the timer interrupt fires. It also passes the amount of time since the last This function registers the handler NotifyFunction so it is called every time
handler call to the NotifyFunction. If NotifyFunction is NULL, then the
handler is unregistered. If the handler is registered, then EFI_SUCCESS is the timer interrupt fires. It also passes the amount of time since the last
returned. If the CPU does not support registering a timer interrupt handler,
then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler handler call to the NotifyFunction. If NotifyFunction is NULL, then the
when a handler is already registered, then EFI_ALREADY_STARTED is returned.
If an attempt is made to unregister a handler when a handler is not registered, handler is unregistered. If the handler is registered, then EFI_SUCCESS is
then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR returned. If the CPU does not support registering a timer interrupt handler,
is returned.
then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param NotifyFunction The function to call when a timer interrupt fires. This when a handler is already registered, then EFI_ALREADY_STARTED is returned.
function executes at TPL_HIGH_LEVEL. The DXE Core will
register a handler for the timer interrupt, so it can know If an attempt is made to unregister a handler when a handler is not registered,
how much time has passed. This information is used to
signal timer based events. NULL will unregister the handler. then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
@retval EFI_SUCCESS The timer handler was registered. register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
@retval EFI_UNSUPPORTED The platform does not support timer interrupts.
@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already is returned.
registered.
@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
previously registered.
@retval EFI_DEVICE_ERROR The timer handler could not be registered. @param This The EFI_TIMER_ARCH_PROTOCOL instance.
**/ @param NotifyFunction The function to call when a timer interrupt fires. This
function executes at TPL_HIGH_LEVEL. The DXE Core will
register a handler for the timer interrupt, so it can know
how much time has passed. This information is used to
signal timer based events. NULL will unregister the handler.
@retval EFI_SUCCESS The timer handler was registered.
@retval EFI_UNSUPPORTED The platform does not support timer interrupts.
@retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
registered.
@retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
previously registered.
@retval EFI_DEVICE_ERROR The timer handler could not be registered.
**/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
TimerDriverRegisterHandler ( TimerDriverRegisterHandler (
@ -146,31 +192,56 @@ TimerDriverRegisterHandler (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
This function adjusts the period of timer interrupts to the value specified
by TimerPeriod. If the timer period is updated, then the selected timer This function adjusts the period of timer interrupts to the value specified
period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. by TimerPeriod. If the timer period is updated, then the selected timer
If an error occurs while attempting to update the timer period, then the
timer hardware will be put back in its state prior to this call, and period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
is disabled. This is not the same as disabling the CPU's interrupts. the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
Instead, it must either turn off the timer hardware, or it must adjust the
interrupt controller so that a CPU interrupt is not generated when the timer If an error occurs while attempting to update the timer period, then the
interrupt fires.
timer hardware will be put back in its state prior to this call, and
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
the timer hardware is not programmable, then EFI_UNSUPPORTED is
returned. If the timer is programmable, then the timer period is disabled. This is not the same as disabling the CPU's interrupts.
will be rounded up to the nearest timer period that is supported
by the timer hardware. If TimerPeriod is set to 0, then the Instead, it must either turn off the timer hardware, or it must adjust the
timer interrupts will be disabled.
interrupt controller so that a CPU interrupt is not generated when the timer
@retval EFI_SUCCESS The timer period was changed.
@retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt. interrupt fires.
@retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
the timer hardware is not programmable, then EFI_UNSUPPORTED is
returned. If the timer is programmable, then the timer period
will be rounded up to the nearest timer period that is supported
by the timer hardware. If TimerPeriod is set to 0, then the
timer interrupts will be disabled.
@retval EFI_SUCCESS The timer period was changed.
@retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
@retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
@ -185,7 +256,7 @@ TimerDriverSetTimerPeriod (
if (TimerPeriod == 0) { if (TimerPeriod == 0) {
// Turn off GPTIMER3 // Turn off GPTIMER3
MmioWrite32(TCLR, TCLR_ST_OFF); MmioWrite32 (TCLR, TCLR_ST_OFF);
Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector); Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector);
} else { } else {
@ -194,14 +265,14 @@ TimerDriverSetTimerPeriod (
// Set GPTIMER3 Load register // Set GPTIMER3 Load register
LoadValue = (INT32) -TimerCount; LoadValue = (INT32) -TimerCount;
MmioWrite32(TLDR, LoadValue); MmioWrite32 (TLDR, LoadValue);
MmioWrite32(TCRR, LoadValue); MmioWrite32 (TCRR, LoadValue);
// Enable Overflow interrupt // Enable Overflow interrupt
MmioWrite32(TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE); MmioWrite32 (TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
// Turn on GPTIMER3, it will reload at overflow // Turn on GPTIMER3, it will reload at overflow
MmioWrite32(TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); MmioWrite32 (TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector); Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector);
} }
@ -214,19 +285,32 @@ TimerDriverSetTimerPeriod (
} }
/** /**
This function retrieves the period of timer interrupts in 100 ns units,
returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod This function retrieves the period of timer interrupts in 100 ns units,
is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
returned, then the timer is currently disabled. returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
@param This The EFI_TIMER_ARCH_PROTOCOL instance. is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
@param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
0 is returned, then the timer is currently disabled. returned, then the timer is currently disabled.
@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
0 is returned, then the timer is currently disabled.
@retval EFI_SUCCESS The timer period was returned in TimerPeriod.
@retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
@ -243,20 +327,34 @@ TimerDriverGetTimerPeriod (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
This function generates a soft timer interrupt. If the platform does not support soft
timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. This function generates a soft timer interrupt. If the platform does not support soft
If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
service, then a soft timer interrupt will be generated. If the timer interrupt is timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
enabled when this service is called, then the registered handler will be invoked. The
registered handler should not be able to distinguish a hardware-generated timer If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
interrupt from a software-generated timer interrupt.
service, then a soft timer interrupt will be generated. If the timer interrupt is
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
enabled when this service is called, then the registered handler will be invoked. The
@retval EFI_SUCCESS The soft timer interrupt was generated.
@retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts. registered handler should not be able to distinguish a hardware-generated timer
interrupt from a software-generated timer interrupt.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@retval EFI_SUCCESS The soft timer interrupt was generated.
@retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
@ -289,39 +387,72 @@ TimerDriverRegisterPeriodicCallback (
} }
/** /**
Interface stucture for the Timer Architectural Protocol.
Interface stucture for the Timer Architectural Protocol.
@par Protocol Description:
This protocol provides the services to initialize a periodic timer
interrupt, and to register a handler that is called each time the timer
interrupt fires. It may also provide a service to adjust the rate of the @par Protocol Description:
periodic timer interrupt. When a timer interrupt occurs, the handler is
passed the amount of time that has passed since the previous timer This protocol provides the services to initialize a periodic timer
interrupt.
interrupt, and to register a handler that is called each time the timer
@param RegisterHandler
Registers a handler that will be called each time the interrupt fires. It may also provide a service to adjust the rate of the
timer interrupt fires. TimerPeriod defines the minimum
time between timer interrupts, so TimerPeriod will also periodic timer interrupt. When a timer interrupt occurs, the handler is
be the minimum time between calls to the registered
handler. passed the amount of time that has passed since the previous timer
@param SetTimerPeriod interrupt.
Sets the period of the timer interrupt in 100 nS units.
This function is optional, and may return EFI_UNSUPPORTED.
If this function is supported, then the timer period will
be rounded up to the nearest supported timer period. @param RegisterHandler
@param GetTimerPeriod Registers a handler that will be called each time the
Retrieves the period of the timer interrupt in 100 nS units.
timer interrupt fires. TimerPeriod defines the minimum
@param GenerateSoftInterrupt
Generates a soft timer interrupt that simulates the firing of time between timer interrupts, so TimerPeriod will also
the timer interrupt. This service can be used to invoke the
registered handler if the timer interrupt has been masked for be the minimum time between calls to the registered
a period of time.
handler.
@param SetTimerPeriod
Sets the period of the timer interrupt in 100 nS units.
This function is optional, and may return EFI_UNSUPPORTED.
If this function is supported, then the timer period will
be rounded up to the nearest supported timer period.
@param GetTimerPeriod
Retrieves the period of the timer interrupt in 100 nS units.
@param GenerateSoftInterrupt
Generates a soft timer interrupt that simulates the firing of
the timer interrupt. This service can be used to invoke the
registered handler if the timer interrupt has been masked for
a period of time.
**/ **/
EFI_TIMER_ARCH_PROTOCOL gTimer = { EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler, TimerDriverRegisterHandler,
@ -335,18 +466,30 @@ TIMER_DEBUG_SUPPORT_PROTOCOL gTimerDebugSupport = {
}; };
/** /**
Initialize the state information for the Timer Architectural Protocol and
the Timer Debug support protocol that allows the debugger to break into a Initialize the state information for the Timer Architectural Protocol and
running program.
the Timer Debug support protocol that allows the debugger to break into a
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table running program.
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems @param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI