diff --git a/OvmfPkg/Bhyve/PlatformPei/Platform.c b/OvmfPkg/Bhyve/PlatformPei/Platform.c
index 11658d478c..9f1900626d 100644
--- a/OvmfPkg/Bhyve/PlatformPei/Platform.c
+++ b/OvmfPkg/Bhyve/PlatformPei/Platform.c
@@ -349,7 +349,8 @@ MiscInitialization (
   // Determine platform type and save Host Bridge DID to PCD
   //
   switch (mHostBridgeDevId) {
-    case 0x1275: // BHYVE
+    case 0x7432: // BHYVE (AMD hostbridge)
+    case 0x1275: // BHYVE (Intel hostbridge)
     case INTEL_82441_DEVICE_ID:
       PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
       Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
diff --git a/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c b/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
index 3b94630ac7..eaade4adea 100644
--- a/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
@@ -1066,7 +1066,8 @@ SetPciIntLine (
     // and should match SeaBIOS src/fw/pciinit.c *_pci_slot_get_irq()
     //
     switch (mHostBridgeDevId) {
-      case 0x1275: // BHYVE
+      case 0x7432: // BHYVE (AMD hostbridge)
+      case 0x1275: // BHYVE (Intel hostbridge)
       case INTEL_82441_DEVICE_ID:
         Idx -= 1;
         break;
@@ -1143,7 +1144,8 @@ PciAcpiInitialization (
   //
   mHostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
   switch (mHostBridgeDevId) {
-    case 0x1275: // BHYVE
+    case 0x7432: // BHYVE (AMD hostbridge)
+    case 0x1275: // BHYVE (Intel hostbridge)
     case INTEL_82441_DEVICE_ID:
       Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
       //