UefiPayloadPkg: Enhance UEFI payload for coreboot and Slim Bootloader

CorebootModulePkg and CorebootPayloadPkg originally supports coreboot only.
In order to support other bootloaders, such as Slim Bootloader, they need
be updated to be more generic.
UEFI Payload (UefiPayloadPkg) a converged package from CorebootModulePkg
and CorebootPayloadPkg with following updates:
a. Support both coreboot and Slim Bootloader
b. Removed SataControllerDxe and BaseSerialPortLib16550 to use EDK2 modules
c. Support passing bootloader parameter to UEFI payload, e.g. coreboot
   table from coreboot or HOB list from Slim Bootloader
d. Using GraphicsOutputDxe from EDK2 with minor change instead of FbGop
e. Remove the dependency to IntelFrameworkPkg and IntelFrameworkModulePkg
   and QuarkSocPkg
f. Use BaseDebugLibSerialPort library as DebugLib
g. Use HPET timer, drop legacy 8254 timer support
h. Use BaseXApicX2ApicLib instead of BaseXApicLib
i. Remove HOB gUefiFrameBufferInfoGuid to use EDK2 graphics HOBs.
j. Other clean ups

On how UefiPayloadPkg could work with coreboot/Slim Bootloader, please
refer UefiPayloadPkg/BuildAndIntegrationInstructions.txt

Once UefiPayloadPkg is checked-in, CorebootModulePkg and CorebootPayloadPkg
could be retired.

Signed-off-by: Guo Dong <guo.dong@intel.com>
Reviewed-by: Maurice Ma <maurice.ma@intel.com>
This commit is contained in:
Dong, Guo
2019-04-11 08:51:22 -07:00
committed by Maurice Ma
parent 87fcc6e863
commit 04af8bf262
50 changed files with 8566 additions and 0 deletions

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/** @file
ACPI Timer implements one instance of Timer Library.
Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiPei.h>
#include <Library/TimerLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Library/DebugLib.h>
#include <Guid/AcpiBoardInfoGuid.h>
#include <IndustryStandard/Acpi.h>
#define ACPI_TIMER_COUNT_SIZE BIT24
UINTN mPmTimerReg = 0;
/**
The constructor function enables ACPI IO space.
If ACPI I/O space not enabled, this function will enable it.
It will always return RETURN_SUCCESS.
@retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
**/
RETURN_STATUS
EFIAPI
AcpiTimerLibConstructor (
VOID
)
{
EFI_HOB_GUID_TYPE *GuidHob;
ACPI_BOARD_INFO *pAcpiBoardInfo;
//
// Find the acpi board information guid hob
//
GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
ASSERT (GuidHob != NULL);
pAcpiBoardInfo = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
mPmTimerReg = (UINTN)pAcpiBoardInfo->PmTimerRegBase;
return EFI_SUCCESS;
}
/**
Internal function to read the current tick counter of ACPI.
Internal function to read the current tick counter of ACPI.
@return The tick counter read.
**/
UINT32
InternalAcpiGetTimerTick (
VOID
)
{
if (mPmTimerReg == 0) {
AcpiTimerLibConstructor ();
}
return IoRead32 (mPmTimerReg);
}
/**
Stalls the CPU for at least the given number of ticks.
Stalls the CPU for at least the given number of ticks. It's invoked by
MicroSecondDelay() and NanoSecondDelay().
@param Delay A period of time to delay in ticks.
**/
VOID
InternalAcpiDelay (
IN UINT32 Delay
)
{
UINT32 Ticks;
UINT32 Times;
Times = Delay >> 22;
Delay &= BIT22 - 1;
do {
//
// The target timer count is calculated here
//
Ticks = InternalAcpiGetTimerTick () + Delay;
Delay = BIT22;
//
// Wait until time out
// Delay >= 2^23 could not be handled by this function
// Timer wrap-arounds are handled correctly by this function
//
while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {
CpuPause ();
}
} while (Times-- > 0);
}
/**
Stalls the CPU for at least the given number of microseconds.
Stalls the CPU for the number of microseconds specified by MicroSeconds.
@param MicroSeconds The minimum number of microseconds to delay.
@return MicroSeconds
**/
UINTN
EFIAPI
MicroSecondDelay (
IN UINTN MicroSeconds
)
{
InternalAcpiDelay (
(UINT32)DivU64x32 (
MultU64x32 (
MicroSeconds,
ACPI_TIMER_FREQUENCY
),
1000000u
)
);
return MicroSeconds;
}
/**
Stalls the CPU for at least the given number of nanoseconds.
Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
@param NanoSeconds The minimum number of nanoseconds to delay.
@return NanoSeconds
**/
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
)
{
InternalAcpiDelay (
(UINT32)DivU64x32 (
MultU64x32 (
NanoSeconds,
ACPI_TIMER_FREQUENCY
),
1000000000u
)
);
return NanoSeconds;
}
/**
Retrieves the current value of a 64-bit free running performance counter.
Retrieves the current value of a 64-bit free running performance counter. The
counter can either count up by 1 or count down by 1. If the physical
performance counter counts by a larger increment, then the counter values
must be translated. The properties of the counter can be retrieved from
GetPerformanceCounterProperties().
@return The current value of the free running performance counter.
**/
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return (UINT64)InternalAcpiGetTimerTick ();
}
/**
Retrieves the 64-bit frequency in Hz and the range of performance counter
values.
If StartValue is not NULL, then the value that the performance counter starts
with immediately after is it rolls over is returned in StartValue. If
EndValue is not NULL, then the value that the performance counter end with
immediately before it rolls over is returned in EndValue. The 64-bit
frequency of the performance counter in Hz is always returned. If StartValue
is less than EndValue, then the performance counter counts up. If StartValue
is greater than EndValue, then the performance counter counts down. For
example, a 64-bit free running counter that counts up would have a StartValue
of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
@param StartValue The value the performance counter starts with when it
rolls over.
@param EndValue The value that the performance counter ends with before
it rolls over.
@return The frequency in Hz.
**/
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
*StartValue = 0;
}
if (EndValue != NULL) {
*EndValue = ACPI_TIMER_COUNT_SIZE - 1;
}
return ACPI_TIMER_FREQUENCY;
}
/**
Converts elapsed ticks of performance counter to time in nanoseconds.
This function converts the elapsed ticks of running performance counter to
time value in unit of nanoseconds.
@param Ticks The number of elapsed ticks of running performance counter.
@return The elapsed time in nanoseconds.
**/
UINT64
EFIAPI
GetTimeInNanoSecond (
IN UINT64 Ticks
)
{
UINT64 Frequency;
UINT64 NanoSeconds;
UINT64 Remainder;
INTN Shift;
Frequency = GetPerformanceCounterProperties (NULL, NULL);
//
// Ticks
// Time = --------- x 1,000,000,000
// Frequency
//
NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);
//
// Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
// Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
// i.e. highest bit set in Remainder should <= 33.
//
Shift = MAX (0, HighBitSet64 (Remainder) - 33);
Remainder = RShiftU64 (Remainder, (UINTN) Shift);
Frequency = RShiftU64 (Frequency, (UINTN) Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds;
}

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## @file
# ACPI Timer Library Instance.
#
# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = AcpiTimerLib
FILE_GUID = A41BF616-EF77-4658-9992-D813071C34CF
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = TimerLib
CONSTRUCTOR = AcpiTimerLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
AcpiTimerLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiPayloadPkg/UefiPayloadPkg.dec
[LibraryClasses]
BaseLib
IoLib
HobLib
DebugLib
[Guids]
gUefiAcpiBoardInfoGuid

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/** @file
This library will parse the coreboot table in memory and extract those required
information.
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi/UefiBaseType.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/BlParseLib.h>
#include <IndustryStandard/Acpi.h>
#include <Coreboot.h>
/**
Convert a packed value from cbuint64 to a UINT64 value.
@param val The pointer to packed data.
@return the UNIT64 value after conversion.
**/
UINT64
cb_unpack64 (
IN struct cbuint64 val
)
{
return LShiftU64 (val.hi, 32) | val.lo;
}
/**
Returns the sum of all elements in a buffer of 16-bit values. During
calculation, the carry bits are also been added.
@param Buffer The pointer to the buffer to carry out the sum operation.
@param Length The size, in bytes, of Buffer.
@return Sum The sum of Buffer with carry bits included during additions.
**/
UINT16
CbCheckSum16 (
IN UINT16 *Buffer,
IN UINTN Length
)
{
UINT32 Sum;
UINT32 TmpValue;
UINTN Idx;
UINT8 *TmpPtr;
Sum = 0;
TmpPtr = (UINT8 *)Buffer;
for(Idx = 0; Idx < Length; Idx++) {
TmpValue = TmpPtr[Idx];
if (Idx % 2 == 1) {
TmpValue <<= 8;
}
Sum += TmpValue;
// Wrap
if (Sum >= 0x10000) {
Sum = (Sum + (Sum >> 16)) & 0xFFFF;
}
}
return (UINT16)((~Sum) & 0xFFFF);
}
/**
Check the coreboot table if it is valid.
@param Header Pointer to coreboot table
@retval TRUE The coreboot table is valid.
@retval Others The coreboot table is not valid.
**/
BOOLEAN
IsValidCbTable (
IN struct cb_header *Header
)
{
UINT16 CheckSum;
if ((Header == NULL) || (Header->table_bytes == 0)) {
return FALSE;
}
if (Header->signature != CB_HEADER_SIGNATURE) {
return FALSE;
}
//
// Check the checksum of the coreboot table header
//
CheckSum = CbCheckSum16 ((UINT16 *)Header, sizeof (*Header));
if (CheckSum != 0) {
DEBUG ((DEBUG_ERROR, "Invalid coreboot table header checksum\n"));
return FALSE;
}
CheckSum = CbCheckSum16 ((UINT16 *)((UINT8 *)Header + sizeof (*Header)), Header->table_bytes);
if (CheckSum != Header->table_checksum) {
DEBUG ((DEBUG_ERROR, "Incorrect checksum of all the coreboot table entries\n"));
return FALSE;
}
return TRUE;
}
/**
This function retrieves the parameter base address from boot loader.
This function will get bootloader specific parameter address for UEFI payload.
e.g. HobList pointer for Slim Bootloader, and coreboot table header for Coreboot.
@retval NULL Failed to find the GUID HOB.
@retval others GUIDed HOB data pointer.
**/
VOID *
EFIAPI
GetParameterBase (
VOID
)
{
struct cb_header *Header;
struct cb_record *Record;
UINT8 *TmpPtr;
UINT8 *CbTablePtr;
UINTN Idx;
//
// coreboot could pass coreboot table to UEFI payload
//
Header = (struct cb_header *)(UINTN)GET_BOOTLOADER_PARAMETER ();
if (IsValidCbTable (Header)) {
return Header;
}
//
// Find simplified coreboot table in memory range 0 ~ 4KB.
// Some GCC version does not allow directly access to NULL pointer,
// so start the search from 0x10 instead.
//
for (Idx = 16; Idx < 4096; Idx += 16) {
Header = (struct cb_header *)Idx;
if (Header->signature == CB_HEADER_SIGNATURE) {
break;
}
}
if (Idx >= 4096) {
return NULL;
}
//
// Check the coreboot header
//
if (!IsValidCbTable (Header)) {
return NULL;
}
//
// Find full coreboot table in high memory
//
CbTablePtr = NULL;
TmpPtr = (UINT8 *)Header + Header->header_bytes;
for (Idx = 0; Idx < Header->table_entries; Idx++) {
Record = (struct cb_record *)TmpPtr;
if (Record->tag == CB_TAG_FORWARD) {
CbTablePtr = (VOID *)(UINTN)((struct cb_forward *)(UINTN)Record)->forward;
break;
}
TmpPtr += Record->size;
}
//
// Check the coreboot header in high memory
//
if (!IsValidCbTable ((struct cb_header *)CbTablePtr)) {
return NULL;
}
SET_BOOTLOADER_PARAMETER ((UINT32)(UINTN)CbTablePtr);
return CbTablePtr;
}
/**
Find coreboot record with given Tag.
@param Tag The tag id to be found
@retval NULL The Tag is not found.
@retval Others The pointer to the record found.
**/
VOID *
FindCbTag (
IN UINT32 Tag
)
{
struct cb_header *Header;
struct cb_record *Record;
UINT8 *TmpPtr;
UINT8 *TagPtr;
UINTN Idx;
Header = (struct cb_header *) GetParameterBase ();
TagPtr = NULL;
TmpPtr = (UINT8 *)Header + Header->header_bytes;
for (Idx = 0; Idx < Header->table_entries; Idx++) {
Record = (struct cb_record *)TmpPtr;
if (Record->tag == Tag) {
TagPtr = TmpPtr;
break;
}
TmpPtr += Record->size;
}
return TagPtr;
}
/**
Find the given table with TableId from the given coreboot memory Root.
@param Root The coreboot memory table to be searched in
@param TableId Table id to be found
@param MemTable To save the base address of the memory table found
@param MemTableSize To save the size of memory table found
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
FindCbMemTable (
IN struct cbmem_root *Root,
IN UINT32 TableId,
OUT VOID **MemTable,
OUT UINT32 *MemTableSize
)
{
UINTN Idx;
BOOLEAN IsImdEntry;
struct cbmem_entry *Entries;
if ((Root == NULL) || (MemTable == NULL)) {
return RETURN_INVALID_PARAMETER;
}
//
// Check if the entry is CBMEM or IMD
// and handle them separately
//
Entries = Root->entries;
if (Entries[0].magic == CBMEM_ENTRY_MAGIC) {
IsImdEntry = FALSE;
} else {
Entries = (struct cbmem_entry *)((struct imd_root *)Root)->entries;
if (Entries[0].magic == IMD_ENTRY_MAGIC) {
IsImdEntry = TRUE;
} else {
return RETURN_NOT_FOUND;
}
}
for (Idx = 0; Idx < Root->num_entries; Idx++) {
if (Entries[Idx].id == TableId) {
if (IsImdEntry) {
*MemTable = (VOID *) ((UINTN)Entries[Idx].start + (UINTN)Root);
} else {
*MemTable = (VOID *) (UINTN)Entries[Idx].start;
}
if (MemTableSize != NULL) {
*MemTableSize = Entries[Idx].size;
}
DEBUG ((DEBUG_INFO, "Find CbMemTable Id 0x%x, base %p, size 0x%x\n",
TableId, *MemTable, Entries[Idx].size));
return RETURN_SUCCESS;
}
}
return RETURN_NOT_FOUND;
}
/**
Acquire the coreboot memory table with the given table id
@param TableId Table id to be searched
@param MemTable Pointer to the base address of the memory table
@param MemTableSize Pointer to the size of the memory table
@retval RETURN_SUCCESS Successfully find out the memory table.
@retval RETURN_INVALID_PARAMETER Invalid input parameters.
@retval RETURN_NOT_FOUND Failed to find the memory table.
**/
RETURN_STATUS
ParseCbMemTable (
IN UINT32 TableId,
OUT VOID **MemTable,
OUT UINT32 *MemTableSize
)
{
EFI_STATUS Status;
struct cb_memory *rec;
struct cb_memory_range *Range;
UINT64 Start;
UINT64 Size;
UINTN Index;
struct cbmem_root *CbMemRoot;
if (MemTable == NULL) {
return RETURN_INVALID_PARAMETER;
}
*MemTable = NULL;
Status = RETURN_NOT_FOUND;
//
// Get the coreboot memory table
//
rec = (struct cb_memory *)FindCbTag (CB_TAG_MEMORY);
if (rec == NULL) {
return Status;
}
for (Index = 0; Index < MEM_RANGE_COUNT(rec); Index++) {
Range = MEM_RANGE_PTR(rec, Index);
Start = cb_unpack64(Range->start);
Size = cb_unpack64(Range->size);
if ((Range->type == CB_MEM_TABLE) && (Start > 0x1000)) {
CbMemRoot = (struct cbmem_root *)(UINTN)(Start + Size - DYN_CBMEM_ALIGN_SIZE);
Status = FindCbMemTable (CbMemRoot, TableId, MemTable, MemTableSize);
if (!EFI_ERROR (Status)) {
break;
}
}
}
return Status;
}
/**
Acquire the memory information from the coreboot table in memory.
@param MemInfoCallback The callback routine
@param Params Pointer to the callback routine parameter
@retval RETURN_SUCCESS Successfully find out the memory information.
@retval RETURN_NOT_FOUND Failed to find the memory information.
**/
RETURN_STATUS
EFIAPI
ParseMemoryInfo (
IN BL_MEM_INFO_CALLBACK MemInfoCallback,
IN VOID *Params
)
{
struct cb_memory *rec;
struct cb_memory_range *Range;
UINTN Index;
MEMROY_MAP_ENTRY MemoryMap;
//
// Get the coreboot memory table
//
rec = (struct cb_memory *)FindCbTag (CB_TAG_MEMORY);
if (rec == NULL) {
return RETURN_NOT_FOUND;
}
for (Index = 0; Index < MEM_RANGE_COUNT(rec); Index++) {
Range = MEM_RANGE_PTR(rec, Index);
MemoryMap.Base = cb_unpack64(Range->start);
MemoryMap.Size = cb_unpack64(Range->size);
MemoryMap.Type = (UINT8)Range->type;
MemoryMap.Flag = 0;
DEBUG ((DEBUG_INFO, "%d. %016lx - %016lx [%02x]\n",
Index, MemoryMap.Base, MemoryMap.Base + MemoryMap.Size - 1, MemoryMap.Type));
MemInfoCallback (&MemoryMap, Params);
}
return RETURN_SUCCESS;
}
/**
Acquire acpi table and smbios table from coreboot
@param SystemTableInfo Pointer to the system table info
@retval RETURN_SUCCESS Successfully find out the tables.
@retval RETURN_NOT_FOUND Failed to find the tables.
**/
RETURN_STATUS
EFIAPI
ParseSystemTable (
OUT SYSTEM_TABLE_INFO *SystemTableInfo
)
{
EFI_STATUS Status;
VOID *MemTable;
UINT32 MemTableSize;
Status = ParseCbMemTable (SIGNATURE_32 ('T', 'B', 'M', 'S'), &MemTable, &MemTableSize);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
SystemTableInfo->SmbiosTableBase = (UINT64) (UINTN)MemTable;
SystemTableInfo->SmbiosTableSize = MemTableSize;
Status = ParseCbMemTable (SIGNATURE_32 ('I', 'P', 'C', 'A'), &MemTable, &MemTableSize);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
SystemTableInfo->AcpiTableBase = (UINT64) (UINTN)MemTable;
SystemTableInfo->AcpiTableSize = MemTableSize;
return Status;
}
/**
Find the serial port information
@param SERIAL_PORT_INFO Pointer to serial port info structure
@retval RETURN_SUCCESS Successfully find the serial port information.
@retval RETURN_NOT_FOUND Failed to find the serial port information .
**/
RETURN_STATUS
EFIAPI
ParseSerialInfo (
OUT SERIAL_PORT_INFO *SerialPortInfo
)
{
struct cb_serial *CbSerial;
CbSerial = FindCbTag (CB_TAG_SERIAL);
if (CbSerial == NULL) {
return RETURN_NOT_FOUND;
}
SerialPortInfo->BaseAddr = CbSerial->baseaddr;
SerialPortInfo->RegWidth = CbSerial->regwidth;
SerialPortInfo->Type = CbSerial->type;
SerialPortInfo->Baud = CbSerial->baud;
SerialPortInfo->InputHertz = CbSerial->input_hertz;
SerialPortInfo->UartPciAddr = CbSerial->uart_pci_addr;
return RETURN_SUCCESS;
}
/**
Find the video frame buffer information
@param GfxInfo Pointer to the EFI_PEI_GRAPHICS_INFO_HOB structure
@retval RETURN_SUCCESS Successfully find the video frame buffer information.
@retval RETURN_NOT_FOUND Failed to find the video frame buffer information .
**/
RETURN_STATUS
EFIAPI
ParseGfxInfo (
OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo
)
{
struct cb_framebuffer *CbFbRec;
EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *GfxMode;
if (GfxInfo == NULL) {
return RETURN_INVALID_PARAMETER;
}
CbFbRec = FindCbTag (CB_TAG_FRAMEBUFFER);
if (CbFbRec == NULL) {
return RETURN_NOT_FOUND;
}
DEBUG ((DEBUG_INFO, "Found coreboot video frame buffer information\n"));
DEBUG ((DEBUG_INFO, "physical_address: 0x%lx\n", CbFbRec->physical_address));
DEBUG ((DEBUG_INFO, "x_resolution: 0x%x\n", CbFbRec->x_resolution));
DEBUG ((DEBUG_INFO, "y_resolution: 0x%x\n", CbFbRec->y_resolution));
DEBUG ((DEBUG_INFO, "bits_per_pixel: 0x%x\n", CbFbRec->bits_per_pixel));
DEBUG ((DEBUG_INFO, "bytes_per_line: 0x%x\n", CbFbRec->bytes_per_line));
DEBUG ((DEBUG_INFO, "red_mask_size: 0x%x\n", CbFbRec->red_mask_size));
DEBUG ((DEBUG_INFO, "red_mask_pos: 0x%x\n", CbFbRec->red_mask_pos));
DEBUG ((DEBUG_INFO, "green_mask_size: 0x%x\n", CbFbRec->green_mask_size));
DEBUG ((DEBUG_INFO, "green_mask_pos: 0x%x\n", CbFbRec->green_mask_pos));
DEBUG ((DEBUG_INFO, "blue_mask_size: 0x%x\n", CbFbRec->blue_mask_size));
DEBUG ((DEBUG_INFO, "blue_mask_pos: 0x%x\n", CbFbRec->blue_mask_pos));
DEBUG ((DEBUG_INFO, "reserved_mask_size: 0x%x\n", CbFbRec->reserved_mask_size));
DEBUG ((DEBUG_INFO, "reserved_mask_pos: 0x%x\n", CbFbRec->reserved_mask_pos));
GfxMode = &GfxInfo->GraphicsMode;
GfxMode->Version = 0;
GfxMode->HorizontalResolution = CbFbRec->x_resolution;
GfxMode->VerticalResolution = CbFbRec->y_resolution;
GfxMode->PixelsPerScanLine = (CbFbRec->bytes_per_line << 3) / CbFbRec->bits_per_pixel;
if ((CbFbRec->red_mask_pos == 0) && (CbFbRec->green_mask_pos == 8) && (CbFbRec->blue_mask_pos == 16)) {
GfxMode->PixelFormat = PixelRedGreenBlueReserved8BitPerColor;
} else if ((CbFbRec->blue_mask_pos == 0) && (CbFbRec->green_mask_pos == 8) && (CbFbRec->red_mask_pos == 16)) {
GfxMode->PixelFormat = PixelBlueGreenRedReserved8BitPerColor;
}
GfxMode->PixelInformation.RedMask = ((1 << CbFbRec->red_mask_size) - 1) << CbFbRec->red_mask_pos;
GfxMode->PixelInformation.GreenMask = ((1 << CbFbRec->green_mask_size) - 1) << CbFbRec->green_mask_pos;
GfxMode->PixelInformation.BlueMask = ((1 << CbFbRec->blue_mask_size) - 1) << CbFbRec->blue_mask_pos;
GfxMode->PixelInformation.ReservedMask = ((1 << CbFbRec->reserved_mask_size) - 1) << CbFbRec->reserved_mask_pos;
GfxInfo->FrameBufferBase = CbFbRec->physical_address;
GfxInfo->FrameBufferSize = CbFbRec->bytes_per_line * CbFbRec->y_resolution;
return RETURN_SUCCESS;
}
/**
Find the video frame buffer device information
@param GfxDeviceInfo Pointer to the EFI_PEI_GRAPHICS_DEVICE_INFO_HOB structure
@retval RETURN_SUCCESS Successfully find the video frame buffer information.
@retval RETURN_NOT_FOUND Failed to find the video frame buffer information.
**/
RETURN_STATUS
EFIAPI
ParseGfxDeviceInfo (
OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo
)
{
return RETURN_NOT_FOUND;
}

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## @file
# Coreboot Table Parse Library.
#
# Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = CbParseLib
FILE_GUID = 49EDFC9E-5945-4386-9C0B-C9B60CD45BB1
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = BlParseLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
CbParseLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiPayloadPkg/UefiPayloadPkg.dec
[LibraryClasses]
BaseLib
BaseMemoryLib
IoLib
DebugLib
PcdLib
[Pcd]
gUefiPayloadPkgTokenSpaceGuid.PcdPayloadStackTop

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/** @file
Header file of PciHostBridgeLib.
Copyright (C) 2016, Red Hat, Inc.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PCI_HOST_BRIDGE_H
#define _PCI_HOST_BRIDGE_H
typedef struct {
ACPI_HID_DEVICE_PATH AcpiDevicePath;
EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} CB_PCI_ROOT_BRIDGE_DEVICE_PATH;
PCI_ROOT_BRIDGE *
ScanForRootBridges (
UINTN *NumberOfRootBridges
);
/**
Initialize a PCI_ROOT_BRIDGE structure.
@param[in] Supports Supported attributes.
@param[in] Attributes Initial attributes.
@param[in] AllocAttributes Allocation attributes.
@param[in] RootBusNumber The bus number to store in RootBus.
@param[in] MaxSubBusNumber The inclusive maximum bus number that can be
assigned to any subordinate bus found behind any
PCI bridge hanging off this root bus.
The caller is responsible for ensuring that
RootBusNumber <= MaxSubBusNumber. If
RootBusNumber equals MaxSubBusNumber, then the
root bus has no room for subordinate buses.
@param[in] Io IO aperture.
@param[in] Mem MMIO aperture.
@param[in] MemAbove4G MMIO aperture above 4G.
@param[in] PMem Prefetchable MMIO aperture.
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
@param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
caller) that should be filled in by this
function.
@retval EFI_SUCCESS Initialization successful. A device path
consisting of an ACPI device path node, with
UID = RootBusNumber, has been allocated and
linked into RootBus.
@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
**/
EFI_STATUS
InitRootBridge (
IN UINT64 Supports,
IN UINT64 Attributes,
IN UINT64 AllocAttributes,
IN UINT8 RootBusNumber,
IN UINT8 MaxSubBusNumber,
IN PCI_ROOT_BRIDGE_APERTURE *Io,
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
OUT PCI_ROOT_BRIDGE *RootBus
);
#endif

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/** @file
Library instance of PciHostBridgeLib library class for coreboot.
Copyright (C) 2016, Red Hat, Inc.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <IndustryStandard/Pci.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PciHostBridgeLib.h>
#include <Library/PciLib.h>
#include "PciHostBridge.h"
STATIC
CONST
CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
{
{
ACPI_DEVICE_PATH,
ACPI_DP,
{
(UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
(UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
}
},
EISA_PNP_ID(0x0A03), // HID
0 // UID
},
{
END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{
END_DEVICE_PATH_LENGTH,
0
}
}
};
/**
Initialize a PCI_ROOT_BRIDGE structure.
@param[in] Supports Supported attributes.
@param[in] Attributes Initial attributes.
@param[in] AllocAttributes Allocation attributes.
@param[in] RootBusNumber The bus number to store in RootBus.
@param[in] MaxSubBusNumber The inclusive maximum bus number that can be
assigned to any subordinate bus found behind any
PCI bridge hanging off this root bus.
The caller is responsible for ensuring that
RootBusNumber <= MaxSubBusNumber. If
RootBusNumber equals MaxSubBusNumber, then the
root bus has no room for subordinate buses.
@param[in] Io IO aperture.
@param[in] Mem MMIO aperture.
@param[in] MemAbove4G MMIO aperture above 4G.
@param[in] PMem Prefetchable MMIO aperture.
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
@param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
caller) that should be filled in by this
function.
@retval EFI_SUCCESS Initialization successful. A device path
consisting of an ACPI device path node, with
UID = RootBusNumber, has been allocated and
linked into RootBus.
@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
**/
EFI_STATUS
InitRootBridge (
IN UINT64 Supports,
IN UINT64 Attributes,
IN UINT64 AllocAttributes,
IN UINT8 RootBusNumber,
IN UINT8 MaxSubBusNumber,
IN PCI_ROOT_BRIDGE_APERTURE *Io,
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
OUT PCI_ROOT_BRIDGE *RootBus
)
{
CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
//
// Be safe if other fields are added to PCI_ROOT_BRIDGE later.
//
ZeroMem (RootBus, sizeof *RootBus);
RootBus->Segment = 0;
RootBus->Supports = Supports;
RootBus->Attributes = Attributes;
RootBus->DmaAbove4G = FALSE;
RootBus->AllocationAttributes = AllocAttributes;
RootBus->Bus.Base = RootBusNumber;
RootBus->Bus.Limit = MaxSubBusNumber;
CopyMem (&RootBus->Io, Io, sizeof (*Io));
CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));
CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));
CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));
CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));
RootBus->NoExtendedConfigSpace = FALSE;
DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),
&mRootBridgeDevicePathTemplate);
if (DevicePath == NULL) {
DEBUG ((DEBUG_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
return EFI_OUT_OF_RESOURCES;
}
DevicePath->AcpiDevicePath.UID = RootBusNumber;
RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
DEBUG ((DEBUG_INFO,
"%a: populated root bus %d, with room for %d subordinate bus(es)\n",
__FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
return EFI_SUCCESS;
}
/**
Return all the root bridge instances in an array.
@param Count Return the count of root bridge instances.
@return All the root bridge instances in an array.
The array should be passed into PciHostBridgeFreeRootBridges()
when it's not used.
**/
PCI_ROOT_BRIDGE *
EFIAPI
PciHostBridgeGetRootBridges (
UINTN *Count
)
{
return ScanForRootBridges (Count);
}
/**
Free the root bridge instances array returned from
PciHostBridgeGetRootBridges().
@param The root bridge instances array.
@param The count of the array.
**/
VOID
EFIAPI
PciHostBridgeFreeRootBridges (
PCI_ROOT_BRIDGE *Bridges,
UINTN Count
)
{
if (Bridges == NULL && Count == 0) {
return;
}
ASSERT (Bridges != NULL && Count > 0);
do {
--Count;
FreePool (Bridges[Count].DevicePath);
} while (Count > 0);
FreePool (Bridges);
}
/**
Inform the platform that the resource conflict happens.
@param HostBridgeHandle Handle of the Host Bridge.
@param Configuration Pointer to PCI I/O and PCI memory resource
descriptors. The Configuration contains the resources
for all the root bridges. The resource for each root
bridge is terminated with END descriptor and an
additional END is appended indicating the end of the
entire resources. The resource descriptor field
values follow the description in
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
.SubmitResources().
**/
VOID
EFIAPI
PciHostBridgeResourceConflict (
EFI_HANDLE HostBridgeHandle,
VOID *Configuration
)
{
//
// coreboot UEFI Payload does not do PCI enumeration and should not call this
// library interface.
//
ASSERT (FALSE);
}

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## @file
# Library instance of PciHostBridgeLib library class for coreboot.
#
# Copyright (C) 2016, Red Hat, Inc.
# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PciHostBridgeLib
FILE_GUID = 62EE5269-CFFD-43a3-BE3F-622FC79F467E
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PciHostBridgeLib
#
# The following information is for reference only and not required by the build
# tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
PciHostBridge.h
PciHostBridgeLib.c
PciHostBridgeSupport.c
[Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
[LibraryClasses]
BaseMemoryLib
DebugLib
DevicePathLib
MemoryAllocationLib
PciLib

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/** @file
Scan the entire PCI bus for root bridges to support coreboot UEFI payload.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <IndustryStandard/Pci.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PciHostBridgeLib.h>
#include <Library/PciLib.h>
#include "PciHostBridge.h"
/**
Adjust the collected PCI resource.
@param[in] Io IO aperture.
@param[in] Mem MMIO aperture.
@param[in] MemAbove4G MMIO aperture above 4G.
@param[in] PMem Prefetchable MMIO aperture.
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
**/
VOID
AdjustRootBridgeResource (
IN PCI_ROOT_BRIDGE_APERTURE *Io,
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
)
{
UINT64 Mask;
//
// For now try to downgrade everything into MEM32 since
// - coreboot does not assign resource above 4GB
// - coreboot might allocate interleaved MEM32 and PMEM32 resource
// in some cases
//
if (PMem->Base < Mem->Base) {
Mem->Base = PMem->Base;
}
if (PMem->Limit > Mem->Limit) {
Mem->Limit = PMem->Limit;
}
PMem->Base = MAX_UINT64;
PMem->Limit = 0;
if (MemAbove4G->Base < 0x100000000ULL) {
if (MemAbove4G->Base < Mem->Base) {
Mem->Base = MemAbove4G->Base;
}
if (MemAbove4G->Limit > Mem->Limit) {
Mem->Limit = MemAbove4G->Limit;
}
MemAbove4G->Base = MAX_UINT64;
MemAbove4G->Limit = 0;
}
if (PMemAbove4G->Base < 0x100000000ULL) {
if (PMemAbove4G->Base < Mem->Base) {
Mem->Base = PMemAbove4G->Base;
}
if (PMemAbove4G->Limit > Mem->Limit) {
Mem->Limit = PMemAbove4G->Limit;
}
PMemAbove4G->Base = MAX_UINT64;
PMemAbove4G->Limit = 0;
}
//
// Align IO resource at 4K boundary
//
Mask = 0xFFFULL;
Io->Limit = ((Io->Limit + Mask) & ~Mask) - 1;
if (Io->Base != MAX_UINT64) {
Io->Base &= ~Mask;
}
//
// Align MEM resource at 1MB boundary
//
Mask = 0xFFFFFULL;
Mem->Limit = ((Mem->Limit + Mask) & ~Mask) - 1;
if (Mem->Base != MAX_UINT64) {
Mem->Base &= ~Mask;
}
}
/**
Probe a bar is existed or not.
@param[in] Address PCI address for the BAR.
@param[out] OriginalValue The original bar value returned.
@param[out] Value The probed bar value returned.
**/
STATIC
VOID
PcatPciRootBridgeBarExisted (
IN UINT64 Address,
OUT UINT32 *OriginalValue,
OUT UINT32 *Value
)
{
UINTN PciAddress;
PciAddress = (UINTN)Address;
//
// Preserve the original value
//
*OriginalValue = PciRead32 (PciAddress);
//
// Disable timer interrupt while the BAR is probed
//
DisableInterrupts ();
PciWrite32 (PciAddress, 0xFFFFFFFF);
*Value = PciRead32 (PciAddress);
PciWrite32 (PciAddress, *OriginalValue);
//
// Enable interrupt
//
EnableInterrupts ();
}
/**
Parse PCI bar and collect the assigned PCI resource information.
@param[in] Command Supported attributes.
@param[in] Bus PCI bus number.
@param[in] Device PCI device number.
@param[in] Function PCI function number.
@param[in] BarOffsetBase PCI bar start offset.
@param[in] BarOffsetEnd PCI bar end offset.
@param[in] Io IO aperture.
@param[in] Mem MMIO aperture.
@param[in] MemAbove4G MMIO aperture above 4G.
@param[in] PMem Prefetchable MMIO aperture.
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
**/
STATIC
VOID
PcatPciRootBridgeParseBars (
IN UINT16 Command,
IN UINTN Bus,
IN UINTN Device,
IN UINTN Function,
IN UINTN BarOffsetBase,
IN UINTN BarOffsetEnd,
IN PCI_ROOT_BRIDGE_APERTURE *Io,
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
)
{
UINT32 OriginalValue;
UINT32 Value;
UINT32 OriginalUpperValue;
UINT32 UpperValue;
UINT64 Mask;
UINTN Offset;
UINTN LowBit;
UINT64 Base;
UINT64 Length;
UINT64 Limit;
PCI_ROOT_BRIDGE_APERTURE *MemAperture;
for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {
PcatPciRootBridgeBarExisted (
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
&OriginalValue, &Value
);
if (Value == 0) {
continue;
}
if ((Value & BIT0) == BIT0) {
//
// IO Bar
//
if (Command & EFI_PCI_COMMAND_IO_SPACE) {
Mask = 0xfffffffc;
Base = OriginalValue & Mask;
Length = ((~(Value & Mask)) & Mask) + 0x04;
if (!(Value & 0xFFFF0000)) {
Length &= 0x0000FFFF;
}
Limit = Base + Length - 1;
if ((Base > 0) && (Base < Limit)) {
if (Io->Base > Base) {
Io->Base = Base;
}
if (Io->Limit < Limit) {
Io->Limit = Limit;
}
}
}
} else {
//
// Mem Bar
//
if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
Mask = 0xfffffff0;
Base = OriginalValue & Mask;
Length = Value & Mask;
if ((Value & (BIT1 | BIT2)) == 0) {
//
// 32bit
//
Length = ((~Length) + 1) & 0xffffffff;
if ((Value & BIT3) == BIT3) {
MemAperture = PMem;
} else {
MemAperture = Mem;
}
} else {
//
// 64bit
//
Offset += 4;
PcatPciRootBridgeBarExisted (
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
&OriginalUpperValue,
&UpperValue
);
Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
if (Length != 0) {
LowBit = LowBitSet64 (Length);
Length = LShiftU64 (1ULL, LowBit);
}
if ((Value & BIT3) == BIT3) {
MemAperture = PMemAbove4G;
} else {
MemAperture = MemAbove4G;
}
}
Limit = Base + Length - 1;
if ((Base > 0) && (Base < Limit)) {
if (MemAperture->Base > Base) {
MemAperture->Base = Base;
}
if (MemAperture->Limit < Limit) {
MemAperture->Limit = Limit;
}
}
}
}
}
}
/**
Scan for all root bridges in platform.
@param[out] NumberOfRootBridges Number of root bridges detected
@retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
**/
PCI_ROOT_BRIDGE *
ScanForRootBridges (
OUT UINTN *NumberOfRootBridges
)
{
UINTN PrimaryBus;
UINTN SubBus;
UINT8 Device;
UINT8 Function;
UINTN NumberOfDevices;
UINTN Address;
PCI_TYPE01 Pci;
UINT64 Attributes;
UINT64 Base;
UINT64 Limit;
UINT64 Value;
PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;
PCI_ROOT_BRIDGE *RootBridges;
UINTN BarOffsetEnd;
*NumberOfRootBridges = 0;
RootBridges = NULL;
//
// After scanning all the PCI devices on the PCI root bridge's primary bus,
// update the Primary Bus Number for the next PCI root bridge to be this PCI
// root bridge's subordinate bus number + 1.
//
for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
SubBus = PrimaryBus;
Attributes = 0;
ZeroMem (&Io, sizeof (Io));
ZeroMem (&Mem, sizeof (Mem));
ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
ZeroMem (&PMem, sizeof (PMem));
ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
//
// Scan all the PCI devices on the primary bus of the PCI root bridge
//
for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
//
// Compute the PCI configuration address of the PCI device to probe
//
Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);
//
// Read the Vendor ID from the PCI Configuration Header
//
if (PciRead16 (Address) == MAX_UINT16) {
if (Function == 0) {
//
// If the PCI Configuration Read fails, or a PCI device does not
// exist, then skip this entire PCI device
//
break;
} else {
//
// If PCI function != 0, VendorId == 0xFFFF, we continue to search
// PCI function.
//
continue;
}
}
//
// Read the entire PCI Configuration Header
//
PciReadBuffer (Address, sizeof (Pci), &Pci);
//
// Increment the number of PCI device found on the primary bus of the
// PCI root bridge
//
NumberOfDevices++;
//
// Look for devices with the VGA Palette Snoop enabled in the COMMAND
// register of the PCI Config Header
//
if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
}
BarOffsetEnd = 0;
//
// PCI-PCI Bridge
//
if (IS_PCI_BRIDGE (&Pci)) {
//
// Get the Bus range that the PPB is decoding
//
if (Pci.Bridge.SubordinateBus > SubBus) {
//
// If the subordinate bus number of the PCI-PCI bridge is greater
// than the PCI root bridge's current subordinate bus number,
// then update the PCI root bridge's subordinate bus number
//
SubBus = Pci.Bridge.SubordinateBus;
}
//
// Get the I/O range that the PPB is decoding
//
Value = Pci.Bridge.IoBase & 0x0f;
Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
if (Value == BIT0) {
Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);
Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);
}
if ((Base > 0) && (Base < Limit)) {
if (Io.Base > Base) {
Io.Base = Base;
}
if (Io.Limit < Limit) {
Io.Limit = Limit;
}
}
//
// Get the Memory range that the PPB is decoding
//
Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;
Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
if ((Base > 0) && (Base < Limit)) {
if (Mem.Base > Base) {
Mem.Base = Base;
}
if (Mem.Limit < Limit) {
Mem.Limit = Limit;
}
}
//
// Get the Prefetchable Memory range that the PPB is decoding
//
Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;
Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
<< 16) | 0xfffff;
MemAperture = &PMem;
if (Value == BIT0) {
Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
MemAperture = &PMemAbove4G;
}
if ((Base > 0) && (Base < Limit)) {
if (MemAperture->Base > Base) {
MemAperture->Base = Base;
}
if (MemAperture->Limit < Limit) {
MemAperture->Limit = Limit;
}
}
//
// Look at the PPB Configuration for legacy decoding attributes
//
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)
== EFI_PCI_BRIDGE_CONTROL_ISA) {
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
}
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)
== EFI_PCI_BRIDGE_CONTROL_VGA) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)
!= 0) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
}
}
BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);
} else {
//
// Parse the BARs of the PCI device to get what I/O Ranges, Memory
// Ranges, and Prefetchable Memory Ranges the device is decoding
//
if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {
BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);
}
}
PcatPciRootBridgeParseBars (
Pci.Hdr.Command,
PrimaryBus,
Device,
Function,
OFFSET_OF (PCI_TYPE00, Device.Bar),
BarOffsetEnd,
&Io,
&Mem, &MemAbove4G,
&PMem, &PMemAbove4G
);
//
// See if the PCI device is an IDE controller
//
if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,
PCI_CLASS_MASS_STORAGE_IDE)) {
if (Pci.Hdr.ClassCode[0] & 0x80) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
if (Pci.Hdr.ClassCode[0] & 0x01) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
}
if (Pci.Hdr.ClassCode[0] & 0x04) {
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
}
}
//
// See if the PCI device is a legacy VGA controller or
// a standard VGA controller
//
if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||
IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)
) {
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
}
//
// See if the PCI Device is a PCI - ISA or PCI - EISA
// or ISA_POSITIVE_DECODE Bridge device
//
if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
}
}
//
// If this device is not a multi function device, then skip the rest
// of this PCI device
//
if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
break;
}
}
}
//
// If at least one PCI device was found on the primary bus of this PCI
// root bridge, then the PCI root bridge exists.
//
if (NumberOfDevices > 0) {
RootBridges = ReallocatePool (
(*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),
(*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),
RootBridges
);
ASSERT (RootBridges != NULL);
AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);
InitRootBridge (
Attributes, Attributes, 0,
(UINT8) PrimaryBus, (UINT8) SubBus,
&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,
&RootBridges[*NumberOfRootBridges]
);
RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;
//
// Increment the index for the next PCI Root Bridge
//
(*NumberOfRootBridges)++;
}
}
return RootBridges;
}

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/** @file
This file include all platform action which can be customized
by IBV/OEM.
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PlatformBootManager.h"
#include "PlatformConsole.h"
VOID
InstallReadyToLock (
VOID
)
{
EFI_STATUS Status;
EFI_HANDLE Handle;
EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
DEBUG((DEBUG_INFO,"InstallReadyToLock entering......\n"));
//
// Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter
// Since PI1.2.1, we need signal EndOfDxe as ExitPmAuth
//
EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid);
DEBUG((DEBUG_INFO,"All EndOfDxe callbacks have returned successfully\n"));
//
// Install DxeSmmReadyToLock protocol in order to lock SMM
//
Status = gBS->LocateProtocol (&gEfiSmmAccess2ProtocolGuid, NULL, (VOID **) &SmmAccess);
if (!EFI_ERROR (Status)) {
Handle = NULL;
Status = gBS->InstallProtocolInterface (
&Handle,
&gEfiDxeSmmReadyToLockProtocolGuid,
EFI_NATIVE_INTERFACE,
NULL
);
ASSERT_EFI_ERROR (Status);
}
DEBUG((DEBUG_INFO,"InstallReadyToLock end\n"));
return;
}
/**
Return the index of the load option in the load option array.
The function consider two load options are equal when the
OptionType, Attributes, Description, FilePath and OptionalData are equal.
@param Key Pointer to the load option to be found.
@param Array Pointer to the array of load options to be found.
@param Count Number of entries in the Array.
@retval -1 Key wasn't found in the Array.
@retval 0 ~ Count-1 The index of the Key in the Array.
**/
INTN
PlatformFindLoadOption (
IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
IN UINTN Count
)
{
UINTN Index;
for (Index = 0; Index < Count; Index++) {
if ((Key->OptionType == Array[Index].OptionType) &&
(Key->Attributes == Array[Index].Attributes) &&
(StrCmp (Key->Description, Array[Index].Description) == 0) &&
(CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&
(Key->OptionalDataSize == Array[Index].OptionalDataSize) &&
(CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {
return (INTN) Index;
}
}
return -1;
}
/**
Register a boot option using a file GUID in the FV.
@param FileGuid The file GUID name in FV.
@param Description The boot option description.
@param Attributes The attributes used for the boot option loading.
**/
VOID
PlatformRegisterFvBootOption (
EFI_GUID *FileGuid,
CHAR16 *Description,
UINT32 Attributes
)
{
EFI_STATUS Status;
UINTN OptionIndex;
EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
UINTN BootOptionCount;
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &LoadedImage);
ASSERT_EFI_ERROR (Status);
EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
DevicePath = AppendDevicePathNode (
DevicePathFromHandle (LoadedImage->DeviceHandle),
(EFI_DEVICE_PATH_PROTOCOL *) &FileNode
);
Status = EfiBootManagerInitializeLoadOption (
&NewOption,
LoadOptionNumberUnassigned,
LoadOptionTypeBoot,
Attributes,
Description,
DevicePath,
NULL,
0
);
if (!EFI_ERROR (Status)) {
BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);
OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);
if (OptionIndex == -1) {
Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);
ASSERT_EFI_ERROR (Status);
}
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
}
}
/**
Do the platform specific action before the console is connected.
Such as:
Update console variable;
Register new Driver#### or Boot####;
Signal ReadyToLock event.
**/
VOID
EFIAPI
PlatformBootManagerBeforeConsole (
VOID
)
{
EFI_INPUT_KEY Enter;
EFI_INPUT_KEY F2;
EFI_INPUT_KEY Down;
EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
PlatformConsoleInit ();
//
// Register ENTER as CONTINUE key
//
Enter.ScanCode = SCAN_NULL;
Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
//
// Map F2 to Boot Manager Menu
//
F2.ScanCode = SCAN_F2;
F2.UnicodeChar = CHAR_NULL;
EfiBootManagerGetBootManagerMenu (&BootOption);
EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);
//
// Also add Down key to Boot Manager Menu since some serial terminals don't support F2 key.
//
Down.ScanCode = SCAN_DOWN;
Down.UnicodeChar = CHAR_NULL;
EfiBootManagerGetBootManagerMenu (&BootOption);
EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &Down, NULL);
//
// Install ready to lock.
// This needs to be done before option rom dispatched.
//
InstallReadyToLock ();
//
// Dispatch deferred images after EndOfDxe event and ReadyToLock installation.
//
EfiBootManagerDispatchDeferredImages ();
}
/**
Do the platform specific action after the console is connected.
Such as:
Dynamically switch output mode;
Signal console ready platform customized event;
Run diagnostics like memory testing;
Connect certain devices;
Dispatch additional option roms.
**/
VOID
EFIAPI
PlatformBootManagerAfterConsole (
VOID
)
{
EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;
EFI_GRAPHICS_OUTPUT_BLT_PIXEL White;
Black.Blue = Black.Green = Black.Red = Black.Reserved = 0;
White.Blue = White.Green = White.Red = White.Reserved = 0xFF;
EfiBootManagerConnectAll ();
EfiBootManagerRefreshAllBootOption ();
//
// Register UEFI Shell
//
PlatformRegisterFvBootOption (PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE);
Print (
L"\n"
L"F2 or Down to enter Boot Manager Menu.\n"
L"ENTER to boot directly.\n"
L"\n"
);
}
/**
This function is called each second during the boot manager waits the timeout.
@param TimeoutRemain The remaining timeout.
**/
VOID
EFIAPI
PlatformBootManagerWaitCallback (
UINT16 TimeoutRemain
)
{
return;
}
/**
The function is called when no boot option could be launched,
including platform recovery options and options pointing to applications
built into firmware volumes.
If this function returns, BDS attempts to enter an infinite loop.
**/
VOID
EFIAPI
PlatformBootManagerUnableToBoot (
VOID
)
{
return;
}

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/**@file
Head file for BDS Platform specific code
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PLATFORM_BOOT_MANAGER_H
#define _PLATFORM_BOOT_MANAGER_H
#include <PiDxe.h>
#include <Protocol/LoadedImage.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootManagerLib.h>
#include <Library/PcdLib.h>
#include <Library/DevicePathLib.h>
#include <Library/HiiLib.h>
#include <Library/PrintLib.h>
#include <Library/DxeServicesLib.h>
#include <Library/BootLogoLib.h>
#include <Protocol/SmmAccess2.h>
typedef struct {
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN ConnectType;
} PLATFORM_CONSOLE_CONNECT_ENTRY;
extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
#define gEndEntire \
{ \
END_DEVICE_PATH_TYPE,\
END_ENTIRE_DEVICE_PATH_SUBTYPE,\
{ END_DEVICE_PATH_LENGTH, 0 },\
}
#define CONSOLE_OUT BIT0
#define CONSOLE_IN BIT1
#define STD_ERROR BIT2
#define CLASS_HID 3
#define SUBCLASS_BOOT 1
#define PROTOCOL_KEYBOARD 1
typedef struct {
USB_CLASS_DEVICE_PATH UsbClass;
EFI_DEVICE_PATH_PROTOCOL End;
} USB_CLASS_FORMAT_DEVICE_PATH;
typedef struct {
VENDOR_DEVICE_PATH VendorDevicePath;
UINT32 Instance;
} WIN_NT_VENDOR_DEVICE_PATH_NODE;
//
// Below is the platform console device path
//
typedef struct {
VENDOR_DEVICE_PATH NtBus;
WIN_NT_VENDOR_DEVICE_PATH_NODE SerialDevice;
UART_DEVICE_PATH Uart;
VENDOR_DEVICE_PATH TerminalType;
EFI_DEVICE_PATH_PROTOCOL End;
} NT_ISA_SERIAL_DEVICE_PATH;
typedef struct {
VENDOR_DEVICE_PATH NtBus;
WIN_NT_VENDOR_DEVICE_PATH_NODE NtGopDevice;
EFI_DEVICE_PATH_PROTOCOL End;
} NT_PLATFORM_GOP_DEVICE_PATH;
extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath;
/**
Use SystemTable Conout to stop video based Simple Text Out consoles from going
to the video device. Put up LogoFile on every video device that is a console.
@param[in] LogoFile File name of logo to display on the center of the screen.
@retval EFI_SUCCESS ConsoleControl has been flipped to graphics and logo displayed.
@retval EFI_UNSUPPORTED Logo not found
**/
EFI_STATUS
PlatformBootManagerEnableQuietBoot (
IN EFI_GUID *LogoFile
);
/**
Use SystemTable Conout to turn on video based Simple Text Out consoles. The
Simple Text Out screens will now be synced up with all non video output devices
@retval EFI_SUCCESS UGA devices are back in text mode and synced up.
**/
EFI_STATUS
PlatformBootManagerDisableQuietBoot (
VOID
);
/**
Show progress bar with title above it. It only works in Graphics mode.
@param TitleForeground Foreground color for Title.
@param TitleBackground Background color for Title.
@param Title Title above progress bar.
@param ProgressColor Progress bar color.
@param Progress Progress (0-100)
@param PreviousValue The previous value of the progress.
@retval EFI_STATUS Success update the progress bar
**/
EFI_STATUS
PlatformBootManagerShowProgress (
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
IN CHAR16 *Title,
IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
IN UINTN Progress,
IN UINTN PreviousValue
);
#endif // _PLATFORM_BOOT_MANAGER_H

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## @file
# Include all platform action which can be customized by IBV/OEM.
#
# Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformBootManagerLib
FILE_GUID = F0D9063A-DADB-4185-85E2-D7ACDA93F7A6
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
PlatformData.c
PlatformConsole.c
PlatformConsole.h
PlatformBootManager.c
PlatformBootManager.h
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiPayloadPkg/UefiPayloadPkg.dec
[LibraryClasses]
BaseLib
UefiBootServicesTableLib
UefiRuntimeServicesTableLib
UefiLib
UefiBootManagerLib
PcdLib
DxeServicesLib
MemoryAllocationLib
DevicePathLib
HiiLib
PrintLib
PlatformHookLib
[Guids]
gEfiEndOfDxeEventGroupGuid
[Protocols]
gEfiGenericMemTestProtocolGuid ## CONSUMES
gEfiGraphicsOutputProtocolGuid ## CONSUMES
gEfiUgaDrawProtocolGuid ## CONSUMES
gEfiBootLogoProtocolGuid ## CONSUMES
gEfiDxeSmmReadyToLockProtocolGuid
gEfiSmmAccess2ProtocolGuid
[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn
gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand
gUefiPayloadPkgTokenSpaceGuid.PcdShellFile
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits

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/** @file
This file include all platform action which can be customized by IBV/OEM.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PlatformBootManager.h"
#include "PlatformConsole.h"
#define PCI_DEVICE_PATH_NODE(Func, Dev) \
{ \
{ \
HARDWARE_DEVICE_PATH, \
HW_PCI_DP, \
{ \
(UINT8) (sizeof (PCI_DEVICE_PATH)), \
(UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \
} \
}, \
(Func), \
(Dev) \
}
#define PNPID_DEVICE_PATH_NODE(PnpId) \
{ \
{ \
ACPI_DEVICE_PATH, \
ACPI_DP, \
{ \
(UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
(UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
}, \
}, \
EISA_PNP_ID((PnpId)), \
0 \
}
#define gPciRootBridge \
PNPID_DEVICE_PATH_NODE(0x0A03)
#define gPnp16550ComPort \
PNPID_DEVICE_PATH_NODE(0x0501)
#define gUartVendor \
{ \
{ \
HARDWARE_DEVICE_PATH, \
HW_VENDOR_DP, \
{ \
(UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
(UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
} \
}, \
{0xD3987D4B, 0x971A, 0x435F, {0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41}} \
}
#define gUart \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_UART_DP, \
{ \
(UINT8) (sizeof (UART_DEVICE_PATH)), \
(UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8) \
} \
}, \
0, \
115200, \
8, \
1, \
1 \
}
#define gPcAnsiTerminal \
{ \
{ \
MESSAGING_DEVICE_PATH, \
MSG_VENDOR_DP, \
{ \
(UINT8) (sizeof (VENDOR_DEVICE_PATH)), \
(UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8) \
} \
}, \
DEVICE_PATH_MESSAGING_PC_ANSI \
}
ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort;
UART_DEVICE_PATH gUartDeviceNode = gUart;
VENDOR_DEVICE_PATH gTerminalTypeDeviceNode = gPcAnsiTerminal;
VENDOR_DEVICE_PATH gUartDeviceVendorNode = gUartVendor;
//
// Predefined platform root bridge
//
PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = {
gPciRootBridge,
gEndEntire
};
EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[] = {
(EFI_DEVICE_PATH_PROTOCOL *) &gPlatformRootBridge0,
NULL
};
BOOLEAN mDetectVgaOnly;
/**
Add UART to ConOut, ConIn, ErrOut.
@param[in] DeviceHandle - LPC device path.
@retval EFI_SUCCESS - Serial console is added to ConOut, ConIn, and ErrOut.
@retval EFI_STATUS - No serial console is added.
**/
EFI_STATUS
PrepareLpcBridgeDevicePath (
IN EFI_HANDLE DeviceHandle
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
DevicePath = NULL;
Status = gBS->HandleProtocol (
DeviceHandle,
&gEfiDevicePathProtocolGuid,
(VOID*)&DevicePath
);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Register COM1
//
DevicePath = AppendDevicePathNode ((EFI_DEVICE_PATH_PROTOCOL *)NULL, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceVendorNode);
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);
EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
return EFI_SUCCESS;
}
/**
Return the GOP device path in the platform.
@param[in] PciDevicePath - Device path for the PCI graphics device.
@param[out] GopDevicePath - Return the device path with GOP installed.
@retval EFI_SUCCESS - PCI VGA is added to ConOut.
@retval EFI_INVALID_PARAMETER - The device path parameter is invalid.
@retval EFI_STATUS - No GOP device found.
**/
EFI_STATUS
GetGopDevicePath (
IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,
OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath
)
{
UINTN Index;
EFI_STATUS Status;
EFI_HANDLE PciDeviceHandle;
EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;
UINTN GopHandleCount;
EFI_HANDLE *GopHandleBuffer;
if (PciDevicePath == NULL || GopDevicePath == NULL) {
return EFI_INVALID_PARAMETER;
}
//
// Initialize the GopDevicePath to be PciDevicePath
//
*GopDevicePath = PciDevicePath;
TempPciDevicePath = PciDevicePath;
Status = gBS->LocateDevicePath (
&gEfiDevicePathProtocolGuid,
&TempPciDevicePath,
&PciDeviceHandle
);
if (EFI_ERROR (Status)) {
return Status;
}
gBS->ConnectController (PciDeviceHandle, NULL, NULL, FALSE);
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiGraphicsOutputProtocolGuid,
NULL,
&GopHandleCount,
&GopHandleBuffer
);
if (!EFI_ERROR (Status)) {
//
// Add all the child handles as possible Console Device
//
for (Index = 0; Index < GopHandleCount; Index++) {
Status = gBS->HandleProtocol (GopHandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID*)&TempDevicePath);
if (EFI_ERROR (Status)) {
continue;
}
if (CompareMem (
PciDevicePath,
TempDevicePath,
GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH
) == 0) {
//
// In current implementation, we only enable one of the child handles
// as console device, i.e. sotre one of the child handle's device
// path to variable "ConOut"
// In future, we could select all child handles to be console device
//
*GopDevicePath = TempDevicePath;
//
// Delete the PCI device's path that added by GetPlugInPciVgaDevicePath()
// Add the integrity GOP device path.
//
EfiBootManagerUpdateConsoleVariable (ConOut, NULL, PciDevicePath);
EfiBootManagerUpdateConsoleVariable (ConOut, TempDevicePath, NULL);
}
}
gBS->FreePool (GopHandleBuffer);
}
return EFI_SUCCESS;
}
/**
Add PCI VGA to ConOut, ConIn, ErrOut.
@param[in] DeviceHandle - Handle of PciIo protocol.
@retval EFI_SUCCESS - PCI VGA is added to ConOut.
@retval EFI_STATUS - No PCI VGA device is added.
**/
EFI_STATUS
PreparePciVgaDevicePath (
IN EFI_HANDLE DeviceHandle
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;
DevicePath = NULL;
Status = gBS->HandleProtocol (
DeviceHandle,
&gEfiDevicePathProtocolGuid,
(VOID*)&DevicePath
);
if (EFI_ERROR (Status)) {
return Status;
}
GetGopDevicePath (DevicePath, &GopDevicePath);
DevicePath = GopDevicePath;
EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
return EFI_SUCCESS;
}
/**
Add PCI Serial to ConOut, ConIn, ErrOut.
@param[in] DeviceHandle - Handle of PciIo protocol.
@retval EFI_SUCCESS - PCI Serial is added to ConOut, ConIn, and ErrOut.
@retval EFI_STATUS - No PCI Serial device is added.
**/
EFI_STATUS
PreparePciSerialDevicePath (
IN EFI_HANDLE DeviceHandle
)
{
EFI_STATUS Status;
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
DevicePath = NULL;
Status = gBS->HandleProtocol (
DeviceHandle,
&gEfiDevicePathProtocolGuid,
(VOID*)&DevicePath
);
if (EFI_ERROR (Status)) {
return Status;
}
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);
DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);
EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ConIn, DevicePath, NULL);
EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
return EFI_SUCCESS;
}
/**
For every PCI instance execute a callback function.
@param[in] Id - The protocol GUID for callback
@param[in] CallBackFunction - The callback function
@param[in] Context - The context of the callback
@retval EFI_STATUS - Callback function failed.
**/
EFI_STATUS
EFIAPI
VisitAllInstancesOfProtocol (
IN EFI_GUID *Id,
IN PROTOCOL_INSTANCE_CALLBACK CallBackFunction,
IN VOID *Context
)
{
EFI_STATUS Status;
UINTN HandleCount;
EFI_HANDLE *HandleBuffer;
UINTN Index;
VOID *Instance;
//
// Start to check all the PciIo to find all possible device
//
HandleCount = 0;
HandleBuffer = NULL;
Status = gBS->LocateHandleBuffer (
ByProtocol,
Id,
NULL,
&HandleCount,
&HandleBuffer
);
if (EFI_ERROR (Status)) {
return Status;
}
for (Index = 0; Index < HandleCount; Index++) {
Status = gBS->HandleProtocol (HandleBuffer[Index], Id, &Instance);
if (EFI_ERROR (Status)) {
continue;
}
Status = (*CallBackFunction) (
HandleBuffer[Index],
Instance,
Context
);
}
gBS->FreePool (HandleBuffer);
return EFI_SUCCESS;
}
/**
For every PCI instance execute a callback function.
@param[in] Handle - The PCI device handle
@param[in] Instance - The instance of the PciIo protocol
@param[in] Context - The context of the callback
@retval EFI_STATUS - Callback function failed.
**/
EFI_STATUS
EFIAPI
VisitingAPciInstance (
IN EFI_HANDLE Handle,
IN VOID *Instance,
IN VOID *Context
)
{
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
PCI_TYPE00 Pci;
PciIo = (EFI_PCI_IO_PROTOCOL*) Instance;
//
// Check for all PCI device
//
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint32,
0,
sizeof (Pci) / sizeof (UINT32),
&Pci
);
if (EFI_ERROR (Status)) {
return Status;
}
return (*(VISIT_PCI_INSTANCE_CALLBACK)(UINTN) Context) (
Handle,
PciIo,
&Pci
);
}
/**
For every PCI instance execute a callback function.
@param[in] CallBackFunction - Callback function pointer
@retval EFI_STATUS - Callback function failed.
**/
EFI_STATUS
EFIAPI
VisitAllPciInstances (
IN VISIT_PCI_INSTANCE_CALLBACK CallBackFunction
)
{
return VisitAllInstancesOfProtocol (
&gEfiPciIoProtocolGuid,
VisitingAPciInstance,
(VOID*)(UINTN) CallBackFunction
);
}
/**
Do platform specific PCI Device check and add them to
ConOut, ConIn, ErrOut.
@param[in] Handle - Handle of PCI device instance
@param[in] PciIo - PCI IO protocol instance
@param[in] Pci - PCI Header register block
@retval EFI_SUCCESS - PCI Device check and Console variable update successfully.
@retval EFI_STATUS - PCI Device check or Console variable update fail.
**/
EFI_STATUS
EFIAPI
DetectAndPreparePlatformPciDevicePath (
IN EFI_HANDLE Handle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN PCI_TYPE00 *Pci
)
{
EFI_STATUS Status;
Status = PciIo->Attributes (
PciIo,
EfiPciIoAttributeOperationEnable,
EFI_PCI_DEVICE_ENABLE,
NULL
);
ASSERT_EFI_ERROR (Status);
if (!mDetectVgaOnly) {
//
// Here we decide whether it is LPC Bridge
//
if ((IS_PCI_LPC (Pci)) ||
((IS_PCI_ISA_PDECODE (Pci)) &&
(Pci->Hdr.VendorId == 0x8086)
)
) {
//
// Add IsaKeyboard to ConIn,
// add IsaSerial to ConOut, ConIn, ErrOut
//
DEBUG ((DEBUG_INFO, "Found LPC Bridge device\n"));
PrepareLpcBridgeDevicePath (Handle);
return EFI_SUCCESS;
}
//
// Here we decide which Serial device to enable in PCI bus
//
if (IS_PCI_16550SERIAL (Pci)) {
//
// Add them to ConOut, ConIn, ErrOut.
//
DEBUG ((DEBUG_INFO, "Found PCI 16550 SERIAL device\n"));
PreparePciSerialDevicePath (Handle);
return EFI_SUCCESS;
}
}
//
// Here we decide which VGA device to enable in PCI bus
//
if (IS_PCI_VGA (Pci)) {
//
// Add them to ConOut.
//
DEBUG ((DEBUG_INFO, "Found PCI VGA device\n"));
PreparePciVgaDevicePath (Handle);
return EFI_SUCCESS;
}
return Status;
}
/**
Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut
@param[in] DetectVgaOnly - Only detect VGA device if it's TRUE.
@retval EFI_SUCCESS - PCI Device check and Console variable update successfully.
@retval EFI_STATUS - PCI Device check or Console variable update fail.
**/
EFI_STATUS
DetectAndPreparePlatformPciDevicePaths (
BOOLEAN DetectVgaOnly
)
{
mDetectVgaOnly = DetectVgaOnly;
EfiBootManagerUpdateConsoleVariable (
ConIn,
(EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath,
NULL
);
return VisitAllPciInstances (DetectAndPreparePlatformPciDevicePath);
}
/**
The function will connect root bridge
@return EFI_SUCCESS Connect RootBridge successfully.
**/
EFI_STATUS
ConnectRootBridge (
VOID
)
{
EFI_STATUS Status;
EFI_HANDLE RootHandle;
//
// Make all the PCI_IO protocols on PCI Seg 0 show up
//
Status = gBS->LocateDevicePath (
&gEfiDevicePathProtocolGuid,
&gPlatformRootBridges[0],
&RootHandle
);
if (EFI_ERROR (Status)) {
return Status;
}
Status = gBS->ConnectController (RootHandle, NULL, NULL, FALSE);
if (EFI_ERROR (Status)) {
return Status;
}
return EFI_SUCCESS;
}
/**
Platform console init. Include the platform firmware vendor, revision
and so crc check.
**/
VOID
EFIAPI
PlatformConsoleInit (
VOID
)
{
gUartDeviceNode.BaudRate = PcdGet64 (PcdUartDefaultBaudRate);
gUartDeviceNode.DataBits = PcdGet8 (PcdUartDefaultDataBits);
gUartDeviceNode.Parity = PcdGet8 (PcdUartDefaultParity);
gUartDeviceNode.StopBits = PcdGet8 (PcdUartDefaultStopBits);
ConnectRootBridge ();
//
// Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut
//
DetectAndPreparePlatformPciDevicePaths (FALSE);
}

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/** @file
Head file for BDS Platform specific code
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef _PLATFORM_CONSOLE_H
#define _PLATFORM_CONSOLE_H
#include <PiDxe.h>
#include <IndustryStandard/Pci.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiLib.h>
#include <Library/DevicePathLib.h>
#include <Protocol/PciIo.h>
#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)
#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
//
// Type definitions
//
//
// Platform Root Bridge
//
typedef struct {
ACPI_HID_DEVICE_PATH PciRootBridge;
EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
typedef
EFI_STATUS
(EFIAPI *PROTOCOL_INSTANCE_CALLBACK)(
IN EFI_HANDLE Handle,
IN VOID *Instance,
IN VOID *Context
);
/**
@param[in] Handle - Handle of PCI device instance
@param[in] PciIo - PCI IO protocol instance
@param[in] Pci - PCI Header register block
**/
typedef
EFI_STATUS
(EFIAPI *VISIT_PCI_INSTANCE_CALLBACK)(
IN EFI_HANDLE Handle,
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN PCI_TYPE00 *Pci
);
/**
Platform console init. Include the platform firmware vendor, revision
and so crc check.
**/
VOID
EFIAPI
PlatformConsoleInit (
VOID
);
#endif

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/**@file
Defined the platform specific device path which will be filled to
ConIn/ConOut variables.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "PlatformBootManager.h"
///
/// Predefined platform default console device path
///
GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
{
NULL,
0
}
};
GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {
{
{
MESSAGING_DEVICE_PATH,
MSG_USB_CLASS_DP,
{
(UINT8) (sizeof (USB_CLASS_DEVICE_PATH)),
(UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)
}
},
0xffff, // VendorId
0xffff, // ProductId
CLASS_HID, // DeviceClass
SUBCLASS_BOOT, // DeviceSubClass
PROTOCOL_KEYBOARD // DeviceProtocol
},
gEndEntire
};

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/** @file
Platform Hook Library instance for UART device.
Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Base.h>
#include <Uefi/UefiBaseType.h>
#include <Library/PciLib.h>
#include <Library/PlatformHookLib.h>
#include <Library/BlParseLib.h>
#include <Library/PcdLib.h>
typedef struct {
UINT16 VendorId; ///< Vendor ID to match the PCI device. The value 0xFFFF terminates the list of entries.
UINT16 DeviceId; ///< Device ID to match the PCI device
UINT32 ClockRate; ///< UART clock rate. Set to 0 for default clock rate of 1843200 Hz
UINT64 Offset; ///< The byte offset into to the BAR
UINT8 BarIndex; ///< Which BAR to get the UART base address
UINT8 RegisterStride; ///< UART register stride in bytes. Set to 0 for default register stride of 1 byte.
UINT16 ReceiveFifoDepth; ///< UART receive FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT16 TransmitFifoDepth; ///< UART transmit FIFO depth in bytes. Set to 0 for a default FIFO depth of 16 bytes.
UINT8 Reserved[2];
} PCI_SERIAL_PARAMETER;
/**
Performs platform specific initialization required for the CPU to access
the hardware associated with a SerialPortLib instance. This function does
not initialize the serial port hardware itself. Instead, it initializes
hardware devices that are required for the CPU to access the serial port
hardware. This function may be called more than once.
@retval RETURN_SUCCESS The platform specific initialization succeeded.
@retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
**/
RETURN_STATUS
EFIAPI
PlatformHookSerialPortInitialize (
VOID
)
{
RETURN_STATUS Status;
UINT32 DeviceVendor;
PCI_SERIAL_PARAMETER *SerialParam;
SERIAL_PORT_INFO SerialPortInfo;
Status = ParseSerialInfo (&SerialPortInfo);
if (RETURN_ERROR (Status)) {
return Status;
}
if (SerialPortInfo.Type == PLD_SERIAL_TYPE_MEMORY_MAPPED) {
Status = PcdSetBoolS (PcdSerialUseMmio, TRUE);
} else { //IO
Status = PcdSetBoolS (PcdSerialUseMmio, FALSE);
}
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet64S (PcdSerialRegisterBase, SerialPortInfo.BaseAddr);
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet32S (PcdSerialRegisterStride, SerialPortInfo.RegWidth);
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet32S (PcdSerialBaudRate, SerialPortInfo.Baud);
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo.Baud);
if (RETURN_ERROR (Status)) {
return Status;
}
Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz);
if (RETURN_ERROR (Status)) {
return Status;
}
if (SerialPortInfo.UartPciAddr >= 0x80000000) {
DeviceVendor = PciRead32 (SerialPortInfo.UartPciAddr & 0x0ffff000);
SerialParam = PcdGetPtr(PcdPciSerialParameters);
SerialParam->VendorId = (UINT16)DeviceVendor;
SerialParam->DeviceId = DeviceVendor >> 16;
SerialParam->ClockRate = SerialPortInfo.InputHertz;
SerialParam->RegisterStride = (UINT8)SerialPortInfo.RegWidth;
}
return RETURN_SUCCESS;
}

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## @file
# Platform Hook Library instance for UART device.
#
# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformHookLib
FILE_GUID = 40A2CBC6-CFB8-447b-A90E-198E88FD345E
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformHookLib
CONSTRUCTOR = PlatformHookSerialPortInitialize
[Sources]
PlatformHookLib.c
[LibraryClasses]
BlParseLib
PcdLib
PciLib
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiPayloadPkg/UefiPayloadPkg.dec
[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCES

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/** @file
Include all platform specific features which can be customized by IBV/OEM.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/UefiLib.h>
#include <Library/PlatformSupportLib.h>
/**
Parse platform specific information from coreboot.
@retval RETURN_SUCCESS The platform specific coreboot support succeeded.
@retval RETURN_DEVICE_ERROR The platform specific coreboot support could not be completed.
**/
EFI_STATUS
EFIAPI
ParsePlatformInfo (
VOID
)
{
return EFI_SUCCESS;
}

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## @file
# Include all platform specific features which can be customized by IBV/OEM.
#
# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PlatformSupportLib
FILE_GUID = B42AA265-00CA-4d4b-AC14-DBD5268E1BC7
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = PlatformSupportLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
PlatformSupportLibNull.c
[Packages]
MdePkg/MdePkg.dec
UefiPayloadPkg/UefiPayloadPkg.dec

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/** @file
Reset System Library functions for bootloader
Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Library/BaseMemoryLib.h>
#include <Guid/AcpiBoardInfoGuid.h>
ACPI_BOARD_INFO mAcpiBoardInfo;
/**
The constructor function to initialize mAcpiBoardInfo.
@retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
**/
RETURN_STATUS
EFIAPI
ResetSystemLibConstructor (
VOID
)
{
EFI_HOB_GUID_TYPE *GuidHob;
ACPI_BOARD_INFO *AcpiBoardInfoPtr;
//
// Find the acpi board information guid hob
//
GuidHob = GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);
ASSERT (GuidHob != NULL);
AcpiBoardInfoPtr = (ACPI_BOARD_INFO *)GET_GUID_HOB_DATA (GuidHob);
CopyMem (&mAcpiBoardInfo, AcpiBoardInfoPtr, sizeof (ACPI_BOARD_INFO));
return EFI_SUCCESS;
}
VOID
AcpiPmControl (
UINTN SuspendType
)
{
UINTN PmCtrlReg;
ASSERT (SuspendType <= 7);
PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;
IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (SuspendType << 10));
IoOr16 (PmCtrlReg, BIT13);
CpuDeadLoop ();
}
/**
Calling this function causes a system-wide reset. This sets
all circuitry within the system to its initial state. This type of reset
is asynchronous to system operation and operates without regard to
cycle boundaries.
System reset should not return, if it returns, it means the system does
not support cold reset.
**/
VOID
EFIAPI
ResetCold (
VOID
)
{
IoWrite8 ((UINTN)mAcpiBoardInfo.ResetRegAddress, mAcpiBoardInfo.ResetValue);
CpuDeadLoop ();
}
/**
Calling this function causes a system-wide initialization. The processors
are set to their initial state, and pending cycles are not corrupted.
System reset should not return, if it returns, it means the system does
not support warm reset.
**/
VOID
EFIAPI
ResetWarm (
VOID
)
{
IoWrite8 ((UINTN)mAcpiBoardInfo.ResetRegAddress, mAcpiBoardInfo.ResetValue);
CpuDeadLoop ();
}
/**
Calling this function causes the system to enter a power state equivalent
to the ACPI G2/S5 or G3 states.
System shutdown should not return, if it returns, it means the system does
not support shut down reset.
**/
VOID
EFIAPI
ResetShutdown (
VOID
)
{
UINTN PmCtrlReg;
//
// GPE0_EN should be disabled to avoid any GPI waking up the system from S5
//
IoWrite16 ((UINTN)mAcpiBoardInfo.PmGpeEnBase, 0);
//
// Clear Power Button Status
//
IoWrite16((UINTN) mAcpiBoardInfo.PmEvtBase, BIT8);
//
// Transform system into S5 sleep state
//
PmCtrlReg = (UINTN)mAcpiBoardInfo.PmCtrlRegBase;
IoAndThenOr16 (PmCtrlReg, (UINT16) ~0x3c00, (UINT16) (7 << 10));
IoOr16 (PmCtrlReg, BIT13);
CpuDeadLoop ();
ASSERT (FALSE);
}
/**
Calling this function causes the system to enter a power state for capsule
update.
Reset update should not return, if it returns, it means the system does
not support capsule update.
**/
VOID
EFIAPI
EnterS3WithImmediateWake (
VOID
)
{
AcpiPmControl (5);
ASSERT (FALSE);
}
/**
This function causes a systemwide reset. The exact type of the reset is
defined by the EFI_GUID that follows the Null-terminated Unicode string passed
into ResetData. If the platform does not recognize the EFI_GUID in ResetData
the platform must pick a supported reset type to perform.The platform may
optionally log the parameters from any non-normal reset that occurs.
@param[in] DataSize The size, in bytes, of ResetData.
@param[in] ResetData The data buffer starts with a Null-terminated string,
followed by the EFI_GUID.
**/
VOID
EFIAPI
ResetPlatformSpecific (
IN UINTN DataSize,
IN VOID *ResetData
)
{
ResetCold ();
}

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## @file
# Library instance for ResetSystem library class for bootloader
#
# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ResetSystemLib
FILE_GUID = C5CD4EEE-527F-47df-9C92-B41414AF7479
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ResetSystemLib
CONSTRUCTOR = ResetSystemLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
ResetSystemLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiPayloadPkg/UefiPayloadPkg.dec
[LibraryClasses]
DebugLib
IoLib
HobLib
BaseMemoryLib
[Guids]
gUefiAcpiBoardInfoGuid

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/** @file
This library will parse the Slim Bootloader to get required information.
Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include <PiDxe.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Library/BlParseLib.h>
#include <IndustryStandard/Acpi.h>
/**
This function retrieves the parameter base address from boot loader.
This function will get bootloader specific parameter address for UEFI payload.
e.g. HobList pointer for Slim Bootloader, and coreboot table header for Coreboot.
@retval NULL Failed to find the GUID HOB.
@retval others GUIDed HOB data pointer.
**/
VOID *
EFIAPI
GetParameterBase (
VOID
)
{
EFI_HOB_HANDOFF_INFO_TABLE *HandoffTable;
HandoffTable = (EFI_HOB_HANDOFF_INFO_TABLE *)(UINTN) GET_BOOTLOADER_PARAMETER ();
if ((HandoffTable->Header.HobType == EFI_HOB_TYPE_HANDOFF) &&
(HandoffTable->Header.HobLength == sizeof (EFI_HOB_HANDOFF_INFO_TABLE)) &&
(HandoffTable->Header.Reserved == 0)) {
return (VOID *)HandoffTable;
}
return NULL;
}
/**
This function retrieves a GUIDed HOB data from Slim Bootloader.
This function will search SBL HOB list to find the first GUIDed HOB that
its GUID matches Guid.
@param[in] Guid A pointer to HOB GUID to search.
@retval NULL Failed to find the GUID HOB.
@retval others GUIDed HOB data pointer.
**/
VOID *
GetGuidHobDataFromSbl (
IN EFI_GUID *Guid
)
{
UINT8 *GuidHob;
CONST VOID *HobList;
HobList = GetParameterBase ();
ASSERT (HobList != NULL);
GuidHob = GetNextGuidHob (Guid, HobList);
if (GuidHob != NULL) {
return GET_GUID_HOB_DATA (GuidHob);
}
return NULL;
}
/**
Acquire the memory map information.
@param MemInfoCallback The callback routine
@param Params Pointer to the callback routine parameter
@retval RETURN_SUCCESS Successfully find out the memory information.
@retval RETURN_NOT_FOUND Failed to find the memory information.
**/
RETURN_STATUS
EFIAPI
ParseMemoryInfo (
IN BL_MEM_INFO_CALLBACK MemInfoCallback,
IN VOID *Params
)
{
MEMROY_MAP_INFO *MemoryMapInfo;
UINTN Idx;
MemoryMapInfo = (MEMROY_MAP_INFO *) GetGuidHobDataFromSbl (&gLoaderMemoryMapInfoGuid);
if (MemoryMapInfo == NULL) {
ASSERT (FALSE);
return RETURN_NOT_FOUND;
}
for (Idx = 0; Idx < MemoryMapInfo->Count; Idx++) {
MemInfoCallback (&MemoryMapInfo->Entry[Idx], Params);
}
return RETURN_SUCCESS;
}
/**
Acquire acpi table and smbios table from slim bootloader
@param SystemTableInfo Pointer to the system table info
@retval RETURN_SUCCESS Successfully find out the tables.
@retval RETURN_NOT_FOUND Failed to find the tables.
**/
RETURN_STATUS
EFIAPI
ParseSystemTable (
OUT SYSTEM_TABLE_INFO *SystemTableInfo
)
{
SYSTEM_TABLE_INFO *TableInfo;
TableInfo = (SYSTEM_TABLE_INFO *)GetGuidHobDataFromSbl (&gUefiSystemTableInfoGuid);
if (TableInfo == NULL) {
ASSERT (FALSE);
return RETURN_NOT_FOUND;
}
CopyMem (SystemTableInfo, TableInfo, sizeof (SYSTEM_TABLE_INFO));
return RETURN_SUCCESS;
}
/**
Find the serial port information
@param SERIAL_PORT_INFO Pointer to serial port info structure
@retval RETURN_SUCCESS Successfully find the serial port information.
@retval RETURN_NOT_FOUND Failed to find the serial port information .
**/
RETURN_STATUS
EFIAPI
ParseSerialInfo (
OUT SERIAL_PORT_INFO *SerialPortInfo
)
{
SERIAL_PORT_INFO *BlSerialInfo;
BlSerialInfo = (SERIAL_PORT_INFO *) GetGuidHobDataFromSbl (&gUefiSerialPortInfoGuid);
if (BlSerialInfo == NULL) {
ASSERT (FALSE);
return RETURN_NOT_FOUND;
}
CopyMem (SerialPortInfo, BlSerialInfo, sizeof (SERIAL_PORT_INFO));
return RETURN_SUCCESS;
}
/**
Find the video frame buffer information
@param GfxInfo Pointer to the EFI_PEI_GRAPHICS_INFO_HOB structure
@retval RETURN_SUCCESS Successfully find the video frame buffer information.
@retval RETURN_NOT_FOUND Failed to find the video frame buffer information .
**/
RETURN_STATUS
EFIAPI
ParseGfxInfo (
OUT EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo
)
{
EFI_PEI_GRAPHICS_INFO_HOB *BlGfxInfo;
BlGfxInfo = (EFI_PEI_GRAPHICS_INFO_HOB *) GetGuidHobDataFromSbl (&gEfiGraphicsInfoHobGuid);
if (BlGfxInfo == NULL) {
return RETURN_NOT_FOUND;
}
CopyMem (GfxInfo, BlGfxInfo, sizeof (EFI_PEI_GRAPHICS_INFO_HOB));
return RETURN_SUCCESS;
}
/**
Find the video frame buffer device information
@param GfxDeviceInfo Pointer to the EFI_PEI_GRAPHICS_DEVICE_INFO_HOB structure
@retval RETURN_SUCCESS Successfully find the video frame buffer information.
@retval RETURN_NOT_FOUND Failed to find the video frame buffer information.
**/
RETURN_STATUS
EFIAPI
ParseGfxDeviceInfo (
OUT EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *GfxDeviceInfo
)
{
EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *BlGfxDeviceInfo;
BlGfxDeviceInfo = (EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *) GetGuidHobDataFromSbl (&gEfiGraphicsDeviceInfoHobGuid);
if (BlGfxDeviceInfo == NULL) {
return RETURN_NOT_FOUND;
}
CopyMem (GfxDeviceInfo, BlGfxDeviceInfo, sizeof (EFI_PEI_GRAPHICS_DEVICE_INFO_HOB));
return RETURN_SUCCESS;
}

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@@ -0,0 +1,46 @@
## @file
# Slim Bootloader parse library.
#
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = SblParseLib
FILE_GUID = DE6FB32C-52CF-4A17-A84C-B323653CB5E0
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = BlParseLib
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
SblParseLib.c
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiPayloadPkg/UefiPayloadPkg.dec
[LibraryClasses]
BaseLib
BaseMemoryLib
DebugLib
PcdLib
HobLib
[Guids]
gUefiSystemTableInfoGuid
gUefiSerialPortInfoGuid
gLoaderMemoryMapInfoGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
[Pcd]
gUefiPayloadPkgTokenSpaceGuid.PcdPayloadStackTop