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UefiCpuPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiCpuPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:17 -08:00
committed by mergify[bot]
parent 91415a36ae
commit 053e878bfb
143 changed files with 14130 additions and 13035 deletions
Download Patch File Download Diff File Expand all files Collapse all files

284
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
View File

@@ -44,13 +44,14 @@ LocalApicBaseAddressMsrSupported (
AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) {
if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
//
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR
//
return FALSE;
}
return TRUE;
}
@@ -78,8 +79,8 @@ GetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
}
/**
@@ -93,7 +94,7 @@ GetLocalApicBaseAddress (
VOID
EFIAPI
SetLocalApicBaseAddress (
IN UINTN BaseAddress
IN UINTN BaseAddress
)
{
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
@@ -109,8 +110,8 @@ SetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
}
@@ -137,7 +138,7 @@ ReadLocalApicReg (
ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
}
/**
@@ -157,14 +158,14 @@ ReadLocalApicReg (
VOID
EFIAPI
WriteLocalApicReg (
IN UINTN MmioOffset,
IN UINT32 Value
IN UINTN MmioOffset,
IN UINT32 Value
)
{
ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
}
/**
@@ -177,13 +178,13 @@ WriteLocalApicReg (
**/
VOID
SendIpi (
IN UINT32 IcrLow,
IN UINT32 ApicId
IN UINT32 IcrLow,
IN UINT32 ApicId
)
{
LOCAL_APIC_ICR_LOW IcrLowReg;
UINT32 IcrHigh;
BOOLEAN InterruptState;
LOCAL_APIC_ICR_LOW IcrLowReg;
UINT32 IcrHigh;
BOOLEAN InterruptState;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
ASSERT (ApicId <= 0xff);
@@ -222,7 +223,6 @@ SendIpi (
WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState);
}
//
@@ -244,21 +244,21 @@ GetApicMode (
)
{
DEBUG_CODE_BEGIN ();
{
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
{
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
//
// Check to see if the CPU supports the APIC Base Address MSR
//
if (LocalApicBaseAddressMsrSupported ()) {
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
//
// Check to see if the CPU supports the APIC Base Address MSR
// Local APIC should have been enabled
//
if (LocalApicBaseAddressMsrSupported ()) {
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
//
// Local APIC should have been enabled
//
ASSERT (ApicBaseMsr.Bits.EN != 0);
ASSERT (ApicBaseMsr.Bits.EXTD == 0);
}
ASSERT (ApicBaseMsr.Bits.EN != 0);
ASSERT (ApicBaseMsr.Bits.EXTD == 0);
}
}
DEBUG_CODE_END ();
return LOCAL_APIC_MODE_XAPIC;
}
@@ -299,9 +299,9 @@ GetInitialApicId (
VOID
)
{
UINT32 ApicId;
UINT32 MaxCpuIdIndex;
UINT32 RegEbx;
UINT32 ApicId;
UINT32 MaxCpuIdIndex;
UINT32 RegEbx;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
@@ -338,7 +338,7 @@ GetApicId (
VOID
)
{
UINT32 ApicId;
UINT32 ApicId;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
@@ -347,9 +347,10 @@ GetApicId (
// If the initial local APIC ID is less 0x100, read APIC ID from
// XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
//
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
ApicId >>= 24;
}
return ApicId;
}
@@ -378,16 +379,16 @@ GetApicVersion (
VOID
EFIAPI
SendFixedIpi (
IN UINT32 ApicId,
IN UINT8 Vector
IN UINT32 ApicId,
IN UINT8 Vector
)
{
LOCAL_APIC_ICR_LOW IcrLow;
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1;
IcrLow.Bits.Vector = Vector;
IcrLow.Bits.Level = 1;
IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -401,16 +402,16 @@ SendFixedIpi (
VOID
EFIAPI
SendFixedIpiAllExcludingSelf (
IN UINT8 Vector
IN UINT8 Vector
)
{
LOCAL_APIC_ICR_LOW IcrLow;
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
IcrLow.Bits.Vector = Vector;
IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, 0);
}
@@ -424,14 +425,14 @@ SendFixedIpiAllExcludingSelf (
VOID
EFIAPI
SendSmiIpi (
IN UINT32 ApicId
IN UINT32 ApicId
)
{
LOCAL_APIC_ICR_LOW IcrLow;
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1;
IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -446,11 +447,11 @@ SendSmiIpiAllExcludingSelf (
VOID
)
{
LOCAL_APIC_ICR_LOW IcrLow;
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
}
@@ -465,14 +466,14 @@ SendSmiIpiAllExcludingSelf (
VOID
EFIAPI
SendInitIpi (
IN UINT32 ApicId
IN UINT32 ApicId
)
{
LOCAL_APIC_ICR_LOW IcrLow;
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1;
IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
}
@@ -487,11 +488,11 @@ SendInitIpiAllExcludingSelf (
VOID
)
{
LOCAL_APIC_ICR_LOW IcrLow;
LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1;
IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
}
@@ -511,21 +512,21 @@ SendInitIpiAllExcludingSelf (
VOID
EFIAPI
SendInitSipiSipi (
IN UINT32 ApicId,
IN UINT32 StartupRoutine
IN UINT32 ApicId,
IN UINT32 StartupRoutine
)
{
LOCAL_APIC_ICR_LOW IcrLow;
LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId);
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12);
MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1;
IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId);
if (!StandardSignatureIsAuthenticAMD ()) {
MicroSecondDelay (200);
@@ -547,20 +548,20 @@ SendInitSipiSipi (
VOID
EFIAPI
SendInitSipiSipiAllExcludingSelf (
IN UINT32 StartupRoutine
IN UINT32 StartupRoutine
)
{
LOCAL_APIC_ICR_LOW IcrLow;
LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf ();
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1;
MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0);
if (!StandardSignatureIsAuthenticAMD ()) {
@@ -616,13 +617,13 @@ ProgramVirtualWireMode (
VOID
)
{
LOCAL_APIC_SVR Svr;
LOCAL_APIC_LVT_LINT Lint;
LOCAL_APIC_SVR Svr;
LOCAL_APIC_LVT_LINT Lint;
//
// Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
//
Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
Svr.Bits.SpuriousVector = 0xf;
Svr.Bits.SoftwareEnable = 1;
WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
@@ -630,21 +631,21 @@ ProgramVirtualWireMode (
//
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
//
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0;
Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
//
// Program the LINT0 vector entry as NMI. Not masked, edge, active high.
//
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0;
Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
}
@@ -659,13 +660,13 @@ DisableLvtInterrupts (
VOID
)
{
LOCAL_APIC_LVT_LINT LvtLint;
LOCAL_APIC_LVT_LINT LvtLint;
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
}
@@ -712,15 +713,15 @@ GetApicTimerCurrentCount (
VOID
EFIAPI
InitializeApicTimer (
IN UINTN DivideValue,
IN UINT32 InitCount,
IN BOOLEAN PeriodicMode,
IN UINT8 Vector
IN UINTN DivideValue,
IN UINT32 InitCount,
IN BOOLEAN PeriodicMode,
IN UINT8 Vector
)
{
LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer;
UINT32 Divisor;
LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer;
UINT32 Divisor;
//
// Ensure local APIC is in software-enabled state.
@@ -734,10 +735,10 @@ InitializeApicTimer (
if (DivideValue != 0) {
ASSERT (DivideValue <= 128);
ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Bits.DivideValue1 = (Divisor & 0x3);
Dcr.Bits.DivideValue2 = (Divisor >> 2);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
@@ -752,7 +753,8 @@ InitializeApicTimer (
} else {
LvtTimer.Bits.TimerMode = 0;
}
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -774,25 +776,25 @@ GetApicTimerState (
OUT UINT8 *Vector OPTIONAL
)
{
UINT32 Divisor;
LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer;
UINT32 Divisor;
LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer;
//
// Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
// Vector Register.
// This bit will be 1, if local APIC is software enabled.
//
ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
if (DivideValue != NULL) {
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
Divisor = (Divisor + 1) & 0x7;
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
Divisor = (Divisor + 1) & 0x7;
*DivideValue = ((UINTN)1) << Divisor;
}
if (PeriodicMode != NULL || Vector != NULL) {
if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) {
@@ -801,8 +803,9 @@ GetApicTimerState (
*PeriodicMode = FALSE;
}
}
if (Vector != NULL) {
*Vector = (UINT8) LvtTimer.Bits.Vector;
*Vector = (UINT8)LvtTimer.Bits.Vector;
}
}
}
@@ -816,9 +819,9 @@ EnableApicTimerInterrupt (
VOID
)
{
LOCAL_APIC_LVT_TIMER LvtTimer;
LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -832,9 +835,9 @@ DisableApicTimerInterrupt (
VOID
)
{
LOCAL_APIC_LVT_TIMER LvtTimer;
LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
}
@@ -851,7 +854,7 @@ GetApicTimerInterruptState (
VOID
)
{
LOCAL_APIC_LVT_TIMER LvtTimer;
LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
@@ -944,6 +947,7 @@ GetApicMsiValue (
MsiData.Bits.Level = 1;
}
}
return MsiData.Uint64;
}
@@ -995,12 +999,15 @@ GetProcessorLocationByApicId (
if (Thread != NULL) {
*Thread = 0;
}
if (Core != NULL) {
*Core = 0;
}
if (Package != NULL) {
*Package = 0;
}
return;
}
@@ -1008,7 +1015,7 @@ GetProcessorLocationByApicId (
// Assume three-level mapping of APIC ID: Package|Core|Thread.
//
ThreadBits = 0;
CoreBits = 0;
CoreBits = 0;
//
// Get max index of CPUID
@@ -1022,7 +1029,7 @@ GetProcessorLocationByApicId (
//
TopologyLeafSupported = FALSE;
if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
AsmCpuidEx (
CPUID_EXTENDED_TOPOLOGY,
0,
&ExtendedTopologyEax.Uint32,
@@ -1065,6 +1072,7 @@ GetProcessorLocationByApicId (
CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break;
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
}
@@ -1085,7 +1093,7 @@ GetProcessorLocationByApicId (
//
// Check for topology extensions on AMD processor
//
if (StandardSignatureIsAuthenticAMD()) {
if (StandardSignatureIsAuthenticAMD ()) {
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
@@ -1102,8 +1110,7 @@ GetProcessorLocationByApicId (
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
}
}
}
else {
} else {
//
// Extract core count based on CACHE information
//
@@ -1115,16 +1122,18 @@ GetProcessorLocationByApicId (
}
}
ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
}
if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
}
@@ -1158,13 +1167,13 @@ GetProcessorLocation2ByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
UINT32 MaxStandardCpuIdIndex;
UINT32 Index;
UINTN LevelType;
UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
UINT32 MaxStandardCpuIdIndex;
UINT32 Index;
UINTN LevelType;
UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
Bits[LevelType] = 0;
@@ -1178,12 +1187,15 @@ GetProcessorLocation2ByApicId (
if (Die != NULL) {
*Die = 0;
}
if (Tile != NULL) {
*Tile = 0;
}
if (Module != NULL) {
*Module = 0;
}
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return;
}
@@ -1193,7 +1205,7 @@ GetProcessorLocation2ByApicId (
// is the preferred mechanism for enumerating topology.
//
for (Index = 0; ; Index++) {
AsmCpuidEx(
AsmCpuidEx (
CPUID_V2_EXTENDED_TOPOLOGY,
Index,
&ExtendedTopologyEax.Uint32,
@@ -1211,6 +1223,7 @@ GetProcessorLocation2ByApicId (
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break;
}
ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
}
@@ -1226,18 +1239,19 @@ GetProcessorLocation2ByApicId (
}
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
; LevelType ++
) {
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
; LevelType++
)
{
if (Location[LevelType] != NULL) {
//
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique