UefiCpuPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
committed by
mergify[bot]
mergify[bot]
parent
91415a36ae
commit
053e878bfb
@@ -45,13 +45,14 @@ LocalApicBaseAddressMsrSupported (
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AsmCpuid (1, &RegEax, NULL, NULL, NULL);
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FamilyId = BitFieldRead32 (RegEax, 8, 11);
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if (FamilyId == 0x04 || FamilyId == 0x05) {
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if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
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//
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// CPUs with a FamilyId of 0x04 or 0x05 do not support the
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// Local APIC Base Address MSR
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//
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return FALSE;
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}
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return TRUE;
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}
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@@ -79,8 +80,8 @@ GetLocalApicBaseAddress (
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
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(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
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return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
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(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
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}
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/**
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@@ -94,7 +95,7 @@ GetLocalApicBaseAddress (
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VOID
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EFIAPI
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SetLocalApicBaseAddress (
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IN UINTN BaseAddress
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IN UINTN BaseAddress
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)
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{
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MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
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@@ -110,8 +111,8 @@ SetLocalApicBaseAddress (
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12);
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ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
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ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
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ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
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AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
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}
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@@ -135,12 +136,12 @@ ReadLocalApicReg (
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IN UINTN MmioOffset
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)
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{
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UINT32 MsrIndex;
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UINT32 MsrIndex;
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ASSERT ((MmioOffset & 0xf) == 0);
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if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
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return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);
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return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
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} else {
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//
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// DFR is not supported in x2APIC mode.
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@@ -174,16 +175,16 @@ ReadLocalApicReg (
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VOID
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EFIAPI
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WriteLocalApicReg (
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IN UINTN MmioOffset,
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IN UINT32 Value
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IN UINTN MmioOffset,
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IN UINT32 Value
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)
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{
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UINT32 MsrIndex;
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UINT32 MsrIndex;
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ASSERT ((MmioOffset & 0xf) == 0);
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if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
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MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);
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MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
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} else {
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//
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// DFR is not supported in x2APIC mode.
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@@ -216,15 +217,15 @@ WriteLocalApicReg (
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**/
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VOID
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SendIpi (
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IN UINT32 IcrLow,
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IN UINT32 ApicId
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IN UINT32 IcrLow,
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IN UINT32 ApicId
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)
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{
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UINT64 MsrValue;
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LOCAL_APIC_ICR_LOW IcrLowReg;
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UINTN LocalApciBaseAddress;
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UINT32 IcrHigh;
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BOOLEAN InterruptState;
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UINT64 MsrValue;
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LOCAL_APIC_ICR_LOW IcrLowReg;
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UINTN LocalApciBaseAddress;
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UINT32 IcrHigh;
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BOOLEAN InterruptState;
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//
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// Legacy APIC or X2APIC?
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@@ -237,7 +238,7 @@ SendIpi (
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//
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// Get base address of this LAPIC
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//
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LocalApciBaseAddress = GetLocalApicBaseAddress();
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LocalApciBaseAddress = GetLocalApicBaseAddress ();
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//
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// Save existing contents of ICR high 32 bits
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@@ -271,13 +272,12 @@ SendIpi (
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MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
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SetInterruptState (InterruptState);
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} else {
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//
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// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
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// interrupt in x2APIC mode.
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//
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MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;
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MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow;
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AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
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}
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}
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@@ -354,7 +354,7 @@ SetApicMode (
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case LOCAL_APIC_MODE_XAPIC:
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break;
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case LOCAL_APIC_MODE_X2APIC:
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBaseMsr.Bits.EXTD = 1;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
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break;
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@@ -368,9 +368,9 @@ SetApicMode (
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// Transition from x2APIC mode to xAPIC mode is a two-step process:
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// x2APIC -> Local APIC disabled -> xAPIC
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//
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
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ApicBaseMsr.Bits.EXTD = 0;
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ApicBaseMsr.Bits.EN = 0;
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ApicBaseMsr.Bits.EN = 0;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
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ApicBaseMsr.Bits.EN = 1;
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AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
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@@ -398,9 +398,9 @@ GetInitialApicId (
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VOID
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)
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{
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UINT32 ApicId;
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UINT32 MaxCpuIdIndex;
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UINT32 RegEbx;
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UINT32 ApicId;
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UINT32 MaxCpuIdIndex;
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UINT32 RegEbx;
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if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
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//
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@@ -419,6 +419,7 @@ GetInitialApicId (
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return ApicId;
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}
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}
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AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
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return RegEbx >> 24;
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} else {
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@@ -437,8 +438,8 @@ GetApicId (
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VOID
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)
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{
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UINT32 ApicId;
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UINT32 InitApicId;
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UINT32 ApicId;
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UINT32 InitApicId;
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ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
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if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
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@@ -473,16 +474,16 @@ GetApicVersion (
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VOID
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EFIAPI
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SendFixedIpi (
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IN UINT32 ApicId,
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IN UINT8 Vector
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IN UINT32 ApicId,
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IN UINT8 Vector
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)
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{
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LOCAL_APIC_ICR_LOW IcrLow;
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LOCAL_APIC_ICR_LOW IcrLow;
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IcrLow.Uint32 = 0;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.Vector = Vector;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.Vector = Vector;
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SendIpi (IcrLow.Uint32, ApicId);
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}
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@@ -496,16 +497,16 @@ SendFixedIpi (
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VOID
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EFIAPI
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SendFixedIpiAllExcludingSelf (
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IN UINT8 Vector
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IN UINT8 Vector
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)
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{
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LOCAL_APIC_ICR_LOW IcrLow;
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LOCAL_APIC_ICR_LOW IcrLow;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
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IcrLow.Bits.Level = 1;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
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IcrLow.Bits.Vector = Vector;
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IcrLow.Bits.Vector = Vector;
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SendIpi (IcrLow.Uint32, 0);
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}
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@@ -519,14 +520,14 @@ SendFixedIpiAllExcludingSelf (
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VOID
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EFIAPI
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SendSmiIpi (
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IN UINT32 ApicId
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IN UINT32 ApicId
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)
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{
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LOCAL_APIC_ICR_LOW IcrLow;
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LOCAL_APIC_ICR_LOW IcrLow;
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IcrLow.Uint32 = 0;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.Level = 1;
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SendIpi (IcrLow.Uint32, ApicId);
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}
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@@ -541,11 +542,11 @@ SendSmiIpiAllExcludingSelf (
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VOID
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)
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{
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LOCAL_APIC_ICR_LOW IcrLow;
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LOCAL_APIC_ICR_LOW IcrLow;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
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IcrLow.Bits.Level = 1;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
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SendIpi (IcrLow.Uint32, 0);
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}
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@@ -560,14 +561,14 @@ SendSmiIpiAllExcludingSelf (
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VOID
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EFIAPI
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SendInitIpi (
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IN UINT32 ApicId
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IN UINT32 ApicId
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)
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{
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LOCAL_APIC_ICR_LOW IcrLow;
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LOCAL_APIC_ICR_LOW IcrLow;
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IcrLow.Uint32 = 0;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.Level = 1;
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SendIpi (IcrLow.Uint32, ApicId);
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}
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@@ -582,11 +583,11 @@ SendInitIpiAllExcludingSelf (
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VOID
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)
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{
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LOCAL_APIC_ICR_LOW IcrLow;
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LOCAL_APIC_ICR_LOW IcrLow;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
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IcrLow.Bits.Level = 1;
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IcrLow.Uint32 = 0;
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
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SendIpi (IcrLow.Uint32, 0);
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}
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@@ -606,21 +607,21 @@ SendInitIpiAllExcludingSelf (
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VOID
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EFIAPI
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SendInitSipiSipi (
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IN UINT32 ApicId,
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IN UINT32 StartupRoutine
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IN UINT32 ApicId,
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IN UINT32 StartupRoutine
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)
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{
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LOCAL_APIC_ICR_LOW IcrLow;
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LOCAL_APIC_ICR_LOW IcrLow;
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ASSERT (StartupRoutine < 0x100000);
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ASSERT ((StartupRoutine & 0xfff) == 0);
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SendInitIpi (ApicId);
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MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
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IcrLow.Uint32 = 0;
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IcrLow.Bits.Vector = (StartupRoutine >> 12);
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MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
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IcrLow.Uint32 = 0;
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IcrLow.Bits.Vector = (StartupRoutine >> 12);
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.Level = 1;
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SendIpi (IcrLow.Uint32, ApicId);
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if (!StandardSignatureIsAuthenticAMD ()) {
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MicroSecondDelay (200);
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@@ -642,20 +643,20 @@ SendInitSipiSipi (
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VOID
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EFIAPI
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SendInitSipiSipiAllExcludingSelf (
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IN UINT32 StartupRoutine
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IN UINT32 StartupRoutine
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)
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{
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LOCAL_APIC_ICR_LOW IcrLow;
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LOCAL_APIC_ICR_LOW IcrLow;
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ASSERT (StartupRoutine < 0x100000);
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ASSERT ((StartupRoutine & 0xfff) == 0);
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SendInitIpiAllExcludingSelf ();
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MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));
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IcrLow.Uint32 = 0;
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IcrLow.Bits.Vector = (StartupRoutine >> 12);
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
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IcrLow.Bits.Level = 1;
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MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
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IcrLow.Uint32 = 0;
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IcrLow.Bits.Vector = (StartupRoutine >> 12);
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IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
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IcrLow.Bits.Level = 1;
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IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
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SendIpi (IcrLow.Uint32, 0);
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if (!StandardSignatureIsAuthenticAMD ()) {
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@@ -711,13 +712,13 @@ ProgramVirtualWireMode (
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VOID
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)
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{
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LOCAL_APIC_SVR Svr;
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LOCAL_APIC_LVT_LINT Lint;
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LOCAL_APIC_SVR Svr;
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LOCAL_APIC_LVT_LINT Lint;
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//
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// Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
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//
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Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
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Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
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Svr.Bits.SpuriousVector = 0xf;
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Svr.Bits.SoftwareEnable = 1;
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WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
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@@ -725,21 +726,21 @@ ProgramVirtualWireMode (
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//
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// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
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//
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Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
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Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
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Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
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Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
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Lint.Bits.InputPinPolarity = 0;
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Lint.Bits.TriggerMode = 0;
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Lint.Bits.Mask = 0;
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Lint.Bits.TriggerMode = 0;
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Lint.Bits.Mask = 0;
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WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
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//
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// Program the LINT0 vector entry as NMI. Not masked, edge, active high.
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//
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Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
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Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
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Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
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Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
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Lint.Bits.InputPinPolarity = 0;
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Lint.Bits.TriggerMode = 0;
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Lint.Bits.Mask = 0;
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Lint.Bits.TriggerMode = 0;
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Lint.Bits.Mask = 0;
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WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
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}
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@@ -754,13 +755,13 @@ DisableLvtInterrupts (
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VOID
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)
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{
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LOCAL_APIC_LVT_LINT LvtLint;
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LOCAL_APIC_LVT_LINT LvtLint;
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LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
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LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
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LvtLint.Bits.Mask = 1;
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WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
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LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
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LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
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LvtLint.Bits.Mask = 1;
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WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
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}
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@@ -807,15 +808,15 @@ GetApicTimerCurrentCount (
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VOID
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EFIAPI
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InitializeApicTimer (
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IN UINTN DivideValue,
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IN UINT32 InitCount,
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IN BOOLEAN PeriodicMode,
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IN UINT8 Vector
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IN UINTN DivideValue,
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IN UINT32 InitCount,
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IN BOOLEAN PeriodicMode,
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IN UINT8 Vector
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)
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{
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LOCAL_APIC_DCR Dcr;
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LOCAL_APIC_LVT_TIMER LvtTimer;
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UINT32 Divisor;
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LOCAL_APIC_DCR Dcr;
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LOCAL_APIC_LVT_TIMER LvtTimer;
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UINT32 Divisor;
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//
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// Ensure local APIC is in software-enabled state.
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@@ -829,10 +830,10 @@ InitializeApicTimer (
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if (DivideValue != 0) {
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ASSERT (DivideValue <= 128);
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ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));
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ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
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Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
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Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
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Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
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Dcr.Bits.DivideValue1 = (Divisor & 0x3);
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Dcr.Bits.DivideValue2 = (Divisor >> 2);
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WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
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@@ -847,7 +848,8 @@ InitializeApicTimer (
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} else {
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LvtTimer.Bits.TimerMode = 0;
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}
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LvtTimer.Bits.Mask = 0;
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LvtTimer.Bits.Mask = 0;
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LvtTimer.Bits.Vector = Vector;
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WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
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}
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@@ -869,25 +871,25 @@ GetApicTimerState (
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OUT UINT8 *Vector OPTIONAL
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)
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{
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UINT32 Divisor;
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LOCAL_APIC_DCR Dcr;
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LOCAL_APIC_LVT_TIMER LvtTimer;
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UINT32 Divisor;
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LOCAL_APIC_DCR Dcr;
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LOCAL_APIC_LVT_TIMER LvtTimer;
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//
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// Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
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// Vector Register.
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// This bit will be 1, if local APIC is software enabled.
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//
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ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
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ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
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if (DivideValue != NULL) {
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Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
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Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
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Divisor = (Divisor + 1) & 0x7;
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Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
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Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
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Divisor = (Divisor + 1) & 0x7;
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*DivideValue = ((UINTN)1) << Divisor;
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}
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if (PeriodicMode != NULL || Vector != NULL) {
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if ((PeriodicMode != NULL) || (Vector != NULL)) {
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LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
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if (PeriodicMode != NULL) {
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if (LvtTimer.Bits.TimerMode == 1) {
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@@ -896,8 +898,9 @@ GetApicTimerState (
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*PeriodicMode = FALSE;
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}
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}
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if (Vector != NULL) {
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*Vector = (UINT8) LvtTimer.Bits.Vector;
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*Vector = (UINT8)LvtTimer.Bits.Vector;
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}
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}
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}
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@@ -911,9 +914,9 @@ EnableApicTimerInterrupt (
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VOID
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)
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{
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LOCAL_APIC_LVT_TIMER LvtTimer;
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LOCAL_APIC_LVT_TIMER LvtTimer;
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LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
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LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
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LvtTimer.Bits.Mask = 0;
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WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
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}
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@@ -927,9 +930,9 @@ DisableApicTimerInterrupt (
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VOID
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)
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{
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LOCAL_APIC_LVT_TIMER LvtTimer;
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LOCAL_APIC_LVT_TIMER LvtTimer;
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LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
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LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
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LvtTimer.Bits.Mask = 1;
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WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
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}
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@@ -946,7 +949,7 @@ GetApicTimerInterruptState (
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VOID
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)
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{
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LOCAL_APIC_LVT_TIMER LvtTimer;
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LOCAL_APIC_LVT_TIMER LvtTimer;
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LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
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return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
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@@ -1039,6 +1042,7 @@ GetApicMsiValue (
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MsiData.Bits.Level = 1;
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}
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}
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return MsiData.Uint64;
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}
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@@ -1090,12 +1094,15 @@ GetProcessorLocationByApicId (
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if (Thread != NULL) {
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*Thread = 0;
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}
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if (Core != NULL) {
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*Core = 0;
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}
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if (Package != NULL) {
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*Package = 0;
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}
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return;
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}
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@@ -1103,7 +1110,7 @@ GetProcessorLocationByApicId (
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// Assume three-level mapping of APIC ID: Package|Core|Thread.
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//
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ThreadBits = 0;
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CoreBits = 0;
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CoreBits = 0;
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//
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// Get max index of CPUID
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@@ -1117,7 +1124,7 @@ GetProcessorLocationByApicId (
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//
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TopologyLeafSupported = FALSE;
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if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
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AsmCpuidEx(
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AsmCpuidEx (
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CPUID_EXTENDED_TOPOLOGY,
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0,
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&ExtendedTopologyEax.Uint32,
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@@ -1160,6 +1167,7 @@ GetProcessorLocationByApicId (
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CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
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break;
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}
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SubIndex++;
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} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
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}
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@@ -1180,7 +1188,7 @@ GetProcessorLocationByApicId (
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//
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// Check for topology extensions on AMD processor
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||||
//
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if (StandardSignatureIsAuthenticAMD()) {
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if (StandardSignatureIsAuthenticAMD ()) {
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if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
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AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
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if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
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@@ -1197,8 +1205,7 @@ GetProcessorLocationByApicId (
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MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
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}
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}
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}
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else {
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} else {
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//
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// Extract core count based on CACHE information
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||||
//
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@@ -1210,16 +1217,18 @@ GetProcessorLocationByApicId (
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||||
}
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}
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ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
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CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
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ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
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CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
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}
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if (Thread != NULL) {
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*Thread = InitialApicId & ((1 << ThreadBits) - 1);
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}
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if (Core != NULL) {
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*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
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}
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if (Package != NULL) {
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*Package = (InitialApicId >> (ThreadBits + CoreBits));
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}
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@@ -1253,13 +1262,13 @@ GetProcessorLocation2ByApicId (
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||||
OUT UINT32 *Thread OPTIONAL
|
||||
)
|
||||
{
|
||||
CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
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||||
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
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UINT32 MaxStandardCpuIdIndex;
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UINT32 Index;
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||||
UINTN LevelType;
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UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
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UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
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CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
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||||
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
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||||
UINT32 MaxStandardCpuIdIndex;
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||||
UINT32 Index;
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||||
UINTN LevelType;
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UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
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||||
UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
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||||
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||||
for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
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||||
Bits[LevelType] = 0;
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@@ -1273,12 +1282,15 @@ GetProcessorLocation2ByApicId (
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||||
if (Die != NULL) {
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||||
*Die = 0;
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||||
}
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||||
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||||
if (Tile != NULL) {
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||||
*Tile = 0;
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||||
}
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||||
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||||
if (Module != NULL) {
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||||
*Module = 0;
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||||
}
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||||
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||||
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
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||||
return;
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||||
}
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||||
@@ -1288,7 +1300,7 @@ GetProcessorLocation2ByApicId (
|
||||
// is the preferred mechanism for enumerating topology.
|
||||
//
|
||||
for (Index = 0; ; Index++) {
|
||||
AsmCpuidEx(
|
||||
AsmCpuidEx (
|
||||
CPUID_V2_EXTENDED_TOPOLOGY,
|
||||
Index,
|
||||
&ExtendedTopologyEax.Uint32,
|
||||
@@ -1306,6 +1318,7 @@ GetProcessorLocation2ByApicId (
|
||||
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
|
||||
break;
|
||||
}
|
||||
|
||||
ASSERT (LevelType < ARRAY_SIZE (Bits));
|
||||
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
|
||||
}
|
||||
@@ -1321,18 +1334,19 @@ GetProcessorLocation2ByApicId (
|
||||
}
|
||||
|
||||
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
|
||||
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die;
|
||||
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile;
|
||||
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;
|
||||
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core;
|
||||
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread;
|
||||
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
|
||||
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
|
||||
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
|
||||
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
|
||||
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
|
||||
|
||||
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
|
||||
|
||||
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
|
||||
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
|
||||
; LevelType ++
|
||||
) {
|
||||
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
|
||||
; LevelType++
|
||||
)
|
||||
{
|
||||
if (Location[LevelType] != NULL) {
|
||||
//
|
||||
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique
|
||||
|
||||
Reference in New Issue
Block a user