UefiCpuPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
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@ -20,10 +20,10 @@
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VOID *
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EFIAPI
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PpinGetConfigData (
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IN UINTN NumberOfProcessors
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IN UINTN NumberOfProcessors
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)
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{
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VOID *ConfigData;
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VOID *ConfigData;
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ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);
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ASSERT (ConfigData != NULL);
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@ -55,8 +55,8 @@ PpinSupport (
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IN VOID *ConfigData OPTIONAL
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)
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{
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MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
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MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
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MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
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MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
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if ((CpuInfo->DisplayFamily == 0x06) &&
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((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
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@ -65,13 +65,14 @@ PpinSupport (
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(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
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(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
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(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
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)) {
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))
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{
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//
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// Check whether platform support this feature.
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//
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PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
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if (PlatformInfo.Bits.PPIN_CAP != 0) {
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MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;
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MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
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ASSERT (MsrPpinCtrl != NULL);
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MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
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return TRUE;
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@ -112,9 +113,9 @@ PpinInitialize (
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IN BOOLEAN State
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)
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{
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MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
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MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
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MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;
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MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
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ASSERT (MsrPpinCtrl != NULL);
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//
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@ -143,14 +144,14 @@ PpinInitialize (
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// According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.
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//
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MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;
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MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;
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MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;
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} else {
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//
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// Disable and Lock.
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// According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.
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//
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MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;
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MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;
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MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;
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}
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CPU_REGISTER_TABLE_WRITE64 (
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