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UefiCpuPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiCpuPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:17 -08:00
committed by mergify[bot]
parent 91415a36ae
commit 053e878bfb
143 changed files with 14130 additions and 13035 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
View File

@@ -20,10 +20,10 @@
VOID *
EFIAPI
PpinGetConfigData (
IN UINTN NumberOfProcessors
IN UINTN NumberOfProcessors
)
{
VOID *ConfigData;
VOID *ConfigData;
ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);
ASSERT (ConfigData != NULL);
@@ -55,8 +55,8 @@ PpinSupport (
IN VOID *ConfigData OPTIONAL
)
{
MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
if ((CpuInfo->DisplayFamily == 0x06) &&
((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
@@ -65,13 +65,14 @@ PpinSupport (
(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
)) {
))
{
//
// Check whether platform support this feature.
//
PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
if (PlatformInfo.Bits.PPIN_CAP != 0) {
MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;
MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
ASSERT (MsrPpinCtrl != NULL);
MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
return TRUE;
@@ -112,9 +113,9 @@ PpinInitialize (
IN BOOLEAN State
)
{
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;
MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
ASSERT (MsrPpinCtrl != NULL);
//
@@ -143,14 +144,14 @@ PpinInitialize (
// According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.
//
MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;
MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;
MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;
} else {
//
// Disable and Lock.
// According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.
//
MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;
MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;
MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;
}
CPU_REGISTER_TABLE_WRITE64 (