UefiCpuPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
committed by
mergify[bot]
parent
91415a36ae
commit
053e878bfb
@ -17,8 +17,7 @@
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/// be terminated by an entry with the END bit set to 1, so 2
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/// entries are required to use a single valid entry.
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///
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#define MAX_TOPA_ENTRY_COUNT 2
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#define MAX_TOPA_ENTRY_COUNT 2
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///
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/// Processor trace output scheme selection.
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@ -29,25 +28,25 @@ typedef enum {
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} RTIT_OUTPUT_SCHEME;
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typedef struct {
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BOOLEAN TopaSupported;
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BOOLEAN SingleRangeSupported;
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MSR_IA32_RTIT_CTL_REGISTER RtitCtrl;
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MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase;
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MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs;
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BOOLEAN TopaSupported;
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BOOLEAN SingleRangeSupported;
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MSR_IA32_RTIT_CTL_REGISTER RtitCtrl;
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MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase;
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MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs;
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} PROC_TRACE_PROCESSOR_DATA;
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typedef struct {
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UINT32 NumberOfProcessors;
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UINT32 NumberOfProcessors;
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UINT8 ProcTraceOutputScheme;
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UINT32 ProcTraceMemSize;
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UINT8 ProcTraceOutputScheme;
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UINT32 ProcTraceMemSize;
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UINTN *ThreadMemRegionTable;
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UINTN AllocatedThreads;
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UINTN *ThreadMemRegionTable;
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UINTN AllocatedThreads;
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UINTN *TopaMemArray;
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UINTN *TopaMemArray;
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PROC_TRACE_PROCESSOR_DATA *ProcessorData;
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PROC_TRACE_PROCESSOR_DATA *ProcessorData;
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} PROC_TRACE_DATA;
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typedef struct {
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@ -73,10 +72,10 @@ ProcTraceGetConfigData (
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ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);
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ASSERT (ConfigData != NULL);
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ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA));
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ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *)((UINT8 *)ConfigData + sizeof (PROC_TRACE_DATA));
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ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors;
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ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
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ConfigData->NumberOfProcessors = (UINT32)NumberOfProcessors;
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ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
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ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);
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return ConfigData;
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@ -107,17 +106,18 @@ ProcTraceSupport (
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IN VOID *ConfigData OPTIONAL
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)
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{
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PROC_TRACE_DATA *ProcTraceData;
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
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CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
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PROC_TRACE_DATA *ProcTraceData;
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CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
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CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
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//
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// Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
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//
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ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
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ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
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ASSERT (ProcTraceData != NULL);
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if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||
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(ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {
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(ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA))
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{
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return FALSE;
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}
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@ -130,12 +130,13 @@ ProcTraceSupport (
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}
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AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);
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ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);
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ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);
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ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN)(Ecx.Bits.RTIT == 1);
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ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1);
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if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||
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(ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {
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ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
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ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
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(ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)))
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{
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ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
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ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
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ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
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return TRUE;
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}
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@ -170,36 +171,37 @@ ProcTraceInitialize (
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IN BOOLEAN State
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)
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{
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UINT32 MemRegionSize;
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UINTN Pages;
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UINTN Alignment;
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UINTN MemRegionBaseAddr;
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UINTN *ThreadMemRegionTable;
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UINTN Index;
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UINTN TopaTableBaseAddr;
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UINTN AlignedAddress;
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UINTN *TopaMemArray;
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PROC_TRACE_TOPA_TABLE *TopaTable;
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PROC_TRACE_DATA *ProcTraceData;
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BOOLEAN FirstIn;
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MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
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MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
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MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
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UINT32 MemRegionSize;
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UINTN Pages;
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UINTN Alignment;
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UINTN MemRegionBaseAddr;
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UINTN *ThreadMemRegionTable;
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UINTN Index;
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UINTN TopaTableBaseAddr;
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UINTN AlignedAddress;
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UINTN *TopaMemArray;
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PROC_TRACE_TOPA_TABLE *TopaTable;
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PROC_TRACE_DATA *ProcTraceData;
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BOOLEAN FirstIn;
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MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
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MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
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MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
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MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
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RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
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RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
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//
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// The scope of the MSR_IA32_RTIT_* is core for below processor type, only program
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// MSR_IA32_RTIT_* for thread 0 in each core.
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//
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if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
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IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
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IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
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{
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if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
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return RETURN_SUCCESS;
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}
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}
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ProcTraceData = (PROC_TRACE_DATA *) ConfigData;
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ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
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ASSERT (ProcTraceData != NULL);
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//
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@ -235,7 +237,7 @@ ProcTraceInitialize (
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}
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MemRegionBaseAddr = 0;
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FirstIn = FALSE;
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FirstIn = FALSE;
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if (ProcTraceData->ThreadMemRegionTable == NULL) {
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FirstIn = TRUE;
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@ -245,7 +247,7 @@ ProcTraceInitialize (
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///
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/// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
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///
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MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));
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MemRegionSize = (UINT32)(1 << (ProcTraceData->ProcTraceMemSize + 12));
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if (FirstIn) {
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DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
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}
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@ -258,32 +260,34 @@ ProcTraceInitialize (
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// address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
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// aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared.
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//
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ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
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ThreadMemRegionTable = (UINTN *)AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
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if (ThreadMemRegionTable == NULL) {
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DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
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return RETURN_OUT_OF_RESOURCES;
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}
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ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
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for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
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Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
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Alignment = MemRegionSize;
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AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
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Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
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Alignment = MemRegionSize;
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AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);
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if (AlignedAddress == 0) {
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DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));
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if (Index == 0) {
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//
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// Could not allocate for BSP even
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//
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FreePool ((VOID *) ThreadMemRegionTable);
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FreePool ((VOID *)ThreadMemRegionTable);
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ThreadMemRegionTable = NULL;
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return RETURN_OUT_OF_RESOURCES;
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}
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break;
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}
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ThreadMemRegionTable[Index] = AlignedAddress;
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DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index]));
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DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64)ThreadMemRegionTable[Index]));
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}
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DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));
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@ -303,7 +307,8 @@ ProcTraceInitialize (
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// Single Range output scheme
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//
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if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
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(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
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(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))
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{
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if (FirstIn) {
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DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
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}
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@ -322,9 +327,9 @@ ProcTraceInitialize (
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//
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// Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region
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//
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OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
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OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
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OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
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OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
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OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
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OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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@ -335,9 +340,9 @@ ProcTraceInitialize (
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//
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// Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)
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//
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OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
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OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
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OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;
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OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;
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OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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@ -350,7 +355,8 @@ ProcTraceInitialize (
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// ToPA(Table of physical address) scheme
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//
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if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
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(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
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(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA))
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{
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//
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// Create ToPA structure aligned at 4KB for each logical thread
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// with at least 2 entries by 8 bytes size each. The first entry
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@ -364,35 +370,38 @@ ProcTraceInitialize (
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//
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// Let BSP allocate ToPA table mem for all threads
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//
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TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
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TopaMemArray = (UINTN *)AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
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if (TopaMemArray == NULL) {
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DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
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return RETURN_OUT_OF_RESOURCES;
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}
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ProcTraceData->TopaMemArray = TopaMemArray;
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for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
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Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
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Alignment = 0x1000;
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AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);
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Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
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Alignment = 0x1000;
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AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);
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if (AlignedAddress == 0) {
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if (Index < ProcTraceData->AllocatedThreads) {
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ProcTraceData->AllocatedThreads = Index;
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}
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DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
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if (Index == 0) {
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//
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// Could not allocate for BSP even
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//
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FreePool ((VOID *) TopaMemArray);
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FreePool ((VOID *)TopaMemArray);
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TopaMemArray = NULL;
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return RETURN_OUT_OF_RESOURCES;
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}
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break;
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}
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TopaMemArray[Index] = AlignedAddress;
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DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index]));
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DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64)TopaMemArray[Index]));
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}
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DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));
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@ -404,26 +413,26 @@ ProcTraceInitialize (
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return RETURN_SUCCESS;
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}
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TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;
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TopaEntryPtr = &TopaTable->TopaEntry[0];
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TopaEntryPtr->Uint64 = 0;
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TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
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TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;
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TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
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TopaEntryPtr->Bits.END = 0;
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TopaTable = (PROC_TRACE_TOPA_TABLE *)TopaTableBaseAddr;
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TopaEntryPtr = &TopaTable->TopaEntry[0];
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TopaEntryPtr->Uint64 = 0;
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TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
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TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;
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TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
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TopaEntryPtr->Bits.END = 0;
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TopaEntryPtr = &TopaTable->TopaEntry[1];
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TopaEntryPtr->Uint64 = 0;
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TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
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TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
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TopaEntryPtr->Bits.END = 1;
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TopaEntryPtr = &TopaTable->TopaEntry[1];
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TopaEntryPtr->Uint64 = 0;
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TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
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TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;
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TopaEntryPtr->Bits.END = 1;
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//
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// Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base
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//
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OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
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OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
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OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;
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OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
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OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
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OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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@ -434,9 +443,9 @@ ProcTraceInitialize (
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//
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// Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0
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//
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OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
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OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
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OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;
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OutputMaskPtrsReg.Bits.OutputOffset = 0;
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OutputMaskPtrsReg.Bits.OutputOffset = 0;
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CPU_REGISTER_TABLE_WRITE64 (
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ProcessorNumber,
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Msr,
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@ -458,10 +467,10 @@ ProcTraceInitialize (
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///
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/// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)
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///
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CtrlReg.Bits.OS = 1;
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CtrlReg.Bits.User = 1;
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CtrlReg.Bits.OS = 1;
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CtrlReg.Bits.User = 1;
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CtrlReg.Bits.BranchEn = 1;
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CtrlReg.Bits.TraceEn = 1;
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CtrlReg.Bits.TraceEn = 1;
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CPU_REGISTER_TABLE_WRITE64 (
|
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ProcessorNumber,
|
||||
Msr,
|
||||
|
Reference in New Issue
Block a user