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UefiCpuPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiCpuPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:17 -08:00
committed by mergify[bot]
parent 91415a36ae
commit 053e878bfb
143 changed files with 14130 additions and 13035 deletions
Download Patch File Download Diff File Expand all files Collapse all files

110
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
View File

@@ -36,13 +36,13 @@ EnableCet (
**/
VOID
GetPageTable (
OUT UINTN *Base,
OUT BOOLEAN *FiveLevels OPTIONAL
OUT UINTN *Base,
OUT BOOLEAN *FiveLevels OPTIONAL
)
{
*Base = ((mInternalCr3 == 0) ?
(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :
mInternalCr3);
(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :
mInternalCr3);
if (FiveLevels != NULL) {
*FiveLevels = FALSE;
}
@@ -59,9 +59,9 @@ SmmInitPageTable (
VOID
)
{
UINTN PageFaultHandlerHookAddress;
IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
EFI_STATUS Status;
UINTN PageFaultHandlerHookAddress;
IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
EFI_STATUS Status;
//
// Initialize spin lock
@@ -72,18 +72,19 @@ SmmInitPageTable (
if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||
HEAP_GUARD_NONSTOP_MODE ||
NULL_DETECTION_NONSTOP_MODE) {
NULL_DETECTION_NONSTOP_MODE)
{
//
// Set own Page Fault entry instead of the default one, because SMM Profile
// feature depends on IRET instruction to do Single Step
//
PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;
IdtEntry += EXCEPT_IA32_PAGE_FAULT;
IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
IdtEntry->Bits.Reserved_0 = 0;
IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
IdtEntry += EXCEPT_IA32_PAGE_FAULT;
IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
IdtEntry->Bits.Reserved_0 = 0;
IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
} else {
//
// Register SMM Page Fault Handler
@@ -98,6 +99,7 @@ SmmInitPageTable (
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
InitializeIDTSmmStackGuard ();
}
return Gen4GPageTable (TRUE);
}
@@ -124,13 +126,13 @@ SmiDefaultPFHandler (
VOID
EFIAPI
SmiPFHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINTN PFAddress;
UINTN GuardPageAddress;
UINTN CpuIndex;
UINTN PFAddress;
UINTN GuardPageAddress;
UINTN CpuIndex;
ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);
@@ -143,25 +145,27 @@ SmiPFHandler (
// or SMM page protection violation.
//
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))
{
DumpCpuContext (InterruptType, SystemContext);
CpuIndex = GetCpuIndex ();
CpuIndex = GetCpuIndex ();
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize);
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(PFAddress >= GuardPageAddress) &&
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))
{
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else {
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);
);
);
} else {
DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%x)\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);
);
);
}
if (HEAP_GUARD_NONSTOP_MODE) {
@@ -169,6 +173,7 @@ SmiPFHandler (
goto Exit;
}
}
CpuDeadLoop ();
goto Exit;
}
@@ -177,13 +182,14 @@ SmiPFHandler (
// If a page fault occurs in non-SMRAM range.
//
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))
{
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);
);
);
CpuDeadLoop ();
goto Exit;
}
@@ -191,13 +197,14 @@ SmiPFHandler (
//
// If NULL pointer was just accessed
//
if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&
(PFAddress < EFI_PAGE_SIZE)) {
if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&
(PFAddress < EFI_PAGE_SIZE))
{
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);
);
);
if (NULL_DETECTION_NONSTOP_MODE) {
GuardPagePFHandler (SystemContext.SystemContextIa32->ExceptionData);
@@ -213,7 +220,7 @@ SmiPFHandler (
DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%x)!\n", PFAddress));
DEBUG_CODE (
DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);
);
);
CpuDeadLoop ();
goto Exit;
}
@@ -241,15 +248,15 @@ SetPageTableAttributes (
VOID
)
{
UINTN Index2;
UINTN Index3;
UINT64 *L1PageTable;
UINT64 *L2PageTable;
UINT64 *L3PageTable;
UINTN PageTableBase;
BOOLEAN IsSplitted;
BOOLEAN PageTableSplitted;
BOOLEAN CetEnabled;
UINTN Index2;
UINTN Index3;
UINT64 *L1PageTable;
UINT64 *L2PageTable;
UINT64 *L3PageTable;
UINTN PageTableBase;
BOOLEAN IsSplitted;
BOOLEAN PageTableSplitted;
BOOLEAN CetEnabled;
//
// Don't mark page table to read-only if heap guard is enabled.
@@ -259,7 +266,7 @@ SetPageTableAttributes (
//
if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) {
DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n"));
return ;
return;
}
//
@@ -267,7 +274,7 @@ SetPageTableAttributes (
//
if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n"));
return ;
return;
}
DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
@@ -276,14 +283,15 @@ SetPageTableAttributes (
// Disable write protection, because we need mark page table to be write protected.
// We need *write* page table memory, to mark itself to be *read only*.
//
CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
if (CetEnabled) {
//
// CET must be disabled if WP is disabled.
//
DisableCet();
DisableCet ();
}
AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
do {
DEBUG ((DEBUG_INFO, "Start...\n"));
@@ -304,15 +312,17 @@ SetPageTableAttributes (
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) {
for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M
continue;
}
L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L1PageTable == NULL) {
continue;
}
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
}
@@ -322,15 +332,15 @@ SetPageTableAttributes (
//
// Enable write protection, after page table updated.
//
AsmWriteCr0 (AsmReadCr0() | CR0_WP);
AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
if (CetEnabled) {
//
// re-enable CET.
//
EnableCet();
EnableCet ();
}
return ;
return;
}
/**
@@ -343,7 +353,7 @@ SaveCr2 (
OUT UINTN *Cr2
)
{
return ;
return;
}
/**
@@ -356,7 +366,7 @@ RestoreCr2 (
IN UINTN Cr2
)
{
return ;
return;
}
/**

2
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
View File

@@ -32,7 +32,7 @@ SemaphoreHook (
mRebasedFlag = RebasedFlag;
CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
mSmmRelocationOriginalAddress = (UINTN)HookReturnFromSmm (
CpuIndex,
CpuState,

76
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c
View File

@@ -8,18 +8,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "PiSmmCpuDxeSmm.h"
extern UINT64 gTaskGateDescriptor;
extern UINT64 gTaskGateDescriptor;
EFI_PHYSICAL_ADDRESS mGdtBuffer;
UINTN mGdtBufferSize;
EFI_PHYSICAL_ADDRESS mGdtBuffer;
UINTN mGdtBufferSize;
extern BOOLEAN mCetSupported;
extern UINTN mSmmShadowStackSize;
extern BOOLEAN mCetSupported;
extern UINTN mSmmShadowStackSize;
X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
UINT32 mCetPl0Ssp;
UINT32 mCetInterruptSsp;
X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;
X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;
UINT32 mCetPl0Ssp;
UINT32 mCetInterruptSsp;
/**
Initialize IDT for SMM Stack Guard.
@@ -38,8 +38,8 @@ InitializeIDTSmmStackGuard (
// is a Task Gate Descriptor so that when a Page Fault Exception occurs,
// the processors can use a known good stack in case stack is ran out.
//
IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
IdtGate += EXCEPT_IA32_PAGE_FAULT;
IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
IdtGate += EXCEPT_IA32_PAGE_FAULT;
IdtGate->Uint64 = gTaskGateDescriptor;
}
@@ -58,13 +58,13 @@ InitGdt (
OUT UINTN *GdtStepSize
)
{
UINTN Index;
IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
UINTN TssBase;
UINTN GdtTssTableSize;
UINT8 *GdtTssTables;
UINTN GdtTableStepSize;
UINTN InterruptShadowStack;
UINTN Index;
IA32_SEGMENT_DESCRIPTOR *GdtDescriptor;
UINTN TssBase;
UINTN GdtTssTableSize;
UINT8 *GdtTssTables;
UINTN GdtTableStepSize;
UINTN InterruptShadowStack;
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
//
@@ -79,46 +79,46 @@ InitGdt (
gcSmiGdtr.Limit += (UINT16)(2 * sizeof (IA32_SEGMENT_DESCRIPTOR));
GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE + 7) & ~7; // 8 bytes aligned
mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
//
// IA32 Stack Guard need use task switch to switch stack that need
// write GDT and TSS, so AllocateCodePages() could not be used here
// as code pages will be set to RO.
//
GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
GdtTssTables = (UINT8 *)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL);
mGdtBuffer = (UINTN)GdtTssTables;
mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE);
CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE);
//
// Fixup TSS descriptors
//
TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);
GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;
GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);
TssBase += TSS_SIZE;
GdtDescriptor++;
GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;
GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);
GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);
//
// Fixup TSS segments
//
// ESP as known good stack
//
*(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;
*(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) = mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;
*(UINT32 *)(TssBase + TSS_IA32_CR3_OFFSET) = Cr3;
//
// Setup ShadowStack for stack switch
//
if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof(UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index);
InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index);
*(UINT32 *)(TssBase + TSS_IA32_SSP_OFFSET) = (UINT32)InterruptShadowStack;
}
}
@@ -127,14 +127,14 @@ InitGdt (
// Just use original table, AllocatePage and copy them here to make sure GDTs are covered in page memory.
//
GdtTssTableSize = gcSmiGdtr.Limit + 1;
mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
GdtTssTables = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL);
mGdtBuffer = (UINTN)GdtTssTables;
mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);
CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);
}
}
@@ -181,24 +181,24 @@ InitShadowStack (
IN VOID *ShadowStack
)
{
UINTN SmmShadowStackSize;
UINTN SmmShadowStackSize;
if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
SmmShadowStackSize += EFI_PAGES_TO_SIZE (2);
}
mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));
mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));
PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));
DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));
mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64));
PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);
DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));
}
}
}

14
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
View File

@@ -20,7 +20,7 @@ InitSmmS3Cr3 (
{
mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (TRUE);
return ;
return;
}
/**
@@ -49,11 +49,11 @@ InitPagesForPFHandler (
**/
VOID
RestorePageTableAbove4G (
UINT64 *PageTable,
UINT64 PFAddress,
UINTN CpuIndex,
UINTN ErrorCode,
BOOLEAN *IsValidPFAddress
UINT64 *PageTable,
UINT64 PFAddress,
UINTN CpuIndex,
UINTN ErrorCode,
BOOLEAN *IsValidPFAddress
)
{
}
@@ -67,7 +67,7 @@ RestorePageTableAbove4G (
**/
VOID
ClearTrapFlag (
IN OUT EFI_SYSTEM_CONTEXT SystemContext
IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
SystemContext.SystemContextIa32->Eflags &= (UINTN) ~BIT8;

62
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h
View File

@@ -12,42 +12,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack (1)
typedef struct _MSR_DS_AREA_STRUCT {
UINT32 BTSBufferBase;
UINT32 BTSIndex;
UINT32 BTSAbsoluteMaximum;
UINT32 BTSInterruptThreshold;
UINT32 PEBSBufferBase;
UINT32 PEBSIndex;
UINT32 PEBSAbsoluteMaximum;
UINT32 PEBSInterruptThreshold;
UINT32 PEBSCounterReset[4];
UINT32 Reserved;
UINT32 BTSBufferBase;
UINT32 BTSIndex;
UINT32 BTSAbsoluteMaximum;
UINT32 BTSInterruptThreshold;
UINT32 PEBSBufferBase;
UINT32 PEBSIndex;
UINT32 PEBSAbsoluteMaximum;
UINT32 PEBSInterruptThreshold;
UINT32 PEBSCounterReset[4];
UINT32 Reserved;
} MSR_DS_AREA_STRUCT;
typedef struct _BRANCH_TRACE_RECORD {
UINT32 LastBranchFrom;
UINT32 LastBranchTo;
UINT32 Rsvd0 : 4;
UINT32 BranchPredicted : 1;
UINT32 Rsvd1 : 27;
UINT32 LastBranchFrom;
UINT32 LastBranchTo;
UINT32 Rsvd0 : 4;
UINT32 BranchPredicted : 1;
UINT32 Rsvd1 : 27;
} BRANCH_TRACE_RECORD;
typedef struct _PEBS_RECORD {
UINT32 Eflags;
UINT32 LinearIP;
UINT32 Eax;
UINT32 Ebx;
UINT32 Ecx;
UINT32 Edx;
UINT32 Esi;
UINT32 Edi;
UINT32 Ebp;
UINT32 Esp;
UINT32 Eflags;
UINT32 LinearIP;
UINT32 Eax;
UINT32 Ebx;
UINT32 Ecx;
UINT32 Edx;
UINT32 Esi;
UINT32 Edi;
UINT32 Ebp;
UINT32 Esp;
} PEBS_RECORD;
#pragma pack ()
#define PHYSICAL_ADDRESS_MASK ((1ull << 32) - SIZE_4KB)
#define PHYSICAL_ADDRESS_MASK ((1ull << 32) - SIZE_4KB)
/**
Update page table to map the memory correctly in order to make the instruction
@@ -63,11 +63,11 @@ typedef struct _PEBS_RECORD {
**/
VOID
RestorePageTableAbove4G (
UINT64 *PageTable,
UINT64 PFAddress,
UINTN CpuIndex,
UINTN ErrorCode,
BOOLEAN *IsValidPFAddress
UINT64 *PageTable,
UINT64 PFAddress,
UINTN CpuIndex,
UINTN ErrorCode,
BOOLEAN *IsValidPFAddress
);
/**