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UefiCpuPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiCpuPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:17 -08:00
committed by mergify[bot]
parent 91415a36ae
commit 053e878bfb
143 changed files with 14130 additions and 13035 deletions
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441
UefiCpuPkg/Application/Cpuid/Cpuid.c
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@@ -36,119 +36,119 @@ typedef struct {
/// Cache description lookup table /// Cache description lookup table
/// ///
CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = { CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {
{ 0x00 , "General" , "Null descriptor, this byte contains no information" }, { 0x00, "General", "Null descriptor, this byte contains no information" },
{ 0x01 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" }, { 0x01, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },
{ 0x02 , "TLB" , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" }, { 0x02, "TLB", "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },
{ 0x03 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" }, { 0x03, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },
{ 0x04 , "TLB" , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" }, { 0x04, "TLB", "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },
{ 0x05 , "TLB" , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" }, { 0x05, "TLB", "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },
{ 0x06 , "Cache" , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" }, { 0x06, "Cache", "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },
{ 0x08 , "Cache" , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" }, { 0x08, "Cache", "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },
{ 0x09 , "Cache" , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" }, { 0x09, "Cache", "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },
{ 0x0A , "Cache" , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" }, { 0x0A, "Cache", "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },
{ 0x0B , "TLB" , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" }, { 0x0B, "TLB", "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },
{ 0x0C , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" }, { 0x0C, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },
{ 0x0D , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" }, { 0x0D, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },
{ 0x0E , "Cache" , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" }, { 0x0E, "Cache", "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },
{ 0x1D , "Cache" , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" }, { 0x1D, "Cache", "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },
{ 0x21 , "Cache" , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" }, { 0x21, "Cache", "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },
{ 0x22 , "Cache" , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" }, { 0x22, "Cache", "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x23 , "Cache" , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x23, "Cache", "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x24 , "Cache" , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" }, { 0x24, "Cache", "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },
{ 0x25 , "Cache" , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x25, "Cache", "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x29 , "Cache" , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x29, "Cache", "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x2C , "Cache" , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" }, { 0x2C, "Cache", "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },
{ 0x30 , "Cache" , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" }, { 0x30, "Cache", "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },
{ 0x40 , "Cache" , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" }, { 0x40, "Cache", "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },
{ 0x41 , "Cache" , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" }, { 0x41, "Cache", "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },
{ 0x42 , "Cache" , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" }, { 0x42, "Cache", "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },
{ 0x43 , "Cache" , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" }, { 0x43, "Cache", "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },
{ 0x44 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" }, { 0x44, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },
{ 0x45 , "Cache" , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" }, { 0x45, "Cache", "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },
{ 0x46 , "Cache" , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" }, { 0x46, "Cache", "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },
{ 0x47 , "Cache" , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" }, { 0x47, "Cache", "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },
{ 0x48 , "Cache" , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" }, { 0x48, "Cache", "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },
{ 0x49 , "Cache" , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" }, { 0x49, "Cache", "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
{ 0x4A , "Cache" , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" }, { 0x4A, "Cache", "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },
{ 0x4B , "Cache" , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" }, { 0x4B, "Cache", "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },
{ 0x4C , "Cache" , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" }, { 0x4C, "Cache", "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },
{ 0x4D , "Cache" , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" }, { 0x4D, "Cache", "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },
{ 0x4E , "Cache" , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" }, { 0x4E, "Cache", "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },
{ 0x4F , "TLB" , "Instruction TLB: 4 KByte pages, 32 entries" }, { 0x4F, "TLB", "Instruction TLB: 4 KByte pages, 32 entries" },
{ 0x50 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" }, { 0x50, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },
{ 0x51 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" }, { 0x51, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },
{ 0x52 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" }, { 0x52, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },
{ 0x55 , "TLB" , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" }, { 0x55, "TLB", "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },
{ 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" }, { 0x56, "TLB", "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },
{ 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" }, { 0x57, "TLB", "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },
{ 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" }, { 0x59, "TLB", "Data TLB0: 4 KByte pages, fully associative, 16 entries" },
{ 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" }, { 0x5A, "TLB", "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },
{ 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" }, { 0x5B, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },
{ 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" }, { 0x5C, "TLB", "Data TLB: 4 KByte and 4 MByte pages,128 entries" },
{ 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" }, { 0x5D, "TLB", "Data TLB: 4 KByte and 4 MByte pages,256 entries" },
{ 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" }, { 0x60, "Cache", "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },
{ 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" }, { 0x61, "TLB", "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },
{ 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" }, { 0x63, "TLB", "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },
{ 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" }, { 0x64, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },
{ 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" }, { 0x66, "Cache", "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },
{ 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" }, { 0x67, "Cache", "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },
{ 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" }, { 0x68, "Cache", "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },
{ 0x6A , "Cache" , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" }, { 0x6A, "Cache", "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },
{ 0x6B , "Cache" , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" }, { 0x6B, "Cache", "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },
{ 0x6C , "Cache" , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" }, { 0x6C, "Cache", "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },
{ 0x6D , "Cache" , "DTLB: 1 GByte pages, fully associative, 16 entries" }, { 0x6D, "Cache", "DTLB: 1 GByte pages, fully associative, 16 entries" },
{ 0x70 , "Cache" , "Trace cache: 12 K-uop, 8-way set associative" }, { 0x70, "Cache", "Trace cache: 12 K-uop, 8-way set associative" },
{ 0x71 , "Cache" , "Trace cache: 16 K-uop, 8-way set associative" }, { 0x71, "Cache", "Trace cache: 16 K-uop, 8-way set associative" },
{ 0x72 , "Cache" , "Trace cache: 32 K-uop, 8-way set associative" }, { 0x72, "Cache", "Trace cache: 32 K-uop, 8-way set associative" },
{ 0x76 , "TLB" , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" }, { 0x76, "TLB", "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },
{ 0x78 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" }, { 0x78, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },
{ 0x79 , "Cache" , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x79, "Cache", "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x7A , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x7A, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x7B , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x7B, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x7C , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x7C, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x7D , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" }, { 0x7D, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },
{ 0x7F , "Cache" , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" }, { 0x7F, "Cache", "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },
{ 0x80 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" }, { 0x80, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },
{ 0x82 , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" }, { 0x82, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },
{ 0x83 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" }, { 0x83, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },
{ 0x84 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" }, { 0x84, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },
{ 0x85 , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" }, { 0x85, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },
{ 0x86 , "Cache" , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, { 0x86, "Cache", "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
{ 0x87 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" }, { 0x87, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
{ 0xA0 , "DTLB" , "DTLB: 4k pages, fully associative, 32 entries" }, { 0xA0, "DTLB", "DTLB: 4k pages, fully associative, 32 entries" },
{ 0xB0 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" }, { 0xB0, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },
{ 0xB1 , "TLB" , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" }, { 0xB1, "TLB", "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },
{ 0xB2 , "TLB" , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" }, { 0xB2, "TLB", "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },
{ 0xB3 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" }, { 0xB3, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },
{ 0xB4 , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" }, { 0xB4, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },
{ 0xB5 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" }, { 0xB5, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },
{ 0xB6 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" }, { 0xB6, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },
{ 0xBA , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" }, { 0xBA, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },
{ 0xC0 , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" }, { 0xC0, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },
{ 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" }, { 0xC1, "STLB", "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },
{ 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" }, { 0xC2, "DTLB", "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },
{ 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." }, { 0xC3, "STLB", "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },
{ 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" }, { 0xC4, "DTLB", "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },
{ 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" }, { 0xCA, "STLB", "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },
{ 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, { 0xD0, "Cache", "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
{ 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" }, { 0xD1, "Cache", "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },
{ 0xD2 , "Cache" , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" }, { 0xD2, "Cache", "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },
{ 0xD6 , "Cache" , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" }, { 0xD6, "Cache", "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
{ 0xD7 , "Cache" , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" }, { 0xD7, "Cache", "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },
{ 0xD8 , "Cache" , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" }, { 0xD8, "Cache", "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },
{ 0xDC , "Cache" , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" }, { 0xDC, "Cache", "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },
{ 0xDD , "Cache" , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" }, { 0xDD, "Cache", "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },
{ 0xDE , "Cache" , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" }, { 0xDE, "Cache", "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },
{ 0xE2 , "Cache" , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" }, { 0xE2, "Cache", "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },
{ 0xE3 , "Cache" , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" }, { 0xE3, "Cache", "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
{ 0xE4 , "Cache" , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" }, { 0xE4, "Cache", "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },
{ 0xEA , "Cache" , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" }, { 0xEA, "Cache", "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },
{ 0xEB , "Cache" , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" }, { 0xEB, "Cache", "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },
{ 0xEC , "Cache" , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" }, { 0xEC, "Cache", "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },
{ 0xF0 , "Prefetch" , "64-Byte prefetching" }, { 0xF0, "Prefetch", "64-Byte prefetching" },
{ 0xF1 , "Prefetch" , "128-Byte prefetching" }, { 0xF1, "Prefetch", "128-Byte prefetching" },
{ 0xFE , "General" , "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." }, { 0xFE, "General", "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },
{ 0xFF , "General" , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" } { 0xFF, "General", "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }
}; };
/// ///
@@ -184,7 +184,7 @@ CpuidSignature (
*(UINT32 *)(Signature + 0) = Ebx; *(UINT32 *)(Signature + 0) = Ebx;
*(UINT32 *)(Signature + 4) = Edx; *(UINT32 *)(Signature + 4) = Edx;
*(UINT32 *)(Signature + 8) = Ecx; *(UINT32 *)(Signature + 8) = Ecx;
Signature [12] = 0; Signature[12] = 0;
Print (L" Signature = %a\n", Signature); Print (L" Signature = %a\n", Signature);
gMaximumBasicFunction = Eax; gMaximumBasicFunction = Eax;
@@ -221,7 +221,7 @@ CpuidVersionInfo (
} }
DisplayModel = Eax.Bits.Model; DisplayModel = Eax.Bits.Model;
if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) { if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {
DisplayModel |= (Eax.Bits.ExtendedModelId << 4); DisplayModel |= (Eax.Bits.ExtendedModelId << 4);
} }
@@ -314,12 +314,14 @@ LookupCacheDescription (
if (CacheDescriptor == 0x00) { if (CacheDescriptor == 0x00) {
return NULL; return NULL;
} }
NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]); NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);
for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) { for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {
if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) { if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {
return &mCpuidCacheInfoDescription[Descriptor]; return &mCpuidCacheInfoDescription[Descriptor];
} }
} }
return NULL; return NULL;
} }
@@ -354,13 +356,15 @@ CpuidCacheInfo (
for (Index = 1; Index < 4; Index++) { for (Index = 1; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]); CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);
if (CacheDescription != NULL) { if (CacheDescription != NULL) {
Print (L" %-8a %a\n", Print (
L" %-8a %a\n",
CacheDescription->Type, CacheDescription->Type,
CacheDescription->Description CacheDescription->Description
); );
} }
} }
} }
if (Ebx.Bits.NotValid == 0) { if (Ebx.Bits.NotValid == 0) {
// //
// Process Ebx.CacheDescriptor[0..3] // Process Ebx.CacheDescriptor[0..3]
@@ -368,13 +372,15 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) { for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]); CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);
if (CacheDescription != NULL) { if (CacheDescription != NULL) {
Print (L" %-8a %a\n", Print (
L" %-8a %a\n",
CacheDescription->Type, CacheDescription->Type,
CacheDescription->Description CacheDescription->Description
); );
} }
} }
} }
if (Ecx.Bits.NotValid == 0) { if (Ecx.Bits.NotValid == 0) {
// //
// Process Ecx.CacheDescriptor[0..3] // Process Ecx.CacheDescriptor[0..3]
@@ -382,13 +388,15 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) { for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]); CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);
if (CacheDescription != NULL) { if (CacheDescription != NULL) {
Print (L" %-8a %a\n", Print (
L" %-8a %a\n",
CacheDescription->Type, CacheDescription->Type,
CacheDescription->Description CacheDescription->Description
); );
} }
} }
} }
if (Edx.Bits.NotValid == 0) { if (Edx.Bits.NotValid == 0) {
// //
// Process Edx.CacheDescriptor[0..3] // Process Edx.CacheDescriptor[0..3]
@@ -396,7 +404,8 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) { for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]); CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);
if (CacheDescription != NULL) { if (CacheDescription != NULL) {
Print (L" %-8a %a\n", Print (
L" %-8a %a\n",
CacheDescription->Type, CacheDescription->Type,
CacheDescription->Description CacheDescription->Description
); );
@@ -457,8 +466,12 @@ CpuidCacheParams (
CacheLevel = 0; CacheLevel = 0;
do { do {
AsmCpuidEx ( AsmCpuidEx (
CPUID_CACHE_PARAMS, CacheLevel, CPUID_CACHE_PARAMS,
&Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32 CacheLevel,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx,
&Edx.Uint32
); );
if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) { if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {
Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel); Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);
@@ -477,6 +490,7 @@ CpuidCacheParams (
PRINT_BIT_FIELD (Edx, CacheInclusiveness); PRINT_BIT_FIELD (Edx, CacheInclusiveness);
PRINT_BIT_FIELD (Edx, ComplexCacheIndexing); PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);
} }
CacheLevel++; CacheLevel++;
} while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL); } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
} }
@@ -585,15 +599,21 @@ CpuidStructuredExtendedFeatureFlags (
AsmCpuidEx ( AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
&Eax, NULL, NULL, NULL &Eax,
NULL,
NULL,
NULL
); );
for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) { for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
AsmCpuidEx ( AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
SubLeaf, SubLeaf,
NULL, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 NULL,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0 || Edx.Uint32 != 0) { if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) {
Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf); Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
PRINT_BIT_FIELD (Ebx, FSGSBASE); PRINT_BIT_FIELD (Ebx, FSGSBASE);
@@ -725,6 +745,7 @@ CpuidExtendedTopology (
if (LeafFunction > gMaximumBasicFunction) { if (LeafFunction > gMaximumBasicFunction) {
return; return;
} }
if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) { if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {
return; return;
} }
@@ -732,16 +753,22 @@ CpuidExtendedTopology (
LevelNumber = 0; LevelNumber = 0;
for (LevelNumber = 0; ; LevelNumber++) { for (LevelNumber = 0; ; LevelNumber++) {
AsmCpuidEx ( AsmCpuidEx (
LeafFunction, LevelNumber, LeafFunction,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx LevelNumber,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx
); );
if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break; break;
} }
Print ( Print (
L"%a (Leaf %08x, Sub-Leaf %08x)\n", L"%a (Leaf %08x, Sub-Leaf %08x)\n",
LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY", LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",
LeafFunction, LevelNumber LeafFunction,
LevelNumber
); );
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);
PRINT_BIT_FIELD (Eax, ApicIdShift); PRINT_BIT_FIELD (Eax, ApicIdShift);
@@ -767,8 +794,12 @@ CpuidExtendedStateSubLeaf (
UINT32 Edx; UINT32 Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, CPUID_EXTENDED_STATE,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx CPUID_EXTENDED_STATE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx
); );
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF); Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);
@@ -801,8 +832,12 @@ CpuidExtendedStateSizeOffset (
for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) { for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
AsmCpuidEx ( AsmCpuidEx (
CPUID_EXTENDED_STATE, SubLeaf, CPUID_EXTENDED_STATE,
&Eax, &Ebx, &Ecx.Uint32, &Edx SubLeaf,
&Eax,
&Ebx,
&Ecx.Uint32,
&Edx
); );
if (Edx != 0) { if (Edx != 0) {
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf); Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);
@@ -834,8 +869,12 @@ CpuidExtendedStateMainLeaf (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF, CPUID_EXTENDED_STATE,
&Eax.Uint32, &Ebx, &Ecx, &Edx CPUID_EXTENDED_STATE_MAIN_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx,
&Edx
); );
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF); Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);
@@ -872,8 +911,12 @@ CpuidIntelRdtMonitoringEnumerationSubLeaf (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, CPUID_INTEL_RDT_MONITORING,
NULL, &Ebx, NULL, &Edx.Uint32 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
NULL,
&Ebx,
NULL,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF); Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);
@@ -899,8 +942,12 @@ CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, CPUID_INTEL_RDT_MONITORING,
NULL, &Ebx, &Ecx, &Edx.Uint32 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
NULL,
&Ebx,
&Ecx,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF); Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);
@@ -927,8 +974,12 @@ CpuidIntelRdtAllocationMemoryBandwidthSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx; CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF, CPUID_INTEL_RDT_ALLOCATION,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
@@ -954,8 +1005,12 @@ CpuidIntelRdtAllocationL3CacheSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, CPUID_INTEL_RDT_ALLOCATION,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
@@ -980,8 +1035,12 @@ CpuidIntelRdtAllocationL2CacheSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, CPUID_INTEL_RDT_ALLOCATION,
&Eax.Uint32, &Ebx, NULL, &Edx.Uint32 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
NULL,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
@@ -1006,8 +1065,12 @@ CpuidIntelRdtAllocationMainLeaf (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, CPUID_INTEL_RDT_ALLOCATION,
NULL, &Ebx.Uint32, NULL, NULL CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
NULL,
&Ebx.Uint32,
NULL,
NULL
); );
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);
@@ -1033,8 +1096,12 @@ CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx; CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF, CPUID_INTEL_SGX,
&Eax.Uint32, &Ebx, NULL, &Edx.Uint32 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
&Eax.Uint32,
&Ebx,
NULL,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF); Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
@@ -1061,8 +1128,12 @@ CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (
UINT32 Edx; UINT32 Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF, CPUID_INTEL_SGX,
&Eax, &Ebx, &Ecx, &Edx CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
&Eax,
&Ebx,
&Ecx,
&Edx
); );
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF); Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);
@@ -1086,8 +1157,12 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf (
SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF; SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;
do { do {
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_SGX, SubLeaf, CPUID_INTEL_SGX,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 SubLeaf,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
if (Eax.Bits.SubLeafType == 0x1) { if (Eax.Bits.SubLeafType == 0x1) {
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf); Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);
@@ -1099,6 +1174,7 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf (
PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection); PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);
PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection); PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);
} }
SubLeaf++; SubLeaf++;
} while (Eax.Bits.SubLeafType == 0x1); } while (Eax.Bits.SubLeafType == 0x1);
} }
@@ -1121,7 +1197,10 @@ CpuidEnumerationOfIntelSgx (
AsmCpuidEx ( AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
NULL, &Ebx.Uint32, NULL, NULL NULL,
&Ebx.Uint32,
NULL,
NULL
); );
if (Ebx.Bits.SGX != 1) { if (Ebx.Bits.SGX != 1) {
// //
@@ -1153,8 +1232,12 @@ CpuidIntelProcessorTraceSubLeaf (
for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) { for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_PROCESSOR_TRACE, SubLeaf, CPUID_INTEL_PROCESSOR_TRACE,
&Eax.Uint32, &Ebx.Uint32, NULL, NULL SubLeaf,
&Eax.Uint32,
&Ebx.Uint32,
NULL,
NULL
); );
Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf); Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);
@@ -1183,8 +1266,12 @@ CpuidIntelProcessorTraceMainLeaf (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, CPUID_INTEL_PROCESSOR_TRACE,
&Eax, &Ebx.Uint32, &Ecx.Uint32, NULL CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
&Eax,
&Ebx.Uint32,
&Ecx.Uint32,
NULL
); );
Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF); Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);
@@ -1273,8 +1360,12 @@ CpuidSocVendorBrandString (
UINT32 BrandString[3 * 4 + 1]; UINT32 BrandString[3 * 4 + 1];
AsmCpuidEx ( AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1, CPUID_SOC_VENDOR,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 CPUID_SOC_VENDOR_BRAND_STRING1,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1284,8 +1375,12 @@ CpuidSocVendorBrandString (
BrandString[3] = Edx.Uint32; BrandString[3] = Edx.Uint32;
AsmCpuidEx ( AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2, CPUID_SOC_VENDOR,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 CPUID_SOC_VENDOR_BRAND_STRING2,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1295,8 +1390,12 @@ CpuidSocVendorBrandString (
BrandString[7] = Edx.Uint32; BrandString[7] = Edx.Uint32;
AsmCpuidEx ( AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3, CPUID_SOC_VENDOR,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 CPUID_SOC_VENDOR_BRAND_STRING3,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1329,8 +1428,12 @@ CpuidSocVendor (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF, CPUID_SOC_VENDOR,
&Eax, &Ebx.Uint32, &Ecx, &Edx CPUID_SOC_VENDOR_MAIN_LEAF,
&Eax,
&Ebx.Uint32,
&Ecx,
&Edx
); );
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);
@@ -1338,6 +1441,7 @@ CpuidSocVendor (
Print (L" Not Supported\n"); Print (L" Not Supported\n");
return; return;
} }
PRINT_VALUE (Eax, MaxSOCID_Index); PRINT_VALUE (Eax, MaxSOCID_Index);
PRINT_BIT_FIELD (Ebx, SocVendorId); PRINT_BIT_FIELD (Ebx, SocVendorId);
PRINT_BIT_FIELD (Ebx, IsVendorScheme); PRINT_BIT_FIELD (Ebx, IsVendorScheme);
@@ -1367,7 +1471,10 @@ CpuidDeterministicAddressTranslationParameters (
AsmCpuidEx ( AsmCpuidEx (
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
&Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32 &Eax,
&Ebx.Uint32,
&Ecx,
&Edx.Uint32
); );
Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF); Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);
@@ -1583,11 +1690,11 @@ UefiMain (
CpuidVersionInfo (); CpuidVersionInfo ();
CpuidCacheInfo (); CpuidCacheInfo ();
CpuidSerialNumber (); CpuidSerialNumber ();
CpuidCacheParams(); CpuidCacheParams ();
CpuidMonitorMwait (); CpuidMonitorMwait ();
CpuidThermalPowerManagement (); CpuidThermalPowerManagement ();
CpuidStructuredExtendedFeatureFlags (); CpuidStructuredExtendedFeatureFlags ();
CpuidDirectCacheAccessInfo(); CpuidDirectCacheAccessInfo ();
CpuidArchitecturalPerformanceMonitoring (); CpuidArchitecturalPerformanceMonitoring ();
CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY); CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY);
CpuidExtendedStateMainLeaf (); CpuidExtendedStateMainLeaf ();

150
UefiCpuPkg/CpuDxe/CpuDxe.c
View File

@@ -79,7 +79,6 @@ FIXED_MTRR mFixedMtrrTable[] = {
}, },
}; };
EFI_CPU_ARCH_PROTOCOL gCpu = { EFI_CPU_ARCH_PROTOCOL gCpu = {
CpuFlushCpuDataCache, CpuFlushCpuDataCache,
CpuEnableInterrupt, CpuEnableInterrupt,
@@ -132,7 +131,6 @@ CpuFlushCpuDataCache (
} }
} }
/** /**
Enables CPU interrupts. Enables CPU interrupts.
@@ -154,7 +152,6 @@ CpuEnableInterrupt (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Disables CPU interrupts. Disables CPU interrupts.
@@ -176,7 +173,6 @@ CpuDisableInterrupt (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Return the state of interrupts. Return the state of interrupts.
@@ -202,7 +198,6 @@ CpuGetInterruptState (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Generates an INIT to the CPU. Generates an INIT to the CPU.
@@ -225,7 +220,6 @@ CpuInit (
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
/** /**
Registers a function to be called from the CPU interrupt handler. Registers a function to be called from the CPU interrupt handler.
@@ -257,7 +251,6 @@ CpuRegisterInterruptHandler (
return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
} }
/** /**
Returns a timer value from one of the CPU's internal timers. There is no Returns a timer value from one of the CPU's internal timers. There is no
inherent time interval between ticks but is a function of the CPU frequency. inherent time interval between ticks but is a function of the CPU frequency.
@@ -323,6 +316,7 @@ CpuGetTimerValue (
NULL NULL
); );
} }
*TimerPeriod = mTimerPeriod; *TimerPeriod = mTimerPeriod;
} }
@@ -395,7 +389,7 @@ CpuSetMemoryAttributes (
// to avoid unnecessary computing. // to avoid unnecessary computing.
// //
if (mIsFlushingGCD) { if (mIsFlushingGCD) {
DEBUG((DEBUG_VERBOSE, " Flushing GCD\n")); DEBUG ((DEBUG_VERBOSE, " Flushing GCD\n"));
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -410,7 +404,7 @@ CpuSetMemoryAttributes (
// by page table memory allocation. // by page table memory allocation.
// //
if (mIsAllocatingPageTable) { if (mIsAllocatingPageTable) {
DEBUG((DEBUG_VERBOSE, " Allocating page table memory\n")); DEBUG ((DEBUG_VERBOSE, " Allocating page table memory\n"));
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -450,7 +444,8 @@ CpuSetMemoryAttributes (
default: default:
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);
CurrentCacheType = MtrrGetMemoryAttribute (BaseAddress);
if (CurrentCacheType != CacheType) { if (CurrentCacheType != CacheType) {
// //
// call MTRR library function // call MTRR library function
@@ -484,7 +479,8 @@ CpuSetMemoryAttributes (
ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED); ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);
} }
} }
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status; return Status;
} }
} }
@@ -515,7 +511,7 @@ InitializeMtrrMask (
if (RegEax >= 0x80000008) { if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax; PhysicalAddressBits = (UINT8)RegEax;
} else { } else {
PhysicalAddressBits = 36; PhysicalAddressBits = 36;
} }
@@ -588,16 +584,20 @@ SearchGcdMemorySpaces (
*StartIndex = 0; *StartIndex = 0;
*EndIndex = 0; *EndIndex = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) { for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (BaseAddress >= MemorySpaceMap[Index].BaseAddress && if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&
BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { (BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))
{
*StartIndex = Index; *StartIndex = Index;
} }
if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { if ((BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress) &&
(BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))
{
*EndIndex = Index; *EndIndex = Index;
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
@@ -655,6 +655,7 @@ SetGcdMemorySpaceAttributes (
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue; continue;
} }
// //
// Calculate the start and end address of the overlapping range // Calculate the start and end address of the overlapping range
// //
@@ -663,11 +664,13 @@ SetGcdMemorySpaceAttributes (
} else { } else {
RegionStart = MemorySpaceMap[Index].BaseAddress; RegionStart = MemorySpaceMap[Index].BaseAddress;
} }
if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
RegionLength = BaseAddress + Length - RegionStart; RegionLength = BaseAddress + Length - RegionStart;
} else { } else {
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart; RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
} }
// //
// Set memory attributes according to MTRR attribute and the original attribute of descriptor // Set memory attributes according to MTRR attribute and the original attribute of descriptor
// //
@@ -681,7 +684,6 @@ SetGcdMemorySpaceAttributes (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Refreshes the GCD Memory Space attributes according to MTRRs. Refreshes the GCD Memory Space attributes according to MTRRs.
@@ -738,7 +740,7 @@ RefreshMemoryAttributesFromMtrr (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType (); DefaultMemoryType = (UINT8)MtrrGetDefaultMemoryType ();
DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType); DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);
// //
@@ -748,6 +750,7 @@ RefreshMemoryAttributesFromMtrr (
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue; continue;
} }
gDS->SetMemorySpaceAttributes ( gDS->SetMemorySpaceAttributes (
MemorySpaceMap[Index].BaseAddress, MemorySpaceMap[Index].BaseAddress,
MemorySpaceMap[Index].Length, MemorySpaceMap[Index].Length,
@@ -761,7 +764,8 @@ RefreshMemoryAttributesFromMtrr (
// //
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid && if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) { (VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK))
{
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
MemorySpaceMap, MemorySpaceMap,
NumberOfDescriptors, NumberOfDescriptors,
@@ -777,9 +781,10 @@ RefreshMemoryAttributesFromMtrr (
// //
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid && if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK && (VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) &&
VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) { (VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE))
Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type); {
Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8)VariableMtrr[Index].Type);
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
MemorySpaceMap, MemorySpaceMap,
NumberOfDescriptors, NumberOfDescriptors,
@@ -795,7 +800,8 @@ RefreshMemoryAttributesFromMtrr (
// //
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid && if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) { (VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE))
{
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
MemorySpaceMap, MemorySpaceMap,
NumberOfDescriptors, NumberOfDescriptors,
@@ -819,7 +825,7 @@ RefreshMemoryAttributesFromMtrr (
// Check for continuous fixed MTRR sections // Check for continuous fixed MTRR sections
// //
for (SubIndex = 0; SubIndex < 8; SubIndex++) { for (SubIndex = 0; SubIndex < 8; SubIndex++) {
MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8); MtrrType = (UINT8)RShiftU64 (RegValue, SubIndex * 8);
CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType); CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
if (Length == 0) { if (Length == 0) {
// //
@@ -843,9 +849,11 @@ RefreshMemoryAttributesFromMtrr (
Attributes = CurrentAttributes; Attributes = CurrentAttributes;
} }
} }
Length += mFixedMtrrTable[Index].Length; Length += mFixedMtrrTable[Index].Length;
} }
} }
// //
// Handle the last fixed MTRR region // Handle the last fixed MTRR region
// //
@@ -921,15 +929,15 @@ InitInterruptDescriptorTable (
EFI_VECTOR_HANDOFF_INFO *VectorInfo; EFI_VECTOR_HANDOFF_INFO *VectorInfo;
VectorInfo = NULL; VectorInfo = NULL;
Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList); Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
if (Status == EFI_SUCCESS && VectorInfoList != NULL) { if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {
VectorInfo = VectorInfoList; VectorInfo = VectorInfoList;
} }
Status = InitializeCpuInterruptHandlers (VectorInfo); Status = InitializeCpuInterruptHandlers (VectorInfo);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
/** /**
Callback function for idle events. Callback function for idle events.
@@ -999,14 +1007,17 @@ IntersectMemoryDescriptor (
UINT64 IntersectionEnd; UINT64 IntersectionEnd;
EFI_STATUS Status; EFI_STATUS Status;
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo && if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&
(Descriptor->Capabilities & Capabilities) == Capabilities) { ((Descriptor->Capabilities & Capabilities) == Capabilities))
{
return EFI_SUCCESS; return EFI_SUCCESS;
} }
IntersectionBase = MAX (Base, Descriptor->BaseAddress); IntersectionBase = MAX (Base, Descriptor->BaseAddress);
IntersectionEnd = MIN (Base + Length, IntersectionEnd = MIN (
Descriptor->BaseAddress + Descriptor->Length); Base + Length,
Descriptor->BaseAddress + Descriptor->Length
);
if (IntersectionBase >= IntersectionEnd) { if (IntersectionBase >= IntersectionEnd) {
// //
// The descriptor and the aperture don't overlap. // The descriptor and the aperture don't overlap.
@@ -1015,21 +1026,39 @@ IntersectMemoryDescriptor (
} }
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) { if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, Status = gDS->AddMemorySpace (
IntersectionBase, IntersectionEnd - IntersectionBase, EfiGcdMemoryTypeMemoryMappedIo,
Capabilities); IntersectionBase,
IntersectionEnd - IntersectionBase,
Capabilities
);
DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, DEBUG ((
"%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__, EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
IntersectionBase, IntersectionEnd, Status)); "%a: %a: add [%Lx, %Lx): %r\n",
gEfiCallerBaseName,
__FUNCTION__,
IntersectionBase,
IntersectionEnd,
Status
));
return Status; return Status;
} }
DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts " DEBUG ((
"with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__, DEBUG_ERROR,
Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
(UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities, "with aperture [%Lx, %Lx) cap %Lx\n",
Base, Base + Length, Capabilities)); gEfiCallerBaseName,
__FUNCTION__,
Descriptor->BaseAddress,
Descriptor->BaseAddress + Descriptor->Length,
(UINT32)Descriptor->GcdMemoryType,
Descriptor->Capabilities,
Base,
Base + Length,
Capabilities
));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -1058,14 +1087,23 @@ AddMemoryMappedIoSpace (
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n", DEBUG ((
gEfiCallerBaseName, __FUNCTION__, Status)); DEBUG_ERROR,
"%a: %a: GetMemorySpaceMap(): %r\n",
gEfiCallerBaseName,
__FUNCTION__,
Status
));
return Status; return Status;
} }
for (Index = 0; Index < NumberOfDescriptors; Index++) { for (Index = 0; Index < NumberOfDescriptors; Index++) {
Status = IntersectMemoryDescriptor (Base, Length, Capabilities, Status = IntersectMemoryDescriptor (
&MemorySpaceMap[Index]); Base,
Length,
Capabilities,
&MemorySpaceMap[Index]
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
goto FreeMemorySpaceMap; goto FreeMemorySpaceMap;
} }
@@ -1083,12 +1121,14 @@ AddMemoryMappedIoSpace (
for (CheckBase = Base; for (CheckBase = Base;
CheckBase < Base + Length; CheckBase < Base + Length;
CheckBase = Descriptor.BaseAddress + Descriptor.Length) { CheckBase = Descriptor.BaseAddress + Descriptor.Length)
{
CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor); CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
ASSERT_EFI_ERROR (CheckStatus); ASSERT_EFI_ERROR (CheckStatus);
ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo); ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities); ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
} }
DEBUG_CODE_END (); DEBUG_CODE_END ();
FreeMemorySpaceMap: FreeMemorySpaceMap:
@@ -1111,7 +1151,7 @@ AddLocalApicMemorySpace (
EFI_STATUS Status; EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS BaseAddress; EFI_PHYSICAL_ADDRESS BaseAddress;
BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress(); BaseAddress = (EFI_PHYSICAL_ADDRESS)GetLocalApicBaseAddress ();
Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC); Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -1130,8 +1170,13 @@ AddLocalApicMemorySpace (
NULL NULL
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n", DEBUG ((
gEfiCallerBaseName, __FUNCTION__, Status)); DEBUG_INFO,
"%a: %a: AllocateMemorySpace() Status - %r\n",
gEfiCallerBaseName,
__FUNCTION__,
Status
));
} }
} }
@@ -1156,7 +1201,7 @@ InitializeCpu (
EFI_STATUS Status; EFI_STATUS Status;
EFI_EVENT IdleLoopEvent; EFI_EVENT IdleLoopEvent;
InitializePageTableLib(); InitializePageTableLib ();
InitializeFloatingPointUnits (); InitializeFloatingPointUnits ();
@@ -1180,7 +1225,8 @@ InitializeCpu (
// //
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&mCpuHandle, &mCpuHandle,
&gEfiCpuArchProtocolGuid, &gCpu, &gEfiCpuArchProtocolGuid,
&gCpu,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

1
UefiCpuPkg/CpuDxe/CpuDxe.h
View File

@@ -297,4 +297,3 @@ extern BOOLEAN mIsAllocatingPageTable;
extern UINTN mNumberOfProcessors; extern UINTN mNumberOfProcessors;
#endif #endif

6
UefiCpuPkg/CpuDxe/CpuGdt.c
View File

@@ -143,7 +143,7 @@ InitGlobalDescriptorTable (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
ASSERT ((Memory != 0) && (Memory < SIZE_4GB)); ASSERT ((Memory != 0) && (Memory < SIZE_4GB));
Gdt = (GDT_ENTRIES *) (UINTN) Memory; Gdt = (GDT_ENTRIES *)(UINTN)Memory;
// //
// Initialize all GDT entries // Initialize all GDT entries
@@ -153,8 +153,8 @@ InitGlobalDescriptorTable (
// //
// Write GDT register // Write GDT register
// //
Gdtr.Base = (UINT32) (UINTN) Gdt; Gdtr.Base = (UINT32)(UINTN)Gdt;
Gdtr.Limit = (UINT16) (sizeof (mGdtTemplate) - 1); Gdtr.Limit = (UINT16)(sizeof (mGdtTemplate) - 1);
AsmWriteGdtr (&Gdtr); AsmWriteGdtr (&Gdtr);
// //

5
UefiCpuPkg/CpuDxe/CpuGdt.h
View File

@@ -30,7 +30,7 @@ typedef struct _GDT_ENTRY {
} GDT_ENTRY; } GDT_ENTRY;
typedef typedef
struct _GDT_ENTRIES { struct _GDT_ENTRIES {
GDT_ENTRY Null; GDT_ENTRY Null;
GDT_ENTRY Linear; GDT_ENTRY Linear;
GDT_ENTRY LinearCode; GDT_ENTRY LinearCode;
@@ -61,8 +61,7 @@ struct _GDT_ENTRIES {
#define CPU_CODE_SEL LINEAR_CODE64_SEL #define CPU_CODE_SEL LINEAR_CODE64_SEL
#define CPU_DATA_SEL LINEAR_DATA64_SEL #define CPU_DATA_SEL LINEAR_DATA64_SEL
#else #else
#error CPU type not supported for CPU GDT initialization! #error CPU type not supported for CPU GDT initialization!
#endif #endif
#endif // _CPU_GDT_H_ #endif // _CPU_GDT_H_

19
UefiCpuPkg/CpuDxe/CpuMp.c
View File

@@ -509,7 +509,7 @@ WhoAmI (
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
) )
{ {
return MpInitLibWhoAmI (ProcessorNumber);; return MpInitLibWhoAmI (ProcessorNumber);
} }
/** /**
@@ -583,6 +583,7 @@ CollectBistDataFromHob (
BistData = CpuInstance[CpuInstanceNumber].InfoRecord.IA32HealthFlags; BistData = CpuInstance[CpuInstanceNumber].InfoRecord.IA32HealthFlags;
} }
} }
if (BistData.Uint32 != 0) { if (BistData.Uint32 != 0) {
// //
// Report Status Code that self test is failed // Report Status Code that self test is failed
@@ -681,9 +682,9 @@ InitializeMpExceptionStackSwitchHandlers (
EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV; EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV;
EssData.Ia32.InitDefaultHandlers = FALSE; EssData.Ia32.InitDefaultHandlers = FALSE;
EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList); EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);
EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber; EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber;
EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize); EssData.Ia32.KnownGoodStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
// //
// Initialize Gdtr to suppress incorrect compiler/analyzer warnings. // Initialize Gdtr to suppress incorrect compiler/analyzer warnings.
@@ -749,7 +750,7 @@ InitializeMpExceptionStackSwitchHandlers (
// //
// Make sure GDT table alignment // Make sure GDT table alignment
// //
EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR)); EssData.Ia32.GdtTable = ALIGN_POINTER (GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));
NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer); NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);
EssData.Ia32.GdtTableSize = NewGdtSize; EssData.Ia32.GdtTableSize = NewGdtSize;
@@ -758,10 +759,12 @@ InitializeMpExceptionStackSwitchHandlers (
EssData.Ia32.ExceptionTssDescSize); EssData.Ia32.ExceptionTssDescSize);
EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop; EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;
DEBUG ((DEBUG_INFO, DEBUG ((
DEBUG_INFO,
"Exception stack top[cpu%lu]: 0x%lX\n", "Exception stack top[cpu%lu]: 0x%lX\n",
(UINT64)(UINTN)Index, (UINT64)(UINTN)Index,
(UINT64)(UINTN)StackTop)); (UINT64)(UINTN)StackTop
));
if (Index == Bsp) { if (Index == Bsp) {
InitializeExceptionStackSwitchHandlers (&EssData); InitializeExceptionStackSwitchHandlers (&EssData);
@@ -841,9 +844,9 @@ InitializeMpSupport (
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&mMpServiceHandle, &mMpServiceHandle,
&gEfiMpServiceProtocolGuid, &mMpServicesTemplate, &gEfiMpServiceProtocolGuid,
&mMpServicesTemplate,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }

1
UefiCpuPkg/CpuDxe/CpuMp.h
View File

@@ -467,4 +467,3 @@ WhoAmI (
); );
#endif // _CPU_MP_H_ #endif // _CPU_MP_H_

123
UefiCpuPkg/CpuDxe/CpuPageTable.c
View File

@@ -80,9 +80,9 @@ typedef enum {
} PAGE_ACTION; } PAGE_ACTION;
PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
{Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64}, { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64 },
{Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64}, { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64 },
{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 },
}; };
PAGE_TABLE_POOL *mPageTablePool = NULL; PAGE_TABLE_POOL *mPageTablePool = NULL;
@@ -137,7 +137,7 @@ IsInSmm (
// load its own page table. // load its own page table.
// //
return (InSmm && return (InSmm &&
mPagingContext.ContextData.X64.PageTableBase != (UINT64)AsmReadCr3()); mPagingContext.ContextData.X64.PageTableBase != (UINT64)AsmReadCr3 ());
} }
/** /**
@@ -162,8 +162,8 @@ GetCurrentPagingContext (
// Don't retrieve current paging context from processor if in SMM mode. // Don't retrieve current paging context from processor if in SMM mode.
// //
if (!IsInSmm ()) { if (!IsInSmm ()) {
ZeroMem (&mPagingContext, sizeof(mPagingContext)); ZeroMem (&mPagingContext, sizeof (mPagingContext));
if (sizeof(UINTN) == sizeof(UINT64)) { if (sizeof (UINTN) == sizeof (UINT64)) {
mPagingContext.MachineType = IMAGE_FILE_MACHINE_X64; mPagingContext.MachineType = IMAGE_FILE_MACHINE_X64;
} else { } else {
mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386; mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386;
@@ -179,15 +179,19 @@ GetCurrentPagingContext (
} else { } else {
*PageTableBase = 0; *PageTableBase = 0;
} }
if (Cr0.Bits.WP != 0) { if (Cr0.Bits.WP != 0) {
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
} }
if (Cr4.Bits.PSE != 0) { if (Cr4.Bits.PSE != 0) {
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE; *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;
} }
if (Cr4.Bits.PAE != 0) { if (Cr4.Bits.PAE != 0) {
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE; *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;
} }
if (Cr4.Bits.LA57 != 0) { if (Cr4.Bits.LA57 != 0) {
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL; *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL;
} }
@@ -198,7 +202,7 @@ GetCurrentPagingContext (
if (RegEdx.Bits.NX != 0) { if (RegEdx.Bits.NX != 0) {
// XD supported // XD supported
MsrEfer.Uint64 = AsmReadMsr64(MSR_CORE_IA32_EFER); MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
if (MsrEfer.Bits.NXE != 0) { if (MsrEfer.Bits.NXE != 0) {
// XD activated // XD activated
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED; *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;
@@ -231,11 +235,13 @@ PageAttributeToLength (
) )
{ {
UINTN Index; UINTN Index;
for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) { if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].Length; return (UINTN)mPageAttributeTable[Index].Length;
} }
} }
return 0; return 0;
} }
@@ -252,11 +258,13 @@ PageAttributeToMask (
) )
{ {
UINTN Index; UINTN Index;
for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) { if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].AddressMask; return (UINTN)mPageAttributeTable[Index].AddressMask;
} }
} }
return 0; return 0;
} }
@@ -312,6 +320,7 @@ GetPageTableEntry (
} else { } else {
L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase; L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;
} }
if (L4PageTable[Index4] == 0) { if (L4PageTable[Index4] == 0) {
*PageAttribute = PageNone; *PageAttribute = PageNone;
return NULL; return NULL;
@@ -319,13 +328,15 @@ GetPageTableEntry (
L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64); L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);
} else { } else {
ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0); ASSERT ((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0);
L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase; L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase;
} }
if (L3PageTable[Index3] == 0) { if (L3PageTable[Index3] == 0) {
*PageAttribute = PageNone; *PageAttribute = PageNone;
return NULL; return NULL;
} }
if ((L3PageTable[Index3] & IA32_PG_PS) != 0) { if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
// 1G // 1G
*PageAttribute = Page1G; *PageAttribute = Page1G;
@@ -337,6 +348,7 @@ GetPageTableEntry (
*PageAttribute = PageNone; *PageAttribute = PageNone;
return NULL; return NULL;
} }
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) { if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M // 2M
*PageAttribute = Page2M; *PageAttribute = Page2M;
@@ -349,6 +361,7 @@ GetPageTableEntry (
*PageAttribute = PageNone; *PageAttribute = PageNone;
return NULL; return NULL;
} }
*PageAttribute = Page4K; *PageAttribute = Page4K;
return &L1PageTable[Index1]; return &L1PageTable[Index1];
} }
@@ -366,16 +379,20 @@ GetAttributesFromPageEntry (
) )
{ {
UINT64 Attributes; UINT64 Attributes;
Attributes = 0; Attributes = 0;
if ((*PageEntry & IA32_PG_P) == 0) { if ((*PageEntry & IA32_PG_P) == 0) {
Attributes |= EFI_MEMORY_RP; Attributes |= EFI_MEMORY_RP;
} }
if ((*PageEntry & IA32_PG_RW) == 0) { if ((*PageEntry & IA32_PG_RW) == 0) {
Attributes |= EFI_MEMORY_RO; Attributes |= EFI_MEMORY_RO;
} }
if ((*PageEntry & IA32_PG_NX) != 0) { if ((*PageEntry & IA32_PG_NX) != 0) {
Attributes |= EFI_MEMORY_XP; Attributes |= EFI_MEMORY_XP;
} }
return Attributes; return Attributes;
} }
@@ -423,6 +440,7 @@ ConvertPageEntryAttribute (
break; break;
} }
} }
if ((Attributes & EFI_MEMORY_RO) != 0) { if ((Attributes & EFI_MEMORY_RO) != 0) {
switch (PageAction) { switch (PageAction) {
case PageActionAssign: case PageActionAssign:
@@ -468,6 +486,7 @@ ConvertPageEntryAttribute (
} }
} }
} }
*PageEntry = NewPageEntry; *PageEntry = NewPageEntry;
if (CurrentPageEntry != NewPageEntry) { if (CurrentPageEntry != NewPageEntry) {
*IsModified = TRUE; *IsModified = TRUE;
@@ -555,10 +574,12 @@ SplitPage (
if (NewPageEntry == NULL) { if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
BaseAddress = *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MASK_64; BaseAddress = *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MASK_64;
for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
} }
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS); (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS);
return RETURN_SUCCESS; return RETURN_SUCCESS;
} else { } else {
@@ -570,16 +591,18 @@ SplitPage (
// No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table. // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.
// //
ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K); ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);
if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) { if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) {
NewPageEntry = AllocatePagesFunc (1); NewPageEntry = AllocatePagesFunc (1);
DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry)); DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));
if (NewPageEntry == NULL) { if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
BaseAddress = *PageEntry & ~AddressEncMask & PAGING_1G_ADDRESS_MASK_64; BaseAddress = *PageEntry & ~AddressEncMask & PAGING_1G_ADDRESS_MASK_64;
for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
} }
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS); (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS);
return RETURN_SUCCESS; return RETURN_SUCCESS;
} else { } else {
@@ -603,14 +626,16 @@ IsReadOnlyPageWriteProtected (
) )
{ {
IA32_CR0 Cr0; IA32_CR0 Cr0;
// //
// To avoid unforseen consequences, don't touch paging settings in SMM mode // To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver. // in this driver.
// //
if (!IsInSmm ()) { if (!IsInSmm ()) {
Cr0.UintN = AsmReadCr0 (); Cr0.UintN = AsmReadCr0 ();
return (BOOLEAN) (Cr0.Bits.WP != 0); return (BOOLEAN)(Cr0.Bits.WP != 0);
} }
return FALSE; return FALSE;
} }
@@ -623,6 +648,7 @@ DisableReadOnlyPageWriteProtect (
) )
{ {
IA32_CR0 Cr0; IA32_CR0 Cr0;
// //
// To avoid unforseen consequences, don't touch paging settings in SMM mode // To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver. // in this driver.
@@ -643,6 +669,7 @@ EnableReadOnlyPageWriteProtect (
) )
{ {
IA32_CR0 Cr0; IA32_CR0 Cr0;
// //
// To avoid unforseen consequences, don't touch paging settings in SMM mode // To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver. // in this driver.
@@ -708,10 +735,12 @@ ConvertMemoryPageAttributes (
DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddress)); DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddress));
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if ((Length & (SIZE_4KB - 1)) != 0) { if ((Length & (SIZE_4KB - 1)) != 0) {
DEBUG ((DEBUG_ERROR, "Length(0x%lx) is not aligned!\n", Length)); DEBUG ((DEBUG_ERROR, "Length(0x%lx) is not aligned!\n", Length));
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (Length == 0) { if (Length == 0) {
DEBUG ((DEBUG_ERROR, "Length is 0!\n")); DEBUG ((DEBUG_ERROR, "Length is 0!\n"));
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
@@ -725,9 +754,10 @@ ConvertMemoryPageAttributes (
if (PagingContext == NULL) { if (PagingContext == NULL) {
GetCurrentPagingContext (&CurrentPagingContext); GetCurrentPagingContext (&CurrentPagingContext);
} else { } else {
CopyMem (&CurrentPagingContext, PagingContext, sizeof(CurrentPagingContext)); CopyMem (&CurrentPagingContext, PagingContext, sizeof (CurrentPagingContext));
} }
switch(CurrentPagingContext.MachineType) {
switch (CurrentPagingContext.MachineType) {
case IMAGE_FILE_MACHINE_I386: case IMAGE_FILE_MACHINE_I386:
if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) { if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) {
if (Attributes == 0) { if (Attributes == 0) {
@@ -737,32 +767,37 @@ ConvertMemoryPageAttributes (
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
} }
if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) { if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) {
DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n")); DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n"));
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if ((BaseAddress + Length) > BASE_4GB) { if ((BaseAddress + Length) > BASE_4GB) {
DEBUG ((DEBUG_ERROR, "Beyond 4GB memory in 32-bit mode!\n")); DEBUG ((DEBUG_ERROR, "Beyond 4GB memory in 32-bit mode!\n"));
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
break; break;
case IMAGE_FILE_MACHINE_X64: case IMAGE_FILE_MACHINE_X64:
ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0); ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0);
break; break;
default: default:
ASSERT(FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
break; break;
} }
// DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes)); // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));
if (IsSplitted != NULL) { if (IsSplitted != NULL) {
*IsSplitted = FALSE; *IsSplitted = FALSE;
} }
if (IsModified != NULL) { if (IsModified != NULL) {
*IsModified = FALSE; *IsModified = FALSE;
} }
if (AllocatePagesFunc == NULL) { if (AllocatePagesFunc == NULL) {
AllocatePagesFunc = AllocatePageTableMemory; AllocatePagesFunc = AllocatePageTableMemory;
} }
@@ -785,6 +820,7 @@ ConvertMemoryPageAttributes (
Status = RETURN_UNSUPPORTED; Status = RETURN_UNSUPPORTED;
goto Done; goto Done;
} }
PageEntryLength = PageAttributeToLength (PageAttribute); PageEntryLength = PageAttributeToLength (PageAttribute);
SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute); SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);
if (SplitAttribute == PageNone) { if (SplitAttribute == PageNone) {
@@ -794,6 +830,7 @@ ConvertMemoryPageAttributes (
*IsModified = TRUE; *IsModified = TRUE;
} }
} }
// //
// Convert success, move to next // Convert success, move to next
// //
@@ -804,17 +841,21 @@ ConvertMemoryPageAttributes (
Status = RETURN_UNSUPPORTED; Status = RETURN_UNSUPPORTED;
goto Done; goto Done;
} }
Status = SplitPage (PageEntry, PageAttribute, SplitAttribute, AllocatePagesFunc); Status = SplitPage (PageEntry, PageAttribute, SplitAttribute, AllocatePagesFunc);
if (RETURN_ERROR (Status)) { if (RETURN_ERROR (Status)) {
Status = RETURN_UNSUPPORTED; Status = RETURN_UNSUPPORTED;
goto Done; goto Done;
} }
if (IsSplitted != NULL) { if (IsSplitted != NULL) {
*IsSplitted = TRUE; *IsSplitted = TRUE;
} }
if (IsModified != NULL) { if (IsModified != NULL) {
*IsModified = TRUE; *IsModified = TRUE;
} }
// //
// Just split current page // Just split current page
// Convert success in next around // Convert success in next around
@@ -829,6 +870,7 @@ Done:
if (IsWpEnabled) { if (IsWpEnabled) {
EnableReadOnlyPageWriteProtect (); EnableReadOnlyPageWriteProtect ();
} }
return Status; return Status;
} }
@@ -874,9 +916,9 @@ AssignMemoryPageAttributes (
BOOLEAN IsModified; BOOLEAN IsModified;
BOOLEAN IsSplitted; BOOLEAN IsSplitted;
// DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\n", BaseAddress, Length, Attributes)); // DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\n", BaseAddress, Length, Attributes));
Status = ConvertMemoryPageAttributes (PagingContext, BaseAddress, Length, Attributes, PageActionAssign, AllocatePagesFunc, &IsSplitted, &IsModified); Status = ConvertMemoryPageAttributes (PagingContext, BaseAddress, Length, Attributes, PageActionAssign, AllocatePagesFunc, &IsSplitted, &IsModified);
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
if ((PagingContext == NULL) && IsModified) { if ((PagingContext == NULL) && IsModified) {
// //
// Flush TLB as last step. // Flush TLB as last step.
@@ -885,7 +927,7 @@ AssignMemoryPageAttributes (
// TLB flush in MWAIT loop mode, there's no need to flush TLB for them // TLB flush in MWAIT loop mode, there's no need to flush TLB for them
// here. // here.
// //
CpuFlushTlb(); CpuFlushTlb ();
} }
} }
@@ -975,7 +1017,8 @@ RefreshGcdMemoryAttributesFromPaging (
DEBUG (( DEBUG ((
DEBUG_WARN, DEBUG_WARN,
"Failed to update capability: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n", "Failed to update capability: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n",
(UINT64)Index, MemorySpaceMap[Index].BaseAddress, (UINT64)Index,
MemorySpaceMap[Index].BaseAddress,
MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - 1, MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - 1,
MemorySpaceMap[Index].Capabilities, MemorySpaceMap[Index].Capabilities,
MemorySpaceMap[Index].Capabilities | Capabilities MemorySpaceMap[Index].Capabilities | Capabilities
@@ -1011,14 +1054,15 @@ RefreshGcdMemoryAttributesFromPaging (
// //
// Note current memory space might start in the middle of a page // Note current memory space might start in the middle of a page
// //
PageStartAddress = (*PageEntry) & (UINT64)PageAttributeToMask(PageAttribute); PageStartAddress = (*PageEntry) & (UINT64)PageAttributeToMask (PageAttribute);
PageLength = PageAttributeToLength (PageAttribute) - (BaseAddress - PageStartAddress); PageLength = PageAttributeToLength (PageAttribute) - (BaseAddress - PageStartAddress);
Attributes = GetAttributesFromPageEntry (PageEntry); Attributes = GetAttributesFromPageEntry (PageEntry);
} }
Length = MIN (PageLength, MemorySpaceLength); Length = MIN (PageLength, MemorySpaceLength);
if (Attributes != (MemorySpaceMap[Index].Attributes & if (Attributes != (MemorySpaceMap[Index].Attributes &
EFI_MEMORY_ATTRIBUTE_MASK)) { EFI_MEMORY_ATTRIBUTE_MASK))
{
NewAttributes = (MemorySpaceMap[Index].Attributes & NewAttributes = (MemorySpaceMap[Index].Attributes &
~EFI_MEMORY_ATTRIBUTE_MASK) | Attributes; ~EFI_MEMORY_ATTRIBUTE_MASK) | Attributes;
Status = gDS->SetMemorySpaceAttributes ( Status = gDS->SetMemorySpaceAttributes (
@@ -1030,7 +1074,9 @@ RefreshGcdMemoryAttributesFromPaging (
DEBUG (( DEBUG ((
DEBUG_VERBOSE, DEBUG_VERBOSE,
"Updated memory space attribute: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n", "Updated memory space attribute: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n",
(UINT64)Index, BaseAddress, BaseAddress + Length - 1, (UINT64)Index,
BaseAddress,
BaseAddress + Length - 1,
MemorySpaceMap[Index].Attributes, MemorySpaceMap[Index].Attributes,
NewAttributes NewAttributes
)); ));
@@ -1169,8 +1215,9 @@ AllocatePageTableMemory (
// //
// Renew the pool if necessary. // Renew the pool if necessary.
// //
if (mPageTablePool == NULL || if ((mPageTablePool == NULL) ||
Pages > mPageTablePool->FreePages) { (Pages > mPageTablePool->FreePages))
{
if (!InitializePageTablePool (Pages)) { if (!InitializePageTablePool (Pages)) {
return NULL; return NULL;
} }
@@ -1238,9 +1285,9 @@ DebugExceptionHandler (
// Clear TF in EFLAGS // Clear TF in EFLAGS
// //
if (mPagingContext.MachineType == IMAGE_FILE_MACHINE_I386) { if (mPagingContext.MachineType == IMAGE_FILE_MACHINE_I386) {
SystemContext.SystemContextIa32->Eflags &= (UINT32)~BIT8; SystemContext.SystemContextIa32->Eflags &= (UINT32) ~BIT8;
} else { } else {
SystemContext.SystemContextX64->Rflags &= (UINT64)~BIT8; SystemContext.SystemContextX64->Rflags &= (UINT64) ~BIT8;
} }
} }
@@ -1289,15 +1336,20 @@ PageFaultExceptionHandler (
PageNumber = 2; PageNumber = 2;
while (PageNumber > 0) { while (PageNumber > 0) {
PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute); PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute);
ASSERT(PageEntry != NULL); ASSERT (PageEntry != NULL);
if (PageEntry != NULL) { if (PageEntry != NULL) {
Attributes = GetAttributesFromPageEntry (PageEntry); Attributes = GetAttributesFromPageEntry (PageEntry);
if ((Attributes & EFI_MEMORY_RP) != 0) { if ((Attributes & EFI_MEMORY_RP) != 0) {
Attributes &= ~EFI_MEMORY_RP; Attributes &= ~EFI_MEMORY_RP;
Status = AssignMemoryPageAttributes (&PagingContext, PFAddress, Status = AssignMemoryPageAttributes (
EFI_PAGE_SIZE, Attributes, NULL); &PagingContext,
if (!EFI_ERROR(Status)) { PFAddress,
EFI_PAGE_SIZE,
Attributes,
NULL
);
if (!EFI_ERROR (Status)) {
Index = mPFEntryCount[CpuIndex]; Index = mPFEntryCount[CpuIndex];
// //
// Re-retrieve page entry because above calling might update page // Re-retrieve page entry because above calling might update page
@@ -1357,7 +1409,8 @@ InitializePageTableLib (
// Reserve memory of page tables for future uses, if paging is enabled. // Reserve memory of page tables for future uses, if paging is enabled.
// //
if ((*PageTableBase != 0) && if ((*PageTableBase != 0) &&
(*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0) { ((*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0))
{
DisableReadOnlyPageWriteProtect (); DisableReadOnlyPageWriteProtect ();
InitializePageTablePool (1); InitializePageTablePool (1);
EnableReadOnlyPageWriteProtect (); EnableReadOnlyPageWriteProtect ();
@@ -1377,5 +1430,5 @@ InitializePageTableLib (
DEBUG ((DEBUG_INFO, " PageTableBase - 0x%Lx\n", (UINT64)*PageTableBase)); DEBUG ((DEBUG_INFO, " PageTableBase - 0x%Lx\n", (UINT64)*PageTableBase));
DEBUG ((DEBUG_INFO, " Attributes - 0x%x\n", *Attributes)); DEBUG ((DEBUG_INFO, " Attributes - 0x%x\n", *Attributes));
return ; return;
} }

3
UefiCpuPkg/CpuDxe/CpuPageTable.h
View File

@@ -57,7 +57,6 @@ typedef struct {
UINTN FreePages; UINTN FreePages;
} PAGE_TABLE_POOL; } PAGE_TABLE_POOL;
/** /**
Allocates one or more 4KB pages for page table. Allocates one or more 4KB pages for page table.
@@ -68,7 +67,7 @@ typedef struct {
**/ **/
typedef typedef
VOID * VOID *
(EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES) ( (EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES)(
IN UINTN Pages IN UINTN Pages
); );

3
UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c
View File

@@ -8,7 +8,6 @@
#include "CpuPageTable.h" #include "CpuPageTable.h"
/** /**
Get paging details. Get paging details.
@@ -27,8 +26,8 @@ GetPagingDetails (
if (PageTableBase != NULL) { if (PageTableBase != NULL) {
*PageTableBase = &PagingContextData->Ia32.PageTableBase; *PageTableBase = &PagingContextData->Ia32.PageTableBase;
} }
if (Attributes != NULL) { if (Attributes != NULL) {
*Attributes = &PagingContextData->Ia32.Attributes; *Attributes = &PagingContextData->Ia32.Attributes;
} }
} }

3
UefiCpuPkg/CpuDxe/X64/PagingAttribute.c
View File

@@ -8,7 +8,6 @@
#include "CpuPageTable.h" #include "CpuPageTable.h"
/** /**
Get paging details. Get paging details.
@@ -27,8 +26,8 @@ GetPagingDetails (
if (PageTableBase != NULL) { if (PageTableBase != NULL) {
*PageTableBase = &PagingContextData->X64.PageTableBase; *PageTableBase = &PagingContextData->X64.PageTableBase;
} }
if (Attributes != NULL) { if (Attributes != NULL) {
*Attributes = &PagingContextData->X64.Attributes; *Attributes = &PagingContextData->X64.Attributes;
} }
} }

2
UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
View File

@@ -18,7 +18,6 @@
#include <Protocol/SmmConfiguration.h> #include <Protocol/SmmConfiguration.h>
#include <Guid/CpuFeaturesInitDone.h> #include <Guid/CpuFeaturesInitDone.h>
/** /**
Worker function to perform CPU feature initialization. Worker function to perform CPU feature initialization.
@@ -133,4 +132,3 @@ CpuFeaturesDxeInitialize (
return EFI_SUCCESS; return EFI_SUCCESS;
} }

8
UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c
View File

@@ -46,8 +46,9 @@ CpuFeaturesPeimInitialize (
Status = PeiServicesGetBootMode (&BootMode); Status = PeiServicesGetBootMode (&BootMode);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
if (BootMode == BOOT_ON_S3_RESUME && if ((BootMode == BOOT_ON_S3_RESUME) &&
!PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) { !PcdGetBool (PcdCpuFeaturesInitOnS3Resume))
{
// //
// Does nothing when if PcdCpuFeaturesInitOnS3Resume is FLASE // Does nothing when if PcdCpuFeaturesInitOnS3Resume is FLASE
// on S3 boot mode // on S3 boot mode
@@ -62,7 +63,7 @@ CpuFeaturesPeimInitialize (
// //
// Install CPU Features Init Done PPI // Install CPU Features Init Done PPI
// //
Status = PeiServicesInstallPpi(&mPeiCpuFeaturesInitDonePpiDesc); Status = PeiServicesInstallPpi (&mPeiCpuFeaturesInitDonePpiDesc);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// //
@@ -72,4 +73,3 @@ CpuFeaturesPeimInitialize (
return EFI_SUCCESS; return EFI_SUCCESS;
} }

18
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
View File

@@ -120,14 +120,14 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access, // For FIFO type, the target address won't increase during the access,
// so treat Count as 1 // so treat Count as 1
// //
if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) { if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
Count = 1; Count = 1;
} }
// //
// Check to see if Width is in the valid range for I/O Port operations // Check to see if Width is in the valid range for I/O Port operations
// //
Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) { if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -164,6 +164,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) { if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@@ -245,7 +246,7 @@ CpuMemoryServiceRead (
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) { if (OperationWidth == EfiCpuIoWidthUint8) {
*Uint8Buffer = MmioRead8 ((UINTN)Address); *Uint8Buffer = MmioRead8 ((UINTN)Address);
@@ -257,6 +258,7 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -325,7 +327,7 @@ CpuMemoryServiceWrite (
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) { if (OperationWidth == EfiCpuIoWidthUint8) {
MmioWrite8 ((UINTN)Address, *Uint8Buffer); MmioWrite8 ((UINTN)Address, *Uint8Buffer);
@@ -337,6 +339,7 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -405,7 +408,7 @@ CpuIoServiceRead (
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
// //
// Fifo operations supported for (mInStride[Width] == 0) // Fifo operations supported for (mInStride[Width] == 0)
@@ -512,7 +515,7 @@ CpuIoServiceWrite (
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
// //
// Fifo operations supported for (mInStride[Width] == 0) // Fifo operations supported for (mInStride[Width] == 0)
@@ -573,7 +576,8 @@ CpuIo2Initialize (
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&mHandle, &mHandle,
&gEfiCpuIo2ProtocolGuid, &mCpuIo2, &gEfiCpuIo2ProtocolGuid,
&mCpuIo2,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

3
UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c
View File

@@ -112,6 +112,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) { if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@@ -184,6 +185,7 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -244,6 +246,7 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }

15
UefiCpuPkg/CpuIoPei/CpuIoPei.c
View File

@@ -131,14 +131,14 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access, // For FIFO type, the target address won't increase during the access,
// so treat Count as 1 // so treat Count as 1
// //
if (Width >= EfiPeiCpuIoWidthFifoUint8 && Width <= EfiPeiCpuIoWidthFifoUint64) { if ((Width >= EfiPeiCpuIoWidthFifoUint8) && (Width <= EfiPeiCpuIoWidthFifoUint64)) {
Count = 1; Count = 1;
} }
// //
// Check to see if Width is in the valid range for I/O Port operations // Check to see if Width is in the valid range for I/O Port operations
// //
Width = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); Width = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
if (!MmioOperation && (Width == EfiPeiCpuIoWidthUint64)) { if (!MmioOperation && (Width == EfiPeiCpuIoWidthUint64)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -168,6 +168,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) { if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@@ -222,7 +223,7 @@ CpuMemoryServiceRead (
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00); Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiPeiCpuIoWidthUint8) { if (OperationWidth == EfiPeiCpuIoWidthUint8) {
@@ -247,6 +248,7 @@ CpuMemoryServiceRead (
} }
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -296,7 +298,7 @@ CpuMemoryServiceWrite (
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00); Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiPeiCpuIoWidthUint8) { if (OperationWidth == EfiPeiCpuIoWidthUint8) {
@@ -321,6 +323,7 @@ CpuMemoryServiceWrite (
} }
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -370,7 +373,7 @@ CpuIoServiceRead (
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
// //
// Fifo operations supported for (mInStride[Width] == 0) // Fifo operations supported for (mInStride[Width] == 0)
@@ -467,7 +470,7 @@ CpuIoServiceWrite (
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
// //
// Fifo operations supported for (mInStride[Width] == 0) // Fifo operations supported for (mInStride[Width] == 0)

41
UefiCpuPkg/CpuMpPei/CpuBist.c
View File

@@ -54,12 +54,12 @@ SecPlatformInformation2 (
// //
// return the information from BistHob // return the information from BistHob
// //
if ((*StructureSize) < (UINT64) DataSize) { if ((*StructureSize) < (UINT64)DataSize) {
*StructureSize = (UINT64) DataSize; *StructureSize = (UINT64)DataSize;
return EFI_BUFFER_TOO_SMALL; return EFI_BUFFER_TOO_SMALL;
} }
*StructureSize = (UINT64) DataSize; *StructureSize = (UINT64)DataSize;
CopyMem (PlatformInformationRecord2, DataInHob, DataSize); CopyMem (PlatformInformationRecord2, DataInHob, DataSize);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -117,8 +117,8 @@ GetBistInfoFromPpi (
); );
if (Status == EFI_BUFFER_TOO_SMALL) { if (Status == EFI_BUFFER_TOO_SMALL) {
Status = PeiServicesAllocatePool ( Status = PeiServicesAllocatePool (
(UINTN) InformationSize, (UINTN)InformationSize,
(VOID **) &SecPlatformInformation2 (VOID **)&SecPlatformInformation2
); );
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
// //
@@ -134,6 +134,7 @@ GetBistInfoFromPpi (
if (BistInformationSize != NULL) { if (BistInformationSize != NULL) {
*BistInformationSize = InformationSize; *BistInformationSize = InformationSize;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
@@ -174,14 +175,13 @@ CollectBistDataFromPpi (
EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2; EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2;
EFI_SEC_PLATFORM_INFORMATION_CPU *CpuInstanceInHob; EFI_SEC_PLATFORM_INFORMATION_CPU *CpuInstanceInHob;
MpInitLibGetNumberOfProcessors (&NumberOfProcessors, &NumberOfEnabledProcessors);
MpInitLibGetNumberOfProcessors(&NumberOfProcessors, &NumberOfEnabledProcessors);
BistInformationSize = sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2) + BistInformationSize = sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2) +
sizeof (EFI_SEC_PLATFORM_INFORMATION_CPU) * NumberOfProcessors; sizeof (EFI_SEC_PLATFORM_INFORMATION_CPU) * NumberOfProcessors;
Status = PeiServicesAllocatePool ( Status = PeiServicesAllocatePool (
(UINTN) BistInformationSize, (UINTN)BistInformationSize,
(VOID **) &PlatformInformationRecord2 (VOID **)&PlatformInformationRecord2
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
PlatformInformationRecord2->NumberOfCpus = (UINT32)NumberOfProcessors; PlatformInformationRecord2->NumberOfCpus = (UINT32)NumberOfProcessors;
@@ -197,7 +197,7 @@ CollectBistDataFromPpi (
PeiServices, PeiServices,
&gEfiSecPlatformInformation2PpiGuid, &gEfiSecPlatformInformation2PpiGuid,
&SecInformationDescriptor, &SecInformationDescriptor,
(VOID *) &SecPlatformInformation2, (VOID *)&SecPlatformInformation2,
NULL NULL
); );
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
@@ -214,7 +214,7 @@ CollectBistDataFromPpi (
PeiServices, PeiServices,
&gEfiSecPlatformInformationPpiGuid, &gEfiSecPlatformInformationPpiGuid,
&SecInformationDescriptor, &SecInformationDescriptor,
(VOID *) &SecPlatformInformation, (VOID *)&SecPlatformInformation,
NULL NULL
); );
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
@@ -230,9 +230,10 @@ CollectBistDataFromPpi (
DEBUG ((DEBUG_INFO, "Does not find any stored CPU BIST information from PPI!\n")); DEBUG ((DEBUG_INFO, "Does not find any stored CPU BIST information from PPI!\n"));
} }
} }
for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber ++) {
for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber++) {
MpInitLibGetProcessorInfo (ProcessorNumber, &ProcessorInfo, &BistData); MpInitLibGetProcessorInfo (ProcessorNumber, &ProcessorInfo, &BistData);
for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex ++) { for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex++) {
ASSERT (CpuInstance != NULL); ASSERT (CpuInstance != NULL);
if (ProcessorInfo.ProcessorId == CpuInstance[CpuIndex].CpuLocation) { if (ProcessorInfo.ProcessorId == CpuInstance[CpuIndex].CpuLocation) {
// //
@@ -241,6 +242,7 @@ CollectBistDataFromPpi (
BistData = CpuInstance[CpuIndex].InfoRecord.IA32HealthFlags; BistData = CpuInstance[CpuIndex].InfoRecord.IA32HealthFlags;
} }
} }
if (BistData.Uint32 != 0) { if (BistData.Uint32 != 0) {
// //
// Report Status Code that self test is failed // Report Status Code that self test is failed
@@ -250,12 +252,15 @@ CollectBistDataFromPpi (
(EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST) (EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST)
); );
} }
DEBUG ((DEBUG_INFO, " APICID - 0x%08x, BIST - 0x%08x\n",
(UINT32) ProcessorInfo.ProcessorId, DEBUG ((
DEBUG_INFO,
" APICID - 0x%08x, BIST - 0x%08x\n",
(UINT32)ProcessorInfo.ProcessorId,
BistData BistData
)); ));
CpuInstanceInHob = PlatformInformationRecord2->CpuInstance; CpuInstanceInHob = PlatformInformationRecord2->CpuInstance;
CpuInstanceInHob[ProcessorNumber].CpuLocation = (UINT32) ProcessorInfo.ProcessorId; CpuInstanceInHob[ProcessorNumber].CpuLocation = (UINT32)ProcessorInfo.ProcessorId;
CpuInstanceInHob[ProcessorNumber].InfoRecord.IA32HealthFlags = BistData; CpuInstanceInHob[ProcessorNumber].InfoRecord.IA32HealthFlags = BistData;
} }
@@ -266,7 +271,7 @@ CollectBistDataFromPpi (
BuildGuidDataHob ( BuildGuidDataHob (
&gEfiSecPlatformInformation2PpiGuid, &gEfiSecPlatformInformation2PpiGuid,
PlatformInformationRecord2, PlatformInformationRecord2,
(UINTN) BistInformationSize (UINTN)BistInformationSize
); );
if (SecPlatformInformation2 != NULL) { if (SecPlatformInformation2 != NULL) {
@@ -285,6 +290,6 @@ CollectBistDataFromPpi (
// Install SecPlatformInformation2 PPI // Install SecPlatformInformation2 PPI
// //
Status = PeiServicesInstallPpi (&mPeiSecPlatformInformation2Ppi); Status = PeiServicesInstallPpi (&mPeiSecPlatformInformation2Ppi);
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR (Status);
} }
} }

1
UefiCpuPkg/CpuMpPei/CpuMp2Pei.c
View File

@@ -414,4 +414,3 @@ EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi = {
EdkiiPeiWhoAmI, EdkiiPeiWhoAmI,
EdkiiPeiStartupAllCPUs EdkiiPeiStartupAllCPUs
}; };

21
UefiCpuPkg/CpuMpPei/CpuMpPei.c
View File

@@ -489,17 +489,18 @@ InitializeMpExceptionStackSwitchHandlers (
return; return;
} }
MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL); MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);
MpInitLibWhoAmI (&Bsp); MpInitLibWhoAmI (&Bsp);
ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList); ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);
NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber; NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;
StackTop = AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfProcessors)); StackTop = AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfProcessors));
ASSERT(StackTop != NULL); ASSERT (StackTop != NULL);
if (StackTop == NULL) { if (StackTop == NULL) {
return; return;
} }
StackTop += NewStackSize * NumberOfProcessors; StackTop += NewStackSize * NumberOfProcessors;
// //
@@ -509,9 +510,9 @@ InitializeMpExceptionStackSwitchHandlers (
EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV; EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV;
EssData.Ia32.InitDefaultHandlers = FALSE; EssData.Ia32.InitDefaultHandlers = FALSE;
EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList); EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);
EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber; EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber;
EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize); EssData.Ia32.KnownGoodStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
// //
// Initialize Gdtr to suppress incorrect compiler/analyzer warnings. // Initialize Gdtr to suppress incorrect compiler/analyzer warnings.
@@ -523,7 +524,7 @@ InitializeMpExceptionStackSwitchHandlers (
// To support stack switch, we need to re-construct GDT but not IDT. // To support stack switch, we need to re-construct GDT but not IDT.
// //
if (Index == Bsp) { if (Index == Bsp) {
GetGdtr(&Gdtr); GetGdtr (&Gdtr);
} else { } else {
// //
// AP might have different size of GDT from BSP. // AP might have different size of GDT from BSP.
@@ -583,7 +584,7 @@ InitializeMpExceptionStackSwitchHandlers (
// //
// Make sure GDT table alignment // Make sure GDT table alignment
// //
EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR)); EssData.Ia32.GdtTable = ALIGN_POINTER (GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));
NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer); NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);
EssData.Ia32.GdtTableSize = NewGdtSize; EssData.Ia32.GdtTableSize = NewGdtSize;
@@ -592,10 +593,12 @@ InitializeMpExceptionStackSwitchHandlers (
EssData.Ia32.ExceptionTssDescSize); EssData.Ia32.ExceptionTssDescSize);
EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop; EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;
DEBUG ((DEBUG_INFO, DEBUG ((
DEBUG_INFO,
"Exception stack top[cpu%lu]: 0x%lX\n", "Exception stack top[cpu%lu]: 0x%lX\n",
(UINT64)(UINTN)Index, (UINT64)(UINTN)Index,
(UINT64)(UINTN)StackTop)); (UINT64)(UINTN)StackTop
));
if (Index == Bsp) { if (Index == Bsp) {
InitializeExceptionStackSwitchHandlers (&EssData); InitializeExceptionStackSwitchHandlers (&EssData);
@@ -672,7 +675,7 @@ InitializeCpuMpWorker (
// //
// Install CPU MP PPI // Install CPU MP PPI
// //
Status = PeiServicesInstallPpi(mPeiCpuMpPpiList); Status = PeiServicesInstallPpi (mPeiCpuMpPpiList);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return Status; return Status;

82
UefiCpuPkg/CpuMpPei/CpuPaging.c
View File

@@ -25,7 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define IA32_PG_NX BIT63 #define IA32_PG_NX BIT63
#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P) #define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)
#define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U |\ #define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U | \
PAGE_ATTRIBUTE_BITS) PAGE_ATTRIBUTE_BITS)
#define PAGING_PAE_INDEX_MASK 0x1FF #define PAGING_PAE_INDEX_MASK 0x1FF
@@ -53,11 +53,11 @@ typedef struct {
} PAGE_ATTRIBUTE_TABLE; } PAGE_ATTRIBUTE_TABLE;
PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
{PageNone, 0, 0, 0, 0}, { PageNone, 0, 0, 0, 0 },
{Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9}, { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9 },
{Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9}, { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9 },
{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9}, { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9 },
{Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9}, { Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9 },
}; };
EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] = { EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] = {
@@ -109,9 +109,9 @@ AllocatePageTableMemory (
{ {
VOID *Address; VOID *Address;
Address = AllocatePages(Pages); Address = AllocatePages (Pages);
if (Address != NULL) { if (Address != NULL) {
ZeroMem(Address, EFI_PAGES_TO_SIZE (Pages)); ZeroMem (Address, EFI_PAGES_TO_SIZE (Pages));
} }
return Address; return Address;
@@ -131,11 +131,11 @@ GetPhysicalAddressWidth (
{ {
UINT32 RegEax; UINT32 RegEax;
if (sizeof(UINTN) == 4) { if (sizeof (UINTN) == 4) {
return 32; return 32;
} }
AsmCpuid(CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) { if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL);
RegEax &= 0xFF; RegEax &= 0xFF;
@@ -204,7 +204,7 @@ GetPageTableEntry (
// //
// Page memory? // Page memory?
// //
if ((PageTable[Index] & IA32_PG_PS) != 0 || Level == PageMin) { if (((PageTable[Index] & IA32_PG_PS) != 0) || (Level == PageMin)) {
*PageAttribute = (PAGE_ATTRIBUTE)Level; *PageAttribute = (PAGE_ATTRIBUTE)Level;
return &PageTable[Index]; return &PageTable[Index];
} }
@@ -247,7 +247,7 @@ SplitPage (
UINT64 AddressEncMask; UINT64 AddressEncMask;
PAGE_ATTRIBUTE SplitTo; PAGE_ATTRIBUTE SplitTo;
if (SplitAttribute == PageNone || SplitAttribute >= PageAttribute) { if ((SplitAttribute == PageNone) || (SplitAttribute >= PageAttribute)) {
ASSERT (SplitAttribute != PageNone); ASSERT (SplitAttribute != PageNone);
ASSERT (SplitAttribute < PageAttribute); ASSERT (SplitAttribute < PageAttribute);
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
@@ -268,7 +268,7 @@ SplitPage (
BaseAddress = *PageEntry & BaseAddress = *PageEntry &
~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
mPageAttributeTable[PageAttribute].AddressMask; mPageAttributeTable[PageAttribute].AddressMask;
for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = BaseAddress | AddressEncMask | NewPageEntry[Index] = BaseAddress | AddressEncMask |
((*PageEntry) & PAGE_PROGATE_BITS); ((*PageEntry) & PAGE_PROGATE_BITS);
@@ -276,7 +276,7 @@ SplitPage (
NewPageEntry[Index] |= IA32_PG_PS; NewPageEntry[Index] |= IA32_PG_PS;
} }
if (Recursively && SplitTo > SplitAttribute) { if (Recursively && (SplitTo > SplitAttribute)) {
SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively); SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively);
} }
@@ -323,10 +323,10 @@ ConvertMemoryPageAttributes (
RETURN_STATUS Status; RETURN_STATUS Status;
EFI_PHYSICAL_ADDRESS MaximumAddress; EFI_PHYSICAL_ADDRESS MaximumAddress;
if (Length == 0 || if ((Length == 0) ||
(BaseAddress & (SIZE_4KB - 1)) != 0 || ((BaseAddress & (SIZE_4KB - 1)) != 0) ||
(Length & (SIZE_4KB - 1)) != 0) { ((Length & (SIZE_4KB - 1)) != 0))
{
ASSERT (Length > 0); ASSERT (Length > 0);
ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0); ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
ASSERT ((Length & (SIZE_4KB - 1)) == 0); ASSERT ((Length & (SIZE_4KB - 1)) == 0);
@@ -335,9 +335,10 @@ ConvertMemoryPageAttributes (
} }
MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32; MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32;
if (BaseAddress > MaximumAddress || if ((BaseAddress > MaximumAddress) ||
Length > MaximumAddress || (Length > MaximumAddress) ||
(BaseAddress > MaximumAddress - (Length - 1))) { (BaseAddress > MaximumAddress - (Length - 1)))
{
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
@@ -355,6 +356,7 @@ ConvertMemoryPageAttributes (
if (RETURN_ERROR (Status)) { if (RETURN_ERROR (Status)) {
return Status; return Status;
} }
// //
// Do it again until the page is 4K. // Do it again until the page is 4K.
// //
@@ -437,7 +439,7 @@ CreatePageTable (
NumberOfEntries = (UINTN)1 << (PhysicalAddressBits - NumberOfEntries = (UINTN)1 << (PhysicalAddressBits -
mPageAttributeTable[TopLevelPageAttr].AddressBitOffset); mPageAttributeTable[TopLevelPageAttr].AddressBitOffset);
PageTable = (UINTN) AllocatePageTableMemory (1); PageTable = (UINTN)AllocatePageTableMemory (1);
if (PageTable == 0) { if (PageTable == 0) {
return 0; return 0;
} }
@@ -455,7 +457,7 @@ CreatePageTable (
// Split the top page table down to the maximum page size supported // Split the top page table down to the maximum page size supported
// //
if (MaxMemoryPage < TopLevelPageAttr) { if (MaxMemoryPage < TopLevelPageAttr) {
Status = SplitPage(PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE); Status = SplitPage (PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -470,7 +472,6 @@ CreatePageTable (
PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length; PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length;
} }
return PageTable; return PageTable;
} }
@@ -488,7 +489,7 @@ EnablePaging (
PageTable = CreatePageTable (); PageTable = CreatePageTable ();
ASSERT (PageTable != 0); ASSERT (PageTable != 0);
if (PageTable != 0) { if (PageTable != 0) {
AsmWriteCr3(PageTable); AsmWriteCr3 (PageTable);
AsmWriteCr4 (AsmReadCr4 () | BIT5); // CR4.PAE AsmWriteCr4 (AsmReadCr4 () | BIT5); // CR4.PAE
AsmWriteCr0 (AsmReadCr0 () | BIT31); // CR0.PG AsmWriteCr0 (AsmReadCr0 () | BIT31); // CR0.PG
} }
@@ -517,7 +518,7 @@ GetStackBase (
StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase; StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase;
StackBase += BASE_4KB; StackBase += BASE_4KB;
StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1); StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1);
StackBase -= PcdGet32(PcdCpuApStackSize); StackBase -= PcdGet32 (PcdCpuApStackSize);
*(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase; *(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase;
} }
@@ -541,12 +542,12 @@ SetupStackGuardPage (
// //
// One extra page at the bottom of the stack is needed for Guard page. // One extra page at the bottom of the stack is needed for Guard page.
// //
if (PcdGet32(PcdCpuApStackSize) <= EFI_PAGE_SIZE) { if (PcdGet32 (PcdCpuApStackSize) <= EFI_PAGE_SIZE) {
DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n")); DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n"));
ASSERT (FALSE); ASSERT (FALSE);
} }
MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL); MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);
MpInitLibWhoAmI (&Bsp); MpInitLibWhoAmI (&Bsp);
for (Index = 0; Index < NumberOfProcessors; ++Index) { for (Index = 0; Index < NumberOfProcessors; ++Index) {
StackBase = 0; StackBase = 0;
@@ -554,26 +555,35 @@ SetupStackGuardPage (
if (Index == Bsp) { if (Index == Bsp) {
Hob.Raw = GetHobList (); Hob.Raw = GetHobList ();
while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) { while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {
if (CompareGuid (&gEfiHobMemoryAllocStackGuid, if (CompareGuid (
&(Hob.MemoryAllocationStack->AllocDescriptor.Name))) { &gEfiHobMemoryAllocStackGuid,
&(Hob.MemoryAllocationStack->AllocDescriptor.Name)
))
{
StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress; StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress;
break; break;
} }
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
} }
} else { } else {
// //
// Ask AP to return is stack base address. // Ask AP to return is stack base address.
// //
MpInitLibStartupThisAP(GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL); MpInitLibStartupThisAP (GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);
} }
ASSERT (StackBase != 0); ASSERT (StackBase != 0);
// //
// Set Guard page at stack base address. // Set Guard page at stack base address.
// //
ConvertMemoryPageAttributes(StackBase, EFI_PAGE_SIZE, 0); ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0);
DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n", DEBUG ((
(UINT64)StackBase, (UINT64)Index)); DEBUG_INFO,
"Stack Guard set at %lx [cpu%lu]!\n",
(UINT64)StackBase,
(UINT64)Index
));
} }
// //
@@ -620,7 +630,7 @@ MemoryDiscoveredPpiNotifyCallback (
InitStackGuard = PcdGetBool (PcdCpuStackGuard); InitStackGuard = PcdGetBool (PcdCpuStackGuard);
} }
if (InitStackGuard || Hob.Raw != NULL) { if (InitStackGuard || (Hob.Raw != NULL)) {
EnablePaging (); EnablePaging ();
} }
@@ -643,8 +653,8 @@ MemoryDiscoveredPpiNotifyCallback (
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw); Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw);
} }
CpuFlushTlb (); CpuFlushTlb ();
return Status; return Status;
} }

5
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
View File

@@ -95,6 +95,7 @@ AllocateZeroPages (
return Buffer; return Buffer;
} }
/** /**
Callback function executed when the EndOfDxe event group is signaled. Callback function executed when the EndOfDxe event group is signaled.
@@ -113,7 +114,7 @@ CpuS3DataOnEndOfDxe (
EFI_STATUS Status; EFI_STATUS Status;
ACPI_CPU_DATA_EX *AcpiCpuDataEx; ACPI_CPU_DATA_EX *AcpiCpuDataEx;
AcpiCpuDataEx = (ACPI_CPU_DATA_EX *) Context; AcpiCpuDataEx = (ACPI_CPU_DATA_EX *)Context;
// //
// Allocate a 4KB reserved page below 1MB // Allocate a 4KB reserved page below 1MB
// //
@@ -179,7 +180,7 @@ CpuS3DataInitialize (
// //
// Set PcdCpuS3DataAddress to the base address of the ACPI_CPU_DATA structure // Set PcdCpuS3DataAddress to the base address of the ACPI_CPU_DATA structure
// //
OldAcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress); OldAcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
AcpiCpuDataEx = AllocateZeroPages (sizeof (ACPI_CPU_DATA_EX)); AcpiCpuDataEx = AllocateZeroPages (sizeof (ACPI_CPU_DATA_EX));
ASSERT (AcpiCpuDataEx != NULL); ASSERT (AcpiCpuDataEx != NULL);

2
UefiCpuPkg/Include/Library/LocalApicLib.h
View File

@@ -453,5 +453,5 @@ GetProcessorLocation2ByApicId (
OUT UINT32 *Core OPTIONAL, OUT UINT32 *Core OPTIONAL,
OUT UINT32 *Thread OPTIONAL OUT UINT32 *Thread OPTIONAL
); );
#endif
#endif

9
UefiCpuPkg/Include/Library/MtrrLib.h
View File

@@ -168,7 +168,6 @@ MtrrSetMemoryAttribute (
IN MTRR_MEMORY_CACHE_TYPE Attribute IN MTRR_MEMORY_CACHE_TYPE Attribute
); );
/** /**
This function will get the memory cache type of the specific address. This function will get the memory cache type of the specific address.
This function is mainly for debugging purposes. This function is mainly for debugging purposes.
@@ -184,7 +183,6 @@ MtrrGetMemoryAttribute (
IN PHYSICAL_ADDRESS Address IN PHYSICAL_ADDRESS Address
); );
/** /**
This function gets the content in fixed MTRRs This function gets the content in fixed MTRRs
@@ -193,13 +191,12 @@ MtrrGetMemoryAttribute (
@return The pointer of FixedSettings @return The pointer of FixedSettings
**/ **/
MTRR_FIXED_SETTINGS* MTRR_FIXED_SETTINGS *
EFIAPI EFIAPI
MtrrGetFixedMtrr ( MtrrGetFixedMtrr (
OUT MTRR_FIXED_SETTINGS *FixedSettings OUT MTRR_FIXED_SETTINGS *FixedSettings
); );
/** /**
This function gets the content in all MTRRs (variable and fixed) This function gets the content in all MTRRs (variable and fixed)
@@ -214,7 +211,6 @@ MtrrGetAllMtrrs (
OUT MTRR_SETTINGS *MtrrSetting OUT MTRR_SETTINGS *MtrrSetting
); );
/** /**
This function sets all MTRRs (variable and fixed) This function sets all MTRRs (variable and fixed)
@@ -229,7 +225,6 @@ MtrrSetAllMtrrs (
IN MTRR_SETTINGS *MtrrSetting IN MTRR_SETTINGS *MtrrSetting
); );
/** /**
Get the attribute of variable MTRRs. Get the attribute of variable MTRRs.
@@ -253,7 +248,6 @@ MtrrGetMemoryAttributeInVariableMtrr (
OUT VARIABLE_MTRR *VariableMtrr OUT VARIABLE_MTRR *VariableMtrr
); );
/** /**
This function prints all MTRRs for debugging. This function prints all MTRRs for debugging.
**/ **/
@@ -361,4 +355,5 @@ MtrrSetMemoryAttributesInMtrrSettings (
IN CONST MTRR_MEMORY_RANGE *Ranges, IN CONST MTRR_MEMORY_RANGE *Ranges,
IN UINTN RangeCount IN UINTN RangeCount
); );
#endif // _MTRR_LIB_H_ #endif // _MTRR_LIB_H_

2
UefiCpuPkg/Include/Library/UefiCpuLib.h
View File

@@ -13,8 +13,6 @@
#ifndef __UEFI_CPU_LIB_H__ #ifndef __UEFI_CPU_LIB_H__
#define __UEFI_CPU_LIB_H__ #define __UEFI_CPU_LIB_H__
/** /**
Initializes floating point units for requirement of UEFI specification. Initializes floating point units for requirement of UEFI specification.

1
UefiCpuPkg/Include/Library/VmgExitLib.h
View File

@@ -15,7 +15,6 @@
#include <Protocol/DebugSupport.h> #include <Protocol/DebugSupport.h>
#include <Register/Amd/Ghcb.h> #include <Register/Amd/Ghcb.h>
/** /**
Perform VMGEXIT. Perform VMGEXIT.

17
UefiCpuPkg/Include/Ppi/MpServices2.h
View File

@@ -35,7 +35,7 @@ typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI;
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) ( (EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfProcessors,
OUT UINTN *NumberOfEnabledProcessors OUT UINTN *NumberOfEnabledProcessors
@@ -57,7 +57,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO) ( (EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
@@ -97,7 +97,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS) ( (EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
@@ -139,7 +139,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP) ( (EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
@@ -171,7 +171,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP) ( (EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableOldBSP IN BOOLEAN EnableOldBSP
@@ -205,7 +205,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP) ( (EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
@@ -227,12 +227,11 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI) ( (EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
); );
/** /**
Activate all of the application proessors. Activate all of the application proessors.
@@ -256,7 +255,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS) ( (EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN TimeoutInMicroSeconds, IN UINTN TimeoutInMicroSeconds,

3
UefiCpuPkg/Include/Ppi/ShadowMicrocode.h
View File

@@ -44,7 +44,7 @@ typedef struct {
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_SHADOW_MICROCODE) ( (EFIAPI *EDKII_PEI_SHADOW_MICROCODE)(
IN EDKII_PEI_SHADOW_MICROCODE_PPI *This, IN EDKII_PEI_SHADOW_MICROCODE_PPI *This,
IN UINTN CpuIdCount, IN UINTN CpuIdCount,
IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
@@ -63,4 +63,3 @@ struct _EDKII_PEI_SHADOW_MICROCODE_PPI {
extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid; extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid;
#endif #endif

10
UefiCpuPkg/Include/Protocol/SmMonitorInit.h
View File

@@ -34,7 +34,7 @@
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR) ( (EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR)(
IN EFI_PHYSICAL_ADDRESS StmImage, IN EFI_PHYSICAL_ADDRESS StmImage,
IN UINTN StmImageSize IN UINTN StmImageSize
); );
@@ -54,7 +54,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE) ( (EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE)(
IN STM_RSC *ResourceList, IN STM_RSC *ResourceList,
IN UINT32 NumEntries OPTIONAL IN UINT32 NumEntries OPTIONAL
); );
@@ -74,7 +74,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE) ( (EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE)(
IN STM_RSC *ResourceList OPTIONAL, IN STM_RSC *ResourceList OPTIONAL,
IN UINT32 NumEntries OPTIONAL IN UINT32 NumEntries OPTIONAL
); );
@@ -94,7 +94,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE) ( (EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE)(
OUT STM_RSC *ResourceList, OUT STM_RSC *ResourceList,
IN OUT UINT32 *ResourceSize IN OUT UINT32 *ResourceSize
); );
@@ -112,7 +112,7 @@ typedef UINT32 EFI_SM_MONITOR_STATE;
**/ **/
typedef typedef
EFI_SM_MONITOR_STATE EFI_SM_MONITOR_STATE
(EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE) ( (EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE)(
VOID VOID
); );

12
UefiCpuPkg/Include/Protocol/SmmCpuService.h
View File

@@ -44,7 +44,7 @@ typedef struct _EFI_SMM_CPU_SERVICE_PROTOCOL EFI_SMM_CPU_SERVICE_PROTOCOL;
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI * EFI_SMM_GET_PROCESSOR_INFO) ( (EFIAPI *EFI_SMM_GET_PROCESSOR_INFO)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
@@ -82,7 +82,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI * EFI_SMM_SWITCH_BSP) ( (EFIAPI *EFI_SMM_SWITCH_BSP)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
); );
@@ -106,7 +106,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SMM_ADD_PROCESSOR) ( (EFIAPI *EFI_SMM_ADD_PROCESSOR)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINT64 ProcessorId, IN UINT64 ProcessorId,
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
@@ -128,7 +128,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SMM_REMOVE_PROCESSOR) ( (EFIAPI *EFI_SMM_REMOVE_PROCESSOR)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
); );
@@ -156,7 +156,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI * EFI_SMM_WHOAMI) ( (EFIAPI *EFI_SMM_WHOAMI)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
); );
@@ -180,7 +180,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER) ( (EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER)(
IN EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler

1
UefiCpuPkg/Include/Register/LocalApic.h
View File

@@ -11,4 +11,3 @@
#include <Register/Intel/LocalApic.h> #include <Register/Intel/LocalApic.h>
#endif #endif

2
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
View File

@@ -77,5 +77,5 @@ GetCpuSteppingId (
AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);
return (UINT8) Eax.Bits.SteppingId; return (UINT8)Eax.Bits.SteppingId;
} }

68
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
View File

@@ -44,13 +44,14 @@ LocalApicBaseAddressMsrSupported (
AsmCpuid (1, &RegEax, NULL, NULL, NULL); AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11); FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) { if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
// //
// CPUs with a FamilyId of 0x04 or 0x05 do not support the // CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR // Local APIC Base Address MSR
// //
return FALSE; return FALSE;
} }
return TRUE; return TRUE;
} }
@@ -78,7 +79,7 @@ GetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
} }
@@ -109,8 +110,8 @@ SetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12); ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32)); ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
} }
@@ -137,7 +138,7 @@ ReadLocalApicReg (
ASSERT ((MmioOffset & 0xf) == 0); ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset); return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
} }
/** /**
@@ -164,7 +165,7 @@ WriteLocalApicReg (
ASSERT ((MmioOffset & 0xf) == 0); ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value); MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
} }
/** /**
@@ -222,7 +223,6 @@ SendIpi (
WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh); WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState); SetInterruptState (InterruptState);
} }
// //
@@ -350,6 +350,7 @@ GetApicId (
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET); ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
ApicId >>= 24; ApicId >>= 24;
} }
return ApicId; return ApicId;
} }
@@ -521,7 +522,7 @@ SendInitSipiSipi (
ASSERT ((StartupRoutine & 0xfff) == 0); ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId); SendInitIpi (ApicId);
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
@@ -556,7 +557,7 @@ SendInitSipiSipiAllExcludingSelf (
ASSERT ((StartupRoutine & 0xfff) == 0); ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf (); SendInitIpiAllExcludingSelf ();
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
@@ -734,7 +735,7 @@ InitializeApicTimer (
if (DivideValue != 0) { if (DivideValue != 0) {
ASSERT (DivideValue <= 128); ASSERT (DivideValue <= 128);
ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue)); ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7); Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
@@ -752,6 +753,7 @@ InitializeApicTimer (
} else { } else {
LvtTimer.Bits.TimerMode = 0; LvtTimer.Bits.TimerMode = 0;
} }
LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector; LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
@@ -783,7 +785,7 @@ GetApicTimerState (
// Vector Register. // Vector Register.
// This bit will be 1, if local APIC is software enabled. // This bit will be 1, if local APIC is software enabled.
// //
ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
if (DivideValue != NULL) { if (DivideValue != NULL) {
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
@@ -792,7 +794,7 @@ GetApicTimerState (
*DivideValue = ((UINTN)1) << Divisor; *DivideValue = ((UINTN)1) << Divisor;
} }
if (PeriodicMode != NULL || Vector != NULL) { if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) { if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) { if (LvtTimer.Bits.TimerMode == 1) {
@@ -801,8 +803,9 @@ GetApicTimerState (
*PeriodicMode = FALSE; *PeriodicMode = FALSE;
} }
} }
if (Vector != NULL) { if (Vector != NULL) {
*Vector = (UINT8) LvtTimer.Bits.Vector; *Vector = (UINT8)LvtTimer.Bits.Vector;
} }
} }
} }
@@ -944,6 +947,7 @@ GetApicMsiValue (
MsiData.Bits.Level = 1; MsiData.Bits.Level = 1;
} }
} }
return MsiData.Uint64; return MsiData.Uint64;
} }
@@ -995,12 +999,15 @@ GetProcessorLocationByApicId (
if (Thread != NULL) { if (Thread != NULL) {
*Thread = 0; *Thread = 0;
} }
if (Core != NULL) { if (Core != NULL) {
*Core = 0; *Core = 0;
} }
if (Package != NULL) { if (Package != NULL) {
*Package = 0; *Package = 0;
} }
return; return;
} }
@@ -1022,7 +1029,7 @@ GetProcessorLocationByApicId (
// //
TopologyLeafSupported = FALSE; TopologyLeafSupported = FALSE;
if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx( AsmCpuidEx (
CPUID_EXTENDED_TOPOLOGY, CPUID_EXTENDED_TOPOLOGY,
0, 0,
&ExtendedTopologyEax.Uint32, &ExtendedTopologyEax.Uint32,
@@ -1065,6 +1072,7 @@ GetProcessorLocationByApicId (
CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break; break;
} }
SubIndex++; SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
} }
@@ -1085,7 +1093,7 @@ GetProcessorLocationByApicId (
// //
// Check for topology extensions on AMD processor // Check for topology extensions on AMD processor
// //
if (StandardSignatureIsAuthenticAMD()) { if (StandardSignatureIsAuthenticAMD ()) {
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
@@ -1102,8 +1110,7 @@ GetProcessorLocationByApicId (
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
} }
} }
} } else {
else {
// //
// Extract core count based on CACHE information // Extract core count based on CACHE information
// //
@@ -1115,16 +1122,18 @@ GetProcessorLocationByApicId (
} }
} }
ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
} }
if (Thread != NULL) { if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1); *Thread = InitialApicId & ((1 << ThreadBits) - 1);
} }
if (Core != NULL) { if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
} }
if (Package != NULL) { if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits)); *Package = (InitialApicId >> (ThreadBits + CoreBits));
} }
@@ -1178,12 +1187,15 @@ GetProcessorLocation2ByApicId (
if (Die != NULL) { if (Die != NULL) {
*Die = 0; *Die = 0;
} }
if (Tile != NULL) { if (Tile != NULL) {
*Tile = 0; *Tile = 0;
} }
if (Module != NULL) { if (Module != NULL) {
*Module = 0; *Module = 0;
} }
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return; return;
} }
@@ -1193,7 +1205,7 @@ GetProcessorLocation2ByApicId (
// is the preferred mechanism for enumerating topology. // is the preferred mechanism for enumerating topology.
// //
for (Index = 0; ; Index++) { for (Index = 0; ; Index++) {
AsmCpuidEx( AsmCpuidEx (
CPUID_V2_EXTENDED_TOPOLOGY, CPUID_V2_EXTENDED_TOPOLOGY,
Index, Index,
&ExtendedTopologyEax.Uint32, &ExtendedTopologyEax.Uint32,
@@ -1211,6 +1223,7 @@ GetProcessorLocation2ByApicId (
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break; break;
} }
ASSERT (LevelType < ARRAY_SIZE (Bits)); ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift; Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
} }
@@ -1226,18 +1239,19 @@ GetProcessorLocation2ByApicId (
} }
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core; Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread; Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32; Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
; LevelType ++ ; LevelType++
) { )
{
if (Location[LevelType] != NULL) { if (Location[LevelType] != NULL) {
// //
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique

72
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
View File

@@ -45,13 +45,14 @@ LocalApicBaseAddressMsrSupported (
AsmCpuid (1, &RegEax, NULL, NULL, NULL); AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11); FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) { if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
// //
// CPUs with a FamilyId of 0x04 or 0x05 do not support the // CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR // Local APIC Base Address MSR
// //
return FALSE; return FALSE;
} }
return TRUE; return TRUE;
} }
@@ -79,7 +80,7 @@ GetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
} }
@@ -110,8 +111,8 @@ SetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12); ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32)); ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
} }
@@ -140,7 +141,7 @@ ReadLocalApicReg (
ASSERT ((MmioOffset & 0xf) == 0); ASSERT ((MmioOffset & 0xf) == 0);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset); return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
} else { } else {
// //
// DFR is not supported in x2APIC mode. // DFR is not supported in x2APIC mode.
@@ -183,7 +184,7 @@ WriteLocalApicReg (
ASSERT ((MmioOffset & 0xf) == 0); ASSERT ((MmioOffset & 0xf) == 0);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value); MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
} else { } else {
// //
// DFR is not supported in x2APIC mode. // DFR is not supported in x2APIC mode.
@@ -237,7 +238,7 @@ SendIpi (
// //
// Get base address of this LAPIC // Get base address of this LAPIC
// //
LocalApciBaseAddress = GetLocalApicBaseAddress(); LocalApciBaseAddress = GetLocalApicBaseAddress ();
// //
// Save existing contents of ICR high 32 bits // Save existing contents of ICR high 32 bits
@@ -271,13 +272,12 @@ SendIpi (
MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh); MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState); SetInterruptState (InterruptState);
} else { } else {
// //
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
// interrupt in x2APIC mode. // interrupt in x2APIC mode.
// //
MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow; MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow;
AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue); AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
} }
} }
@@ -419,6 +419,7 @@ GetInitialApicId (
return ApicId; return ApicId;
} }
} }
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
return RegEbx >> 24; return RegEbx >> 24;
} else { } else {
@@ -616,7 +617,7 @@ SendInitSipiSipi (
ASSERT ((StartupRoutine & 0xfff) == 0); ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId); SendInitIpi (ApicId);
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
@@ -651,7 +652,7 @@ SendInitSipiSipiAllExcludingSelf (
ASSERT ((StartupRoutine & 0xfff) == 0); ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf (); SendInitIpiAllExcludingSelf ();
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
@@ -829,7 +830,7 @@ InitializeApicTimer (
if (DivideValue != 0) { if (DivideValue != 0) {
ASSERT (DivideValue <= 128); ASSERT (DivideValue <= 128);
ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue)); ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7); Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
@@ -847,6 +848,7 @@ InitializeApicTimer (
} else { } else {
LvtTimer.Bits.TimerMode = 0; LvtTimer.Bits.TimerMode = 0;
} }
LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector; LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
@@ -878,7 +880,7 @@ GetApicTimerState (
// Vector Register. // Vector Register.
// This bit will be 1, if local APIC is software enabled. // This bit will be 1, if local APIC is software enabled.
// //
ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
if (DivideValue != NULL) { if (DivideValue != NULL) {
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
@@ -887,7 +889,7 @@ GetApicTimerState (
*DivideValue = ((UINTN)1) << Divisor; *DivideValue = ((UINTN)1) << Divisor;
} }
if (PeriodicMode != NULL || Vector != NULL) { if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) { if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) { if (LvtTimer.Bits.TimerMode == 1) {
@@ -896,8 +898,9 @@ GetApicTimerState (
*PeriodicMode = FALSE; *PeriodicMode = FALSE;
} }
} }
if (Vector != NULL) { if (Vector != NULL) {
*Vector = (UINT8) LvtTimer.Bits.Vector; *Vector = (UINT8)LvtTimer.Bits.Vector;
} }
} }
} }
@@ -1039,6 +1042,7 @@ GetApicMsiValue (
MsiData.Bits.Level = 1; MsiData.Bits.Level = 1;
} }
} }
return MsiData.Uint64; return MsiData.Uint64;
} }
@@ -1090,12 +1094,15 @@ GetProcessorLocationByApicId (
if (Thread != NULL) { if (Thread != NULL) {
*Thread = 0; *Thread = 0;
} }
if (Core != NULL) { if (Core != NULL) {
*Core = 0; *Core = 0;
} }
if (Package != NULL) { if (Package != NULL) {
*Package = 0; *Package = 0;
} }
return; return;
} }
@@ -1117,7 +1124,7 @@ GetProcessorLocationByApicId (
// //
TopologyLeafSupported = FALSE; TopologyLeafSupported = FALSE;
if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx( AsmCpuidEx (
CPUID_EXTENDED_TOPOLOGY, CPUID_EXTENDED_TOPOLOGY,
0, 0,
&ExtendedTopologyEax.Uint32, &ExtendedTopologyEax.Uint32,
@@ -1160,6 +1167,7 @@ GetProcessorLocationByApicId (
CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break; break;
} }
SubIndex++; SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
} }
@@ -1180,7 +1188,7 @@ GetProcessorLocationByApicId (
// //
// Check for topology extensions on AMD processor // Check for topology extensions on AMD processor
// //
if (StandardSignatureIsAuthenticAMD()) { if (StandardSignatureIsAuthenticAMD ()) {
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
@@ -1197,8 +1205,7 @@ GetProcessorLocationByApicId (
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
} }
} }
} } else {
else {
// //
// Extract core count based on CACHE information // Extract core count based on CACHE information
// //
@@ -1210,16 +1217,18 @@ GetProcessorLocationByApicId (
} }
} }
ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
} }
if (Thread != NULL) { if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1); *Thread = InitialApicId & ((1 << ThreadBits) - 1);
} }
if (Core != NULL) { if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
} }
if (Package != NULL) { if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits)); *Package = (InitialApicId >> (ThreadBits + CoreBits));
} }
@@ -1273,12 +1282,15 @@ GetProcessorLocation2ByApicId (
if (Die != NULL) { if (Die != NULL) {
*Die = 0; *Die = 0;
} }
if (Tile != NULL) { if (Tile != NULL) {
*Tile = 0; *Tile = 0;
} }
if (Module != NULL) { if (Module != NULL) {
*Module = 0; *Module = 0;
} }
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return; return;
} }
@@ -1288,7 +1300,7 @@ GetProcessorLocation2ByApicId (
// is the preferred mechanism for enumerating topology. // is the preferred mechanism for enumerating topology.
// //
for (Index = 0; ; Index++) { for (Index = 0; ; Index++) {
AsmCpuidEx( AsmCpuidEx (
CPUID_V2_EXTENDED_TOPOLOGY, CPUID_V2_EXTENDED_TOPOLOGY,
Index, Index,
&ExtendedTopologyEax.Uint32, &ExtendedTopologyEax.Uint32,
@@ -1306,6 +1318,7 @@ GetProcessorLocation2ByApicId (
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break; break;
} }
ASSERT (LevelType < ARRAY_SIZE (Bits)); ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift; Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
} }
@@ -1321,18 +1334,19 @@ GetProcessorLocation2ByApicId (
} }
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core; Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread; Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32; Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
; LevelType ++ ; LevelType++
) { )
{
if (Location[LevelType] != NULL) { if (Location[LevelType] != NULL) {
// //
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique

67
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
View File

@@ -28,10 +28,20 @@ CpuCacheInfoPrintCpuCacheInfoTable (
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n")); DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
for (Index = 0; Index < CpuCacheInfoCount; Index++) { for (Index = 0; Index < CpuCacheInfoCount; Index++) {
DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n", DEBUG ((
Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel, DEBUG_INFO,
CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n",
CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount)); Index,
CpuCacheInfo[Index].Package,
CpuCacheInfo[Index].CoreType,
CpuCacheInfo[Index].CacheLevel,
CpuCacheInfo[Index].CacheType,
CpuCacheInfo[Index].CacheWays,
CpuCacheInfo[Index].FullyAssociativeCache,
CpuCacheInfo[Index].DirectMappedCache,
CpuCacheInfo[Index].CacheSizeinKB,
CpuCacheInfo[Index].CacheCount
));
} }
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n")); DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
@@ -59,15 +69,15 @@ CpuCacheInfoCompare (
ZeroMem (&Comparator1, sizeof (Comparator1)); ZeroMem (&Comparator1, sizeof (Comparator1));
ZeroMem (&Comparator2, sizeof (Comparator2)); ZeroMem (&Comparator2, sizeof (Comparator2));
Comparator1.Bits.Package = ((CPU_CACHE_INFO*)Buffer1)->Package; Comparator1.Bits.Package = ((CPU_CACHE_INFO *)Buffer1)->Package;
Comparator1.Bits.CoreType = ((CPU_CACHE_INFO*)Buffer1)->CoreType; Comparator1.Bits.CoreType = ((CPU_CACHE_INFO *)Buffer1)->CoreType;
Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer1)->CacheLevel; Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer1)->CacheLevel;
Comparator1.Bits.CacheType = ((CPU_CACHE_INFO*)Buffer1)->CacheType; Comparator1.Bits.CacheType = ((CPU_CACHE_INFO *)Buffer1)->CacheType;
Comparator2.Bits.Package = ((CPU_CACHE_INFO*)Buffer2)->Package; Comparator2.Bits.Package = ((CPU_CACHE_INFO *)Buffer2)->Package;
Comparator2.Bits.CoreType = ((CPU_CACHE_INFO*)Buffer2)->CoreType; Comparator2.Bits.CoreType = ((CPU_CACHE_INFO *)Buffer2)->CoreType;
Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer2)->CacheLevel; Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer2)->CacheLevel;
Comparator2.Bits.CacheType = ((CPU_CACHE_INFO*)Buffer2)->CacheType; Comparator2.Bits.CacheType = ((CPU_CACHE_INFO *)Buffer2)->CacheType;
if (Comparator1.Uint64 == Comparator2.Uint64) { if (Comparator1.Uint64 == Comparator2.Uint64) {
return 0; return 0;
@@ -135,7 +145,7 @@ CpuCacheInfoGetNumberOfPackages (
@retval Return the number of CoreType of requested package. @retval Return the number of CoreType of requested package.
**/ **/
UINTN UINTN
CpuCacheInfoGetNumberOfCoreTypePerPackage( CpuCacheInfoGetNumberOfCoreTypePerPackage (
IN CPUID_PROCESSOR_INFO *ProcessorInfo, IN CPUID_PROCESSOR_INFO *ProcessorInfo,
IN UINTN NumberOfProcessors, IN UINTN NumberOfProcessors,
IN UINTN Package IN UINTN Package
@@ -218,7 +228,7 @@ CpuCacheInfoCollectCoreAndCacheData (
Context->ProcessorInfo[ProcessorIndex].CoreType = 0; Context->ProcessorInfo[ProcessorIndex].CoreType = 0;
if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) { if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) {
AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL); AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL);
Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8) NativeModelIdAndCoreTypeEax.Bits.CoreType; Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8)NativeModelIdAndCoreTypeEax.Bits.CoreType;
} }
// //
@@ -320,12 +330,13 @@ CpuCacheInfoCollectCpuCacheInfoData (
continue; continue;
} }
if (CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel && if ((CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel) &&
CacheData[Index].CacheType == CacheData[NextIndex].CacheType && (CacheData[Index].CacheType == CacheData[NextIndex].CacheType) &&
ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package && (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&
ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType && (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&
(ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) == ((ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) ==
(ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)) { (ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)))
{
CacheData[NextIndex].CacheSizeinKB = 0; // uses the sharing cache CacheData[NextIndex].CacheSizeinKB = 0; // uses the sharing cache
} }
} }
@@ -334,10 +345,11 @@ CpuCacheInfoCollectCpuCacheInfoData (
// For the cache that already exists in LocalCacheInfo, increase its CacheCount. // For the cache that already exists in LocalCacheInfo, increase its CacheCount.
// //
for (CacheInfoIndex = 0; CacheInfoIndex < LocalCacheInfoCount; CacheInfoIndex++) { for (CacheInfoIndex = 0; CacheInfoIndex < LocalCacheInfoCount; CacheInfoIndex++) {
if (LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package && if ((LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&
LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType && (LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&
LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel && (LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel) &&
LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType) { (LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType))
{
LocalCacheInfo[CacheInfoIndex].CacheCount++; LocalCacheInfo[CacheInfoIndex].CacheCount++;
break; break;
} }
@@ -370,7 +382,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
// //
// Sort LocalCacheInfo array by CPU package ID, core type, cache level and cache type. // Sort LocalCacheInfo array by CPU package ID, core type, cache level and cache type.
// //
QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID*) &SortBuffer); QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID *)&SortBuffer);
CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheInfoCount); CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheInfoCount);
DEBUG_CODE ( DEBUG_CODE (
CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount); CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);
@@ -421,7 +433,7 @@ GetCpuCacheInfo (
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (*CpuCacheInfoCount != 0 && CpuCacheInfo == NULL) { if ((*CpuCacheInfoCount != 0) && (CpuCacheInfo == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -445,6 +457,7 @@ GetCpuCacheInfo (
if (Context.ProcessorInfo == NULL) { if (Context.ProcessorInfo == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
// //
// Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CacheData. // Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CacheData.
// CacheData array consists of CPUID_CACHE_DATA data structure for each Cpuid Cache Parameter Leaf // CacheData array consists of CPUID_CACHE_DATA data structure for each Cpuid Cache Parameter Leaf
@@ -467,7 +480,7 @@ GetCpuCacheInfo (
for (ProcessorIndex = 0; ProcessorIndex < NumberOfProcessors; ProcessorIndex++) { for (ProcessorIndex = 0; ProcessorIndex < NumberOfProcessors; ProcessorIndex++) {
CpuCacheInfoGetProcessorInfo (Context.MpServices, ProcessorIndex, &ProcessorInfo); CpuCacheInfoGetProcessorInfo (Context.MpServices, ProcessorIndex, &ProcessorInfo);
Context.ProcessorInfo[ProcessorIndex].Package = ProcessorInfo.Location.Package; Context.ProcessorInfo[ProcessorIndex].Package = ProcessorInfo.Location.Package;
Context.ProcessorInfo[ProcessorIndex].ApicId = (UINT32) ProcessorInfo.ProcessorId; Context.ProcessorInfo[ProcessorIndex].ApicId = (UINT32)ProcessorInfo.ProcessorId;
} }
// //

1
UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c
View File

@@ -58,6 +58,7 @@ CpuCacheInfoStartupAllCPUs (
// //
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
} }
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
Procedure (ProcedureArgument); Procedure (ProcedureArgument);

2
UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
View File

@@ -114,7 +114,6 @@ typedef struct {
CPUID_CACHE_DATA *CacheData; CPUID_CACHE_DATA *CacheData;
} COLLECT_CPUID_CACHE_DATA_CONTEXT; } COLLECT_CPUID_CACHE_DATA_CONTEXT;
/* /*
Defines the maximum count of Deterministic Cache Parameters Leaf of all APs and BSP. Defines the maximum count of Deterministic Cache Parameters Leaf of all APs and BSP.
To save boot time, skip starting up all APs to calculate each AP's count of Deterministic To save boot time, skip starting up all APs to calculate each AP's count of Deterministic
@@ -193,4 +192,5 @@ UINT32
CpuCacheInfoGetNumberOfProcessors ( CpuCacheInfoGetNumberOfProcessors (
IN MP_SERVICES MpServices IN MP_SERVICES MpServices
); );
#endif #endif

6
UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
View File

@@ -57,11 +57,12 @@ AesniSupport (
MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) { if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {
MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData; MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
ASSERT (MsrFeatureConfig != NULL); ASSERT (MsrFeatureConfig != NULL);
MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG); MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
return TRUE; return TRUE;
} }
return FALSE; return FALSE;
} }
@@ -102,7 +103,7 @@ AesniInitialize (
// programming it. // programming it.
// //
if (CpuInfo->ProcessorInfo.Location.Thread == 0) { if (CpuInfo->ProcessorInfo.Location.Thread == 0) {
MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData; MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
ASSERT (MsrFeatureConfig != NULL); ASSERT (MsrFeatureConfig != NULL);
if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) { if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD ( CPU_REGISTER_TABLE_WRITE_FIELD (
@@ -115,5 +116,6 @@ AesniInitialize (
); );
} }
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

5
UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
View File

@@ -62,7 +62,7 @@ ClockModulationSupport (
CLOCK_MODULATION_CONFIG_DATA *CmConfigData; CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) { if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) {
CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData; CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;
ASSERT (CmConfigData != NULL); ASSERT (CmConfigData != NULL);
AsmCpuid ( AsmCpuid (
CPUID_THERMAL_POWER_MANAGEMENT, CPUID_THERMAL_POWER_MANAGEMENT,
@@ -74,6 +74,7 @@ ClockModulationSupport (
CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION); CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
return TRUE; return TRUE;
} }
return FALSE; return FALSE;
} }
@@ -106,7 +107,7 @@ ClockModulationInitialize (
CLOCK_MODULATION_CONFIG_DATA *CmConfigData; CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation; MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation;
CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData; CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;
ASSERT (CmConfigData != NULL); ASSERT (CmConfigData != NULL);
ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation; ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation;

20
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
View File

@@ -33,6 +33,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) { if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"MWAIT", "MWAIT",
@@ -44,6 +45,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) { if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"ACPI", "ACPI",
@@ -55,6 +57,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) { if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"EIST", "EIST",
@@ -66,6 +69,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) { if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"FastStrings", "FastStrings",
@@ -77,6 +81,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) { if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Lock Feature Control Register", "Lock Feature Control Register",
@@ -88,6 +93,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) { if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"SMX", "SMX",
@@ -100,6 +106,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) { if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"VMX", "VMX",
@@ -112,6 +119,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) { if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Limit CpuId Maximum Value", "Limit CpuId Maximum Value",
@@ -123,6 +131,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) { if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Machine Check Enable", "Machine Check Enable",
@@ -134,6 +143,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) { if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Machine Check Architect", "Machine Check Architect",
@@ -145,6 +155,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) { if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"MCG_CTL", "MCG_CTL",
@@ -156,6 +167,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) { if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Pending Break", "Pending Break",
@@ -167,6 +179,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) { if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"C1E", "C1E",
@@ -178,6 +191,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) { if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"X2Apic", "X2Apic",
@@ -189,6 +203,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) { if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"PPIN", "PPIN",
@@ -200,6 +215,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"LMCE", "LMCE",
@@ -212,6 +228,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) { if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Proc Trace", "Proc Trace",
@@ -226,6 +243,3 @@ CpuCommonFeaturesLibConstructor (
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
View File

@@ -69,7 +69,8 @@ EistInitialize (
// //
if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
View File

@@ -40,7 +40,8 @@ FastStringsInitialize (
// //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

9
UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
View File

@@ -68,7 +68,8 @@ VmxInitialize (
// //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -146,7 +147,8 @@ LockFeatureControlRegisterInitialize (
// //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -226,7 +228,8 @@ SmxInitialize (
// core. // core.
// //
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
View File

@@ -72,7 +72,8 @@ LimitCpuidMaxvalInitialize (
IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

19
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
View File

@@ -102,6 +102,7 @@ McaSupport (
if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) { if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE; return FALSE;
} }
return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1); return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);
} }
@@ -144,7 +145,8 @@ McaInitialize (
IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -162,7 +164,7 @@ McaInitialize (
if (State) { if (State) {
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) { for (BankIndex = 0; BankIndex < (UINT32)McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -172,7 +174,7 @@ McaInitialize (
} }
if (PcdGetBool (PcdIsPowerOnReset)) { if (PcdGetBool (PcdIsPowerOnReset)) {
for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) { for (BankIndex = 0; BankIndex < (UINTN)McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -215,6 +217,7 @@ McgCtlSupport (
if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) { if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE; return FALSE;
} }
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
return (McgCap.Bits.MCG_CTL_P == 1); return (McgCap.Bits.MCG_CTL_P == 1);
} }
@@ -249,7 +252,7 @@ McgCtlInitialize (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
MSR_IA32_MCG_CTL, MSR_IA32_MCG_CTL,
(State)? MAX_UINT64 : 0 (State) ? MAX_UINT64 : 0
); );
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -287,9 +290,10 @@ LmceSupport (
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
if (ProcessorNumber == 0) { if (ProcessorNumber == 0) {
DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0))); DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0)));
} }
return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0);
return (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0);
} }
/** /**
@@ -325,7 +329,8 @@ LmceInitialize (
// //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
View File

@@ -70,7 +70,8 @@ MonitorMwaitInitialize (
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

4
UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
View File

@@ -36,9 +36,11 @@ PendingBreakSupport (
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1); return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1);
} }
return FALSE; return FALSE;
} }

7
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
View File

@@ -65,13 +65,14 @@ PpinSupport (
(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable (CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series. (CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor (CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
)) { ))
{
// //
// Check whether platform support this feature. // Check whether platform support this feature.
// //
PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1); PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
if (PlatformInfo.Bits.PPIN_CAP != 0) { if (PlatformInfo.Bits.PPIN_CAP != 0) {
MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
ASSERT (MsrPpinCtrl != NULL); ASSERT (MsrPpinCtrl != NULL);
MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
return TRUE; return TRUE;
@@ -114,7 +115,7 @@ PpinInitialize (
{ {
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
ASSERT (MsrPpinCtrl != NULL); ASSERT (MsrPpinCtrl != NULL);
// //

61
UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
View File

@@ -19,7 +19,6 @@
/// ///
#define MAX_TOPA_ENTRY_COUNT 2 #define MAX_TOPA_ENTRY_COUNT 2
/// ///
/// Processor trace output scheme selection. /// Processor trace output scheme selection.
/// ///
@@ -73,9 +72,9 @@ ProcTraceGetConfigData (
ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors); ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA)); ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *)((UINT8 *)ConfigData + sizeof (PROC_TRACE_DATA));
ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors; ConfigData->NumberOfProcessors = (UINT32)NumberOfProcessors;
ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize); ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme); ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);
@@ -114,10 +113,11 @@ ProcTraceSupport (
// //
// Check if ProcTraceMemorySize option is enabled (0xFF means disable by user) // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
// //
ProcTraceData = (PROC_TRACE_DATA *) ConfigData; ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
ASSERT (ProcTraceData != NULL); ASSERT (ProcTraceData != NULL);
if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) || if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||
(ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) { (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA))
{
return FALSE; return FALSE;
} }
@@ -130,10 +130,11 @@ ProcTraceSupport (
} }
AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL); AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);
ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1); ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN)(Ecx.Bits.RTIT == 1);
ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1); ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1);
if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) || if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||
(ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) { (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)))
{
ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL); ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE); ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS); ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
@@ -193,13 +194,14 @@ ProcTraceInitialize (
// MSR_IA32_RTIT_* for thread 0 in each core. // MSR_IA32_RTIT_* for thread 0 in each core.
// //
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
} }
ProcTraceData = (PROC_TRACE_DATA *) ConfigData; ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
ASSERT (ProcTraceData != NULL); ASSERT (ProcTraceData != NULL);
// //
@@ -245,7 +247,7 @@ ProcTraceInitialize (
/// ///
/// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
/// ///
MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12)); MemRegionSize = (UINT32)(1 << (ProcTraceData->ProcTraceMemSize + 12));
if (FirstIn) { if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize)); DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
} }
@@ -258,32 +260,34 @@ ProcTraceInitialize (
// address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be // address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
// aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared. // aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared.
// //
ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *)); ThreadMemRegionTable = (UINTN *)AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
if (ThreadMemRegionTable == NULL) { if (ThreadMemRegionTable == NULL) {
DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n")); DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable; ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) { for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
Pages = EFI_SIZE_TO_PAGES (MemRegionSize); Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
Alignment = MemRegionSize; Alignment = MemRegionSize;
AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment); AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);
if (AlignedAddress == 0) { if (AlignedAddress == 0) {
DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads)); DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));
if (Index == 0) { if (Index == 0) {
// //
// Could not allocate for BSP even // Could not allocate for BSP even
// //
FreePool ((VOID *) ThreadMemRegionTable); FreePool ((VOID *)ThreadMemRegionTable);
ThreadMemRegionTable = NULL; ThreadMemRegionTable = NULL;
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
break; break;
} }
ThreadMemRegionTable[Index] = AlignedAddress; ThreadMemRegionTable[Index] = AlignedAddress;
DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index])); DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64)ThreadMemRegionTable[Index]));
} }
DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads)); DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));
@@ -303,7 +307,8 @@ ProcTraceInitialize (
// Single Range output scheme // Single Range output scheme
// //
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) { (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))
{
if (FirstIn) { if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n")); DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
} }
@@ -324,7 +329,7 @@ ProcTraceInitialize (
// //
OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64; OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF; OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF; OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -350,7 +355,8 @@ ProcTraceInitialize (
// ToPA(Table of physical address) scheme // ToPA(Table of physical address) scheme
// //
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) { (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA))
{
// //
// Create ToPA structure aligned at 4KB for each logical thread // Create ToPA structure aligned at 4KB for each logical thread
// with at least 2 entries by 8 bytes size each. The first entry // with at least 2 entries by 8 bytes size each. The first entry
@@ -364,35 +370,38 @@ ProcTraceInitialize (
// //
// Let BSP allocate ToPA table mem for all threads // Let BSP allocate ToPA table mem for all threads
// //
TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *)); TopaMemArray = (UINTN *)AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
if (TopaMemArray == NULL) { if (TopaMemArray == NULL) {
DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n")); DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
ProcTraceData->TopaMemArray = TopaMemArray; ProcTraceData->TopaMemArray = TopaMemArray;
for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) { for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE)); Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
Alignment = 0x1000; Alignment = 0x1000;
AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment); AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);
if (AlignedAddress == 0) { if (AlignedAddress == 0) {
if (Index < ProcTraceData->AllocatedThreads) { if (Index < ProcTraceData->AllocatedThreads) {
ProcTraceData->AllocatedThreads = Index; ProcTraceData->AllocatedThreads = Index;
} }
DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads)); DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
if (Index == 0) { if (Index == 0) {
// //
// Could not allocate for BSP even // Could not allocate for BSP even
// //
FreePool ((VOID *) TopaMemArray); FreePool ((VOID *)TopaMemArray);
TopaMemArray = NULL; TopaMemArray = NULL;
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
break; break;
} }
TopaMemArray[Index] = AlignedAddress; TopaMemArray[Index] = AlignedAddress;
DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index])); DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64)TopaMemArray[Index]));
} }
DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads)); DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));
@@ -404,18 +413,18 @@ ProcTraceInitialize (
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr; TopaTable = (PROC_TRACE_TOPA_TABLE *)TopaTableBaseAddr;
TopaEntryPtr = &TopaTable->TopaEntry[0]; TopaEntryPtr = &TopaTable->TopaEntry[0];
TopaEntryPtr->Uint64 = 0; TopaEntryPtr->Uint64 = 0;
TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF; TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF; TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;
TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize; TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
TopaEntryPtr->Bits.END = 0; TopaEntryPtr->Bits.END = 0;
TopaEntryPtr = &TopaTable->TopaEntry[1]; TopaEntryPtr = &TopaTable->TopaEntry[1];
TopaEntryPtr->Uint64 = 0; TopaEntryPtr->Uint64 = 0;
TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF; TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF; TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;
TopaEntryPtr->Bits.END = 1; TopaEntryPtr->Bits.END = 1;
// //
@@ -423,7 +432,7 @@ ProcTraceInitialize (
// //
OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64; OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF; OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF; OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,

5
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
View File

@@ -59,7 +59,7 @@ X2ApicSupport (
BOOLEAN *X2ApicEnabled; BOOLEAN *X2ApicEnabled;
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
X2ApicEnabled = (BOOLEAN *) ConfigData; X2ApicEnabled = (BOOLEAN *)ConfigData;
// //
// *ConfigData indicates if X2APIC enabled on current processor // *ConfigData indicates if X2APIC enabled on current processor
// //
@@ -107,7 +107,7 @@ X2ApicInitialize (
} }
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
X2ApicEnabled = (BOOLEAN *) ConfigData; X2ApicEnabled = (BOOLEAN *)ConfigData;
if (X2ApicEnabled[ProcessorNumber]) { if (X2ApicEnabled[ProcessorNumber]) {
PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD ( PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber, ProcessorNumber,
@@ -133,5 +133,6 @@ X2ApicInitialize (
); );
} }
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

17
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
View File

@@ -69,7 +69,7 @@ GetExceptionNameStr (
IN EFI_EXCEPTION_TYPE ExceptionType IN EFI_EXCEPTION_TYPE ExceptionType
) )
{ {
if ((UINTN) ExceptionType < EXCEPTION_KNOWN_NAME_NUM) { if ((UINTN)ExceptionType < EXCEPTION_KNOWN_NAME_NUM) {
return mExceptionNameStr[ExceptionType]; return mExceptionNameStr[ExceptionType];
} else { } else {
return mExceptionReservedStr; return mExceptionReservedStr;
@@ -130,20 +130,22 @@ DumpModuleImageInfo (
// //
// Find Image Base entry point // Find Image Base entry point
// //
Status = PeCoffLoaderGetEntryPoint ((VOID *) Pe32Data, &EntryPoint); Status = PeCoffLoaderGetEntryPoint ((VOID *)Pe32Data, &EntryPoint);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
EntryPoint = NULL; EntryPoint = NULL;
} }
InternalPrintMessage ("!!!! Find image based on IP(0x%x) ", CurrentEip); InternalPrintMessage ("!!!! Find image based on IP(0x%x) ", CurrentEip);
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data); PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);
if (PdbPointer != NULL) { if (PdbPointer != NULL) {
InternalPrintMessage ("%a", PdbPointer); InternalPrintMessage ("%a", PdbPointer);
} else { } else {
InternalPrintMessage ("(No PDB) " ); InternalPrintMessage ("(No PDB) ");
} }
InternalPrintMessage ( InternalPrintMessage (
" (ImageBase=%016lp, EntryPoint=%016p) !!!!\n", " (ImageBase=%016lp, EntryPoint=%016p) !!!!\n",
(VOID *) Pe32Data, (VOID *)Pe32Data,
EntryPoint EntryPoint
); );
} }
@@ -174,10 +176,13 @@ ReadAndVerifyVectorInfo (
// //
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (VectorInfo->VectorNumber < VectorCount) { if (VectorInfo->VectorNumber < VectorCount) {
ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute; ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute;
} }
VectorInfo ++;
VectorInfo++;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
View File

@@ -318,4 +318,3 @@ AsmGetTssTemplateMap (
); );
#endif #endif

24
UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
View File

@@ -107,7 +107,7 @@ InitializeCpuInterruptHandlers (
(VOID **)&ReservedVectors (VOID **)&ReservedVectors
); );
ASSERT (!EFI_ERROR (Status) && ReservedVectors != NULL); ASSERT (!EFI_ERROR (Status) && ReservedVectors != NULL);
SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff); SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff);
if (VectorInfo != NULL) { if (VectorInfo != NULL) {
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_INTERRUPT_NUM); Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_INTERRUPT_NUM);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@@ -127,6 +127,7 @@ InitializeCpuInterruptHandlers (
if (IdtEntryCount > CPU_INTERRUPT_NUM) { if (IdtEntryCount > CPU_INTERRUPT_NUM) {
IdtEntryCount = CPU_INTERRUPT_NUM; IdtEntryCount = CPU_INTERRUPT_NUM;
} }
// //
// Create Interrupt Descriptor Table and Copy the old IDT table in // Create Interrupt Descriptor Table and Copy the old IDT table in
// //
@@ -144,18 +145,18 @@ InitializeCpuInterruptHandlers (
); );
ASSERT (!EFI_ERROR (Status) && InterruptEntryCode != NULL); ASSERT (!EFI_ERROR (Status) && InterruptEntryCode != NULL);
InterruptEntry = (UINTN) InterruptEntryCode; InterruptEntry = (UINTN)InterruptEntryCode;
for (Index = 0; Index < CPU_INTERRUPT_NUM; Index ++) { for (Index = 0; Index < CPU_INTERRUPT_NUM; Index++) {
CopyMem ( CopyMem (
(VOID *) InterruptEntry, (VOID *)InterruptEntry,
(VOID *) TemplateMap.ExceptionStart, (VOID *)TemplateMap.ExceptionStart,
TemplateMap.ExceptionStubHeaderSize TemplateMap.ExceptionStubHeaderSize
); );
AsmVectorNumFixup ((VOID *) InterruptEntry, (UINT8) Index, (VOID *) TemplateMap.ExceptionStart); AsmVectorNumFixup ((VOID *)InterruptEntry, (UINT8)Index, (VOID *)TemplateMap.ExceptionStart);
InterruptEntry += TemplateMap.ExceptionStubHeaderSize; InterruptEntry += TemplateMap.ExceptionStubHeaderSize;
} }
TemplateMap.ExceptionStart = (UINTN) InterruptEntryCode; TemplateMap.ExceptionStart = (UINTN)InterruptEntryCode;
mExceptionHandlerData.IdtEntryCount = CPU_INTERRUPT_NUM; mExceptionHandlerData.IdtEntryCount = CPU_INTERRUPT_NUM;
mExceptionHandlerData.ReservedVectors = ReservedVectors; mExceptionHandlerData.ReservedVectors = ReservedVectors;
mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler; mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler;
@@ -166,9 +167,9 @@ InitializeCpuInterruptHandlers (
// //
// Load Interrupt Descriptor Table // Load Interrupt Descriptor Table
// //
IdtDescriptor.Base = (UINTN) IdtTable; IdtDescriptor.Base = (UINTN)IdtTable;
IdtDescriptor.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1); IdtDescriptor.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1);
AsmWriteIdtr ((IA32_DESCRIPTOR *) &IdtDescriptor); AsmWriteIdtr ((IA32_DESCRIPTOR *)&IdtDescriptor);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -246,7 +247,7 @@ InitializeCpuExceptionHandlersEx (
// version instead; or this method must be implemented as a simple wrapper of // version instead; or this method must be implemented as a simple wrapper of
// non-ex version of it, if this version has to be called. // non-ex version of it, if this version has to be called.
// //
if (InitData == NULL || InitData->X64.InitDefaultHandlers) { if ((InitData == NULL) || InitData->X64.InitDefaultHandlers) {
Status = InitializeCpuExceptionHandlers (VectorInfo); Status = InitializeCpuExceptionHandlers (VectorInfo);
} else { } else {
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@@ -279,6 +280,7 @@ InitializeCpuExceptionHandlersEx (
InitData = &EssData; InitData = &EssData;
} }
Status = ArchSetupExceptionStack (InitData); Status = ArchSetupExceptionStack (InitData);
} }
} }

50
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
View File

@@ -77,7 +77,7 @@ ArchSaveExceptionContext (
// //
// Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin. // Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin.
// //
SystemContext.SystemContextIa32->Eip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode; SystemContext.SystemContextIa32->Eip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode;
} }
/** /**
@@ -131,17 +131,18 @@ ArchSetupExceptionStack (
UINTN GdtSize; UINTN GdtSize;
EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
if (StackSwitchData == NULL || if ((StackSwitchData == NULL) ||
StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV || (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
StackSwitchData->Ia32.KnownGoodStackTop == 0 || (StackSwitchData->Ia32.KnownGoodStackTop == 0) ||
StackSwitchData->Ia32.KnownGoodStackSize == 0 || (StackSwitchData->Ia32.KnownGoodStackSize == 0) ||
StackSwitchData->Ia32.StackSwitchExceptions == NULL || (StackSwitchData->Ia32.StackSwitchExceptions == NULL) ||
StackSwitchData->Ia32.StackSwitchExceptionNumber == 0 || (StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) ||
StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM || (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
StackSwitchData->Ia32.GdtTable == NULL || (StackSwitchData->Ia32.GdtTable == NULL) ||
StackSwitchData->Ia32.IdtTable == NULL || (StackSwitchData->Ia32.IdtTable == NULL) ||
StackSwitchData->Ia32.ExceptionTssDesc == NULL || (StackSwitchData->Ia32.ExceptionTssDesc == NULL) ||
StackSwitchData->Ia32.ExceptionTss == NULL) { (StackSwitchData->Ia32.ExceptionTss == NULL))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -159,7 +160,8 @@ ArchSetupExceptionStack (
} }
if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize > if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize >
((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) { ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -168,11 +170,14 @@ ArchSetupExceptionStack (
// specified. // specified.
// //
if (StackSwitchData->Ia32.ExceptionTssDescSize < if (StackSwitchData->Ia32.ExceptionTssDescSize <
sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) { sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (StackSwitchData->Ia32.ExceptionTssSize < if (StackSwitchData->Ia32.ExceptionTssSize <
sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) { sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -198,6 +203,7 @@ ArchSetupExceptionStack (
if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) { if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) {
Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable; Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable;
} }
if (StackSwitchData->Ia32.IdtTableSize > 0) { if (StackSwitchData->Ia32.IdtTableSize > 0) {
Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1); Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1);
} }
@@ -209,7 +215,7 @@ ArchSetupExceptionStack (
TssBase = (UINTN)Tss; TssBase = (UINTN)Tss;
TssDesc->Uint64 = 0; TssDesc->Uint64 = 0;
TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
@@ -234,7 +240,7 @@ ArchSetupExceptionStack (
TssBase = (UINTN)Tss; TssBase = (UINTN)Tss;
TssDesc->Uint64 = 0; TssDesc->Uint64 = 0;
TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
@@ -246,8 +252,9 @@ ArchSetupExceptionStack (
// Fixup TSS // Fixup TSS
// //
Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index]; Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index];
if (Vector >= CPU_EXCEPTION_NUM || if ((Vector >= CPU_EXCEPTION_NUM) ||
Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) { (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
{
continue; continue;
} }
@@ -331,8 +338,10 @@ DumpCpuContext (
(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0
); );
} }
InternalPrintMessage ("\n"); InternalPrintMessage ("\n");
} }
InternalPrintMessage ( InternalPrintMessage (
"EIP - %08x, CS - %08x, EFLAGS - %08x\n", "EIP - %08x, CS - %08x, EFLAGS - %08x\n",
SystemContext.SystemContextIa32->Eip, SystemContext.SystemContextIa32->Eip,
@@ -415,7 +424,8 @@ DumpImageAndCpuContent (
// Dump module image base and module entry point by EIP // Dump module image base and module entry point by EIP
// //
if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) && if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&
((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)) { ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0))
{
// //
// The EIP in SystemContext could not be used // The EIP in SystemContext could not be used
// if it is page fault with I/D set. // if it is page fault with I/D set.

5
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
View File

@@ -62,6 +62,7 @@ SetExceptionHandlerData (
EXCEPTION0_STUB_HEADER *Exception0StubHeader; EXCEPTION0_STUB_HEADER *Exception0StubHeader;
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
IA32_IDT_GATE_DESCRIPTOR *IdtTable; IA32_IDT_GATE_DESCRIPTOR *IdtTable;
// //
// Duplicate the exception #0 stub header in pool and cache the ExceptionHandlerData just after the stub header. // Duplicate the exception #0 stub header in pool and cache the ExceptionHandlerData just after the stub header.
// So AP can get the ExceptionHandlerData by reading the IDT[0]. // So AP can get the ExceptionHandlerData by reading the IDT[0].
@@ -243,7 +244,7 @@ InitializeCpuExceptionHandlersEx (
// version instead; or this method must be implemented as a simple wrapper of // version instead; or this method must be implemented as a simple wrapper of
// non-ex version of it, if this version has to be called. // non-ex version of it, if this version has to be called.
// //
if (InitData == NULL || InitData->Ia32.InitDefaultHandlers) { if ((InitData == NULL) || InitData->Ia32.InitDefaultHandlers) {
Status = InitializeCpuExceptionHandlers (VectorInfo); Status = InitializeCpuExceptionHandlers (VectorInfo);
} else { } else {
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@@ -253,7 +254,7 @@ InitializeCpuExceptionHandlersEx (
// //
// Initializing stack switch is only necessary for Stack Guard functionality. // Initializing stack switch is only necessary for Stack Guard functionality.
// //
if (PcdGetBool (PcdCpuStackGuard) && InitData != NULL) { if (PcdGetBool (PcdCpuStackGuard) && (InitData != NULL)) {
Status = ArchSetupExceptionStack (InitData); Status = ArchSetupExceptionStack (InitData);
} }
} }

39
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
View File

@@ -45,7 +45,7 @@ CommonExceptionHandlerWorker (
} }
} }
ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (SystemContext.SystemContextIa32); ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *)(UINTN)(SystemContext.SystemContextIa32);
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler; ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;
@@ -75,6 +75,7 @@ CommonExceptionHandlerWorker (
ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler; ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
return; return;
} }
// //
// If spin-lock cannot be acquired, it's the second time entering here. // If spin-lock cannot be acquired, it's the second time entering here.
// 'break' instead of 'return' is used so the new exception handler can be executed. // 'break' instead of 'return' is used so the new exception handler can be executed.
@@ -91,8 +92,10 @@ CommonExceptionHandlerWorker (
ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock); ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock);
break; break;
} }
CpuPause (); CpuPause ();
} }
break; break;
case 0xffffffff: case 0xffffffff:
break; break;
@@ -104,9 +107,10 @@ CommonExceptionHandlerWorker (
break; break;
} }
if (ExternalInterruptHandler != NULL && if ((ExternalInterruptHandler != NULL) &&
ExternalInterruptHandler[ExceptionType] != NULL) { (ExternalInterruptHandler[ExceptionType] != NULL))
(ExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext); {
(ExternalInterruptHandler[ExceptionType])(ExceptionType, SystemContext);
} else if (ExceptionType < CPU_EXCEPTION_NUM) { } else if (ExceptionType < CPU_EXCEPTION_NUM) {
// //
// Get Spinlock to display CPU information // Get Spinlock to display CPU information
@@ -114,6 +118,7 @@ CommonExceptionHandlerWorker (
while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) { while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) {
CpuPause (); CpuPause ();
} }
// //
// Initialize the serial port before dumping. // Initialize the serial port before dumping.
// //
@@ -162,7 +167,7 @@ UpdateIdtTable (
// //
CodeSegment = AsmReadCs (); CodeSegment = AsmReadCs ();
for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index ++) { for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index++) {
IdtTable[Index].Bits.Selector = CodeSegment; IdtTable[Index].Bits.Selector = CodeSegment;
// //
// Check reserved vectors attributes // Check reserved vectors attributes
@@ -176,14 +181,14 @@ UpdateIdtTable (
case EFI_VECTOR_HANDOFF_HOOK_AFTER: case EFI_VECTOR_HANDOFF_HOOK_AFTER:
InitializeSpinLock (&ReservedVectors[Index].SpinLock); InitializeSpinLock (&ReservedVectors[Index].SpinLock);
CopyMem ( CopyMem (
(VOID *) ReservedVectors[Index].HookAfterStubHeaderCode, (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode,
(VOID *) TemplateMap->HookAfterStubHeaderStart, (VOID *)TemplateMap->HookAfterStubHeaderStart,
TemplateMap->ExceptionStubHeaderSize TemplateMap->ExceptionStubHeaderSize
); );
AsmVectorNumFixup ( AsmVectorNumFixup (
(VOID *) ReservedVectors[Index].HookAfterStubHeaderCode, (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode,
(UINT8) Index, (UINT8)Index,
(VOID *) TemplateMap->HookAfterStubHeaderStart (VOID *)TemplateMap->HookAfterStubHeaderStart
); );
// //
// Go on the following code // Go on the following code
@@ -233,7 +238,7 @@ InitializeCpuExceptionHandlersWorker (
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff); SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
if (VectorInfo != NULL) { if (VectorInfo != NULL) {
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_EXCEPTION_NUM); Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_EXCEPTION_NUM);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@@ -253,7 +258,7 @@ InitializeCpuExceptionHandlersWorker (
IdtEntryCount = CPU_EXCEPTION_NUM; IdtEntryCount = CPU_EXCEPTION_NUM;
} }
IdtTable = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base; IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
AsmGetTemplateAddressMap (&TemplateMap); AsmGetTemplateAddressMap (&TemplateMap);
ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE); ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);
@@ -295,20 +300,20 @@ RegisterCpuInterruptHandlerWorker (
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler; ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;
if (InterruptType < 0 || InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum || if ((InterruptType < 0) || (InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum) ||
ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) { (ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK))
{
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (InterruptHandler == NULL && ExternalInterruptHandler[InterruptType] == NULL) { if ((InterruptHandler == NULL) && (ExternalInterruptHandler[InterruptType] == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (InterruptHandler != NULL && ExternalInterruptHandler[InterruptType] != NULL) { if ((InterruptHandler != NULL) && (ExternalInterruptHandler[InterruptType] != NULL)) {
return EFI_ALREADY_STARTED; return EFI_ALREADY_STARTED;
} }
ExternalInterruptHandler[InterruptType] = InterruptHandler; ExternalInterruptHandler[InterruptType] = InterruptHandler;
return EFI_SUCCESS; return EFI_SUCCESS;
} }

8
UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
View File

@@ -93,12 +93,13 @@ InitializeCpuExceptionHandlers (
UINTN InterruptHandler; UINTN InterruptHandler;
if (VectorInfo != NULL) { if (VectorInfo != NULL) {
SetMem ((VOID *) ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff); SetMem ((VOID *)ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectorData, CPU_EXCEPTION_NUM); Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectorData, CPU_EXCEPTION_NUM);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
} }
// //
// Read IDT descriptor and calculate IDT size // Read IDT descriptor and calculate IDT size
// //
@@ -110,6 +111,7 @@ InitializeCpuExceptionHandlers (
// //
IdtEntryCount = CPU_EXCEPTION_NUM; IdtEntryCount = CPU_EXCEPTION_NUM;
} }
// //
// Use current CS as the segment selector of interrupt gate in IDT // Use current CS as the segment selector of interrupt gate in IDT
// //
@@ -117,7 +119,7 @@ InitializeCpuExceptionHandlers (
AsmGetTemplateAddressMap (&TemplateMap); AsmGetTemplateAddressMap (&TemplateMap);
IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base; IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
for (Index = 0; Index < IdtEntryCount; Index ++) { for (Index = 0; Index < IdtEntryCount; Index++) {
IdtTable[Index].Bits.Selector = CodeSegment; IdtTable[Index].Bits.Selector = CodeSegment;
// //
// Check reserved vectors attributes if has, only EFI_VECTOR_HANDOFF_DO_NOT_HOOK // Check reserved vectors attributes if has, only EFI_VECTOR_HANDOFF_DO_NOT_HOOK
@@ -128,12 +130,14 @@ InitializeCpuExceptionHandlers (
continue; continue;
} }
} }
// //
// Update IDT entry // Update IDT entry
// //
InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize; InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;
ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler); ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
View File

@@ -19,6 +19,7 @@ SPIN_LOCK mDisplayMessageSpinLock;
RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM]; RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM]; EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
EXCEPTION_HANDLER_DATA mExceptionHandlerData; EXCEPTION_HANDLER_DATA mExceptionHandlerData;
/** /**
Common exception handler. Common exception handler.

49
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
View File

@@ -38,8 +38,8 @@ ArchGetIdtHandler (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
) )
{ {
return IdtEntry->Bits.OffsetLow + (((UINTN) IdtEntry->Bits.OffsetHigh) << 16) + return IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16) +
(((UINTN) IdtEntry->Bits.OffsetUpper) << 32); (((UINTN)IdtEntry->Bits.OffsetUpper) << 32);
} }
/** /**
@@ -80,7 +80,7 @@ ArchSaveExceptionContext (
// //
// Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin. // Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin.
// //
SystemContext.SystemContextX64->Rip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode; SystemContext.SystemContextX64->Rip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode;
} }
/** /**
@@ -135,17 +135,18 @@ ArchSetupExceptionStack (
UINTN TssBase; UINTN TssBase;
UINTN GdtSize; UINTN GdtSize;
if (StackSwitchData == NULL || if ((StackSwitchData == NULL) ||
StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV || (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
StackSwitchData->X64.KnownGoodStackTop == 0 || (StackSwitchData->X64.KnownGoodStackTop == 0) ||
StackSwitchData->X64.KnownGoodStackSize == 0 || (StackSwitchData->X64.KnownGoodStackSize == 0) ||
StackSwitchData->X64.StackSwitchExceptions == NULL || (StackSwitchData->X64.StackSwitchExceptions == NULL) ||
StackSwitchData->X64.StackSwitchExceptionNumber == 0 || (StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||
StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM || (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
StackSwitchData->X64.GdtTable == NULL || (StackSwitchData->X64.GdtTable == NULL) ||
StackSwitchData->X64.IdtTable == NULL || (StackSwitchData->X64.IdtTable == NULL) ||
StackSwitchData->X64.ExceptionTssDesc == NULL || (StackSwitchData->X64.ExceptionTssDesc == NULL) ||
StackSwitchData->X64.ExceptionTss == NULL) { (StackSwitchData->X64.ExceptionTss == NULL))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -163,7 +164,8 @@ ArchSetupExceptionStack (
} }
if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) > if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >
((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) { ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -173,6 +175,7 @@ ArchSetupExceptionStack (
if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) { if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) { if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -203,6 +206,7 @@ ArchSetupExceptionStack (
if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) { if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {
Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable; Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;
} }
if (StackSwitchData->X64.IdtTableSize > 0) { if (StackSwitchData->X64.IdtTableSize > 0) {
Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1); Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);
} }
@@ -214,8 +218,8 @@ ArchSetupExceptionStack (
TssBase = (UINTN)Tss; TssBase = (UINTN)Tss;
TssDesc->Uint128.Uint64 = 0; TssDesc->Uint128.Uint64 = 0;
TssDesc->Uint128.Uint64_1= 0; TssDesc->Uint128.Uint64_1 = 0;
TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
@@ -242,10 +246,12 @@ ArchSetupExceptionStack (
// Set the IST field to enable corresponding IST // Set the IST field to enable corresponding IST
// //
Vector = StackSwitchData->X64.StackSwitchExceptions[Index]; Vector = StackSwitchData->X64.StackSwitchExceptions[Index];
if (Vector >= CPU_EXCEPTION_NUM || if ((Vector >= CPU_EXCEPTION_NUM) ||
Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) { (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
{
continue; continue;
} }
IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1); IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);
} }
@@ -304,8 +310,10 @@ DumpCpuContext (
(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0 (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0
); );
} }
InternalPrintMessage ("\n"); InternalPrintMessage ("\n");
} }
InternalPrintMessage ( InternalPrintMessage (
"RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n", "RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n",
SystemContext.SystemContextX64->Rip, SystemContext.SystemContextX64->Rip,
@@ -415,7 +423,8 @@ DumpImageAndCpuContent (
// Dump module image base and module entry point by RIP // Dump module image base and module entry point by RIP
// //
if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) && if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&
((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0)) { ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0))
{
// //
// The RIP in SystemContext could not be used // The RIP in SystemContext could not be used
// if it is page fault with I/D set. // if it is page fault with I/D set.

1
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
View File

@@ -38,4 +38,3 @@ InternalGetPerformanceCounterFrequency (
{ {
return CpuidCoreClockCalculateTscFrequency (); return CpuidCoreClockCalculateTscFrequency ();
} }

22
UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
View File

@@ -13,7 +13,9 @@
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Register/Cpuid.h> #include <Register/Cpuid.h>
GUID mCpuCrystalFrequencyHobGuid = { 0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a } }; GUID mCpuCrystalFrequencyHobGuid = {
0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a }
};
/** /**
Internal function to retrieves the 64-bit frequency in Hz. Internal function to retrieves the 64-bit frequency in Hz.
@@ -57,11 +59,12 @@ CpuidCoreClockCalculateTscFrequency (
// //
// If EAX or EBX returns 0, the XTAL ratio is not enumerated. // If EAX or EBX returns 0, the XTAL ratio is not enumerated.
// //
if (RegEax == 0 || RegEbx ==0 ) { if ((RegEax == 0) || (RegEbx == 0)) {
ASSERT (RegEax != 0); ASSERT (RegEax != 0);
ASSERT (RegEbx != 0); ASSERT (RegEbx != 0);
return 0; return 0;
} }
// //
// If ECX returns 0, the XTAL frequency is not enumerated. // If ECX returns 0, the XTAL frequency is not enumerated.
// And PcdCpuCoreCrystalClockFrequency defined should base on processor series. // And PcdCpuCoreCrystalClockFrequency defined should base on processor series.
@@ -69,7 +72,7 @@ CpuidCoreClockCalculateTscFrequency (
if (RegEcx == 0) { if (RegEcx == 0) {
CoreXtalFrequency = PcdGet64 (PcdCpuCoreCrystalClockFrequency); CoreXtalFrequency = PcdGet64 (PcdCpuCoreCrystalClockFrequency);
} else { } else {
CoreXtalFrequency = (UINT64) RegEcx; CoreXtalFrequency = (UINT64)RegEcx;
} }
// //
@@ -99,7 +102,7 @@ InternalCpuDelay (
// //
// The target timer count is calculated here // The target timer count is calculated here
// //
Ticks = AsmReadTsc() + Delay; Ticks = AsmReadTsc () + Delay;
// //
// Wait until time out // Wait until time out
@@ -107,8 +110,8 @@ InternalCpuDelay (
// Thus, this function must be called within 10 years of reset since // Thus, this function must be called within 10 years of reset since
// Intel guarantees a minimum of 10 years before the TSC wraps. // Intel guarantees a minimum of 10 years before the TSC wraps.
// //
while (AsmReadTsc() <= Ticks) { while (AsmReadTsc () <= Ticks) {
CpuPause(); CpuPause ();
} }
} }
@@ -128,7 +131,6 @@ MicroSecondDelay (
IN UINTN MicroSeconds IN UINTN MicroSeconds
) )
{ {
InternalCpuDelay ( InternalCpuDelay (
DivU64x32 ( DivU64x32 (
MultU64x64 ( MultU64x64 (
@@ -158,7 +160,6 @@ NanoSecondDelay (
IN UINTN NanoSeconds IN UINTN NanoSeconds
) )
{ {
InternalCpuDelay ( InternalCpuDelay (
DivU64x32 ( DivU64x32 (
MultU64x64 ( MultU64x64 (
@@ -230,6 +231,7 @@ GetPerformanceCounterProperties (
if (EndValue != NULL) { if (EndValue != NULL) {
*EndValue = 0xffffffffffffffffULL; *EndValue = 0xffffffffffffffffULL;
} }
return InternalGetPerformanceCounterFrequency (); return InternalGetPerformanceCounterFrequency ();
} }
@@ -270,8 +272,8 @@ GetTimeInNanoSecond (
// i.e. highest bit set in Remainder should <= 33. // i.e. highest bit set in Remainder should <= 33.
// //
Shift = MAX (0, HighBitSet64 (Remainder) - 33); Shift = MAX (0, HighBitSet64 (Remainder) - 33);
Remainder = RShiftU64 (Remainder, (UINTN) Shift); Remainder = RShiftU64 (Remainder, (UINTN)Shift);
Frequency = RShiftU64 (Frequency, (UINTN) Shift); Frequency = RShiftU64 (Frequency, (UINTN)Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL); NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds; return NanoSeconds;

41
UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c
View File

@@ -49,7 +49,7 @@ GetProcessorMicrocodeCpuId (
ASSERT (MicrocodeCpuId != NULL); ASSERT (MicrocodeCpuId != NULL);
PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
MicrocodeCpuId->PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId; MicrocodeCpuId->PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId;
AsmCpuid (CPUID_VERSION_INFO, &MicrocodeCpuId->ProcessorSignature, NULL, NULL, NULL); AsmCpuid (CPUID_VERSION_INFO, &MicrocodeCpuId->ProcessorSignature, NULL, NULL, NULL);
} }
@@ -82,6 +82,7 @@ GetMicrocodeLength (
if (Microcode->DataSize != 0) { if (Microcode->DataSize != 0) {
TotalSize = Microcode->TotalSize; TotalSize = Microcode->TotalSize;
} }
return TotalSize; return TotalSize;
} }
@@ -100,7 +101,7 @@ LoadMicrocode (
{ {
ASSERT (Microcode != NULL); ASSERT (Microcode != NULL);
AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64) (UINTN) (Microcode + 1)); AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64)(UINTN)(Microcode + 1));
} }
/** /**
@@ -133,7 +134,8 @@ IsProcessorMatchedMicrocode (
for (Index = 0; Index < MicrocodeCpuIdCount; Index++) { for (Index = 0; Index < MicrocodeCpuIdCount; Index++) {
if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) && if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) &&
(ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0) { ((ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0))
{
return TRUE; return TRUE;
} }
} }
@@ -206,7 +208,7 @@ IsValidMicrocode (
// the input microcode buffer is so small that even cannot contain the header. // the input microcode buffer is so small that even cannot contain the header.
// the input microcode buffer is so large that exceeds MAX_ADDRESS. // the input microcode buffer is so large that exceeds MAX_ADDRESS.
// //
if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN) Microcode))) { if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN)Microcode))) {
return FALSE; return FALSE;
} }
@@ -249,7 +251,7 @@ IsValidMicrocode (
// //
// The summation of all DWORDs in microcode should be zero. // The summation of all DWORDs in microcode should be zero.
// //
if (VerifyChecksum && (CalculateSum32 ((UINT32 *) Microcode, TotalSize) != 0)) { if (VerifyChecksum && (CalculateSum32 ((UINT32 *)Microcode, TotalSize) != 0)) {
return FALSE; return FALSE;
} }
@@ -272,29 +274,34 @@ IsValidMicrocode (
if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) || ((ExtendedTableLength % 4) != 0)) { if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) || ((ExtendedTableLength % 4) != 0)) {
return FALSE; return FALSE;
} }
// //
// Extended Table exist, check if the CPU in support list // Extended Table exist, check if the CPU in support list
// //
ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINTN) (Microcode + 1) + DataSize); ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *)((UINTN)(Microcode + 1) + DataSize);
if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (CPU_MICROCODE_EXTENDED_TABLE)) { if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (CPU_MICROCODE_EXTENDED_TABLE)) {
return FALSE; return FALSE;
} }
if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_EXTENDED_TABLE) if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_EXTENDED_TABLE)
> ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) { > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER))
return FALSE; {
}
//
// Check the extended table checksum
//
if (VerifyChecksum && (CalculateSum32 ((UINT32 *) ExtendedTableHeader, ExtendedTableLength) != 0)) {
return FALSE; return FALSE;
} }
ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1); //
for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index ++) { // Check the extended table checksum
//
if (VerifyChecksum && (CalculateSum32 ((UINT32 *)ExtendedTableHeader, ExtendedTableLength) != 0)) {
return FALSE;
}
ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *)(ExtendedTableHeader + 1);
for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index++) {
if (VerifyChecksum && if (VerifyChecksum &&
(ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[Index].ProcessorFlag (ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[Index].ProcessorFlag
+ ExtendedTable[Index].Checksum != Sum32)) { + ExtendedTable[Index].Checksum != Sum32))
{
// //
// The extended table entry is valid when the summation of Processor Signature, Processor Flags // The extended table entry is valid when the summation of Processor Signature, Processor Flags
// and Checksum equal to the coresponding summation from primary header. Because: // and Checksum equal to the coresponding summation from primary header. Because:
@@ -308,6 +315,7 @@ IsValidMicrocode (
// //
continue; continue;
} }
Match = IsProcessorMatchedMicrocode ( Match = IsProcessorMatchedMicrocode (
ExtendedTable[Index].ProcessorSignature.Uint32, ExtendedTable[Index].ProcessorSignature.Uint32,
ExtendedTable[Index].ProcessorFlag, ExtendedTable[Index].ProcessorFlag,
@@ -318,5 +326,6 @@ IsValidMicrocode (
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }

74
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
View File

@@ -115,6 +115,7 @@ GetWakeupBuffer (
} else { } else {
StartAddress = 0x88000; StartAddress = 0x88000;
} }
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
MemoryType, MemoryType,
@@ -123,7 +124,7 @@ GetWakeupBuffer (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
StartAddress = (EFI_PHYSICAL_ADDRESS) -1; StartAddress = (EFI_PHYSICAL_ADDRESS)-1;
} else if (PcdGetBool (PcdSevEsIsEnabled)) { } else if (PcdGetBool (PcdSevEsIsEnabled)) {
// //
// Next SEV-ES wakeup buffer allocation must be below this allocation // Next SEV-ES wakeup buffer allocation must be below this allocation
@@ -131,10 +132,14 @@ GetWakeupBuffer (
mSevEsDxeWakeupBuffer = StartAddress; mSevEsDxeWakeupBuffer = StartAddress;
} }
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n", DEBUG ((
(UINTN) StartAddress, WakeupBufferSize)); DEBUG_INFO,
"WakeupBufferStart = %x, WakeupBufferSize = %x\n",
(UINTN)StartAddress,
WakeupBufferSize
));
return (UINTN) StartAddress; return (UINTN)StartAddress;
} }
/** /**
@@ -202,7 +207,7 @@ GetSevEsAPMemory (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN) StartAddress)); DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN)StartAddress));
// //
// Save the SevEsAPMemory as the AP jump table. // Save the SevEsAPMemory as the AP jump table.
@@ -211,10 +216,10 @@ GetSevEsAPMemory (
Ghcb = Msr.Ghcb; Ghcb = Msr.Ghcb;
VmgInit (Ghcb, &InterruptState); VmgInit (Ghcb, &InterruptState);
VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64) (UINTN) StartAddress); VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64)(UINTN)StartAddress);
VmgDone (Ghcb, InterruptState); VmgDone (Ghcb, InterruptState);
return (UINTN) StartAddress; return (UINTN)StartAddress;
} }
/** /**
@@ -236,7 +241,6 @@ CheckAndUpdateApsStatus (
// First, check whether pending StartupAllAPs() exists. // First, check whether pending StartupAllAPs() exists.
// //
if (CpuMpData->WaitEvent != NULL) { if (CpuMpData->WaitEvent != NULL) {
Status = CheckAllAPs (); Status = CheckAllAPs ();
// //
// If all APs finish for StartupAllAPs(), signal the WaitEvent for it. // If all APs finish for StartupAllAPs(), signal the WaitEvent for it.
@@ -251,7 +255,6 @@ CheckAndUpdateApsStatus (
// Second, check whether pending StartupThisAPs() callings exist. // Second, check whether pending StartupThisAPs() callings exist.
// //
for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) { for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {
if (CpuMpData->CpuData[ProcessorNumber].WaitEvent == NULL) { if (CpuMpData->CpuData[ProcessorNumber].WaitEvent == NULL) {
continue; continue;
} }
@@ -307,18 +310,20 @@ GetProtectedMode16CS (
UINTN GdtEntryCount; UINTN GdtEntryCount;
UINT16 Index; UINT16 Index;
Index = (UINT16) -1; Index = (UINT16)-1;
AsmReadGdtr (&GdtrDesc); AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) { for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) { if (GdtEntry->Bits.L == 0) {
if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 0) { if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 0)) {
break; break;
} }
} }
GdtEntry++; GdtEntry++;
} }
ASSERT (Index != GdtEntryCount); ASSERT (Index != GdtEntryCount);
return Index * 8; return Index * 8;
} }
@@ -340,15 +345,17 @@ GetProtectedModeCS (
AsmReadGdtr (&GdtrDesc); AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) { for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) { if (GdtEntry->Bits.L == 0) {
if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) { if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {
break; break;
} }
} }
GdtEntry++; GdtEntry++;
} }
ASSERT (Index != GdtEntryCount); ASSERT (Index != GdtEntryCount);
return Index * 8; return Index * 8;
} }
@@ -378,13 +385,14 @@ RelocateApLoop (
} else { } else {
StackStart = mReservedTopOfApStack; StackStart = mReservedTopOfApStack;
} }
AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoopFunc;
AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFunc;
AsmRelocateApLoopFunc ( AsmRelocateApLoopFunc (
MwaitSupport, MwaitSupport,
CpuMpData->ApTargetCState, CpuMpData->ApTargetCState,
CpuMpData->PmCodeSegment, CpuMpData->PmCodeSegment,
StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE,
(UINTN) &mNumberToFinish, (UINTN)&mNumberToFinish,
CpuMpData->Pm16CodeSegment, CpuMpData->Pm16CodeSegment,
CpuMpData->SevEsAPBuffer, CpuMpData->SevEsAPBuffer,
CpuMpData->WakeupBuffer CpuMpData->WakeupBuffer
@@ -422,15 +430,15 @@ MpInitChangeApLoopCallback (
CpuPause (); CpuPause ();
} }
if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN) -1)) { if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN)-1)) {
// //
// There are APs present. Re-use reserved memory area below 1MB from // There are APs present. Re-use reserved memory area below 1MB from
// WakeupBuffer as the area to be used for transitioning to 16-bit mode // WakeupBuffer as the area to be used for transitioning to 16-bit mode
// in support of booting of the AP by an OS. // in support of booting of the AP by an OS.
// //
CopyMem ( CopyMem (
(VOID *) CpuMpData->WakeupBuffer, (VOID *)CpuMpData->WakeupBuffer,
(VOID *) (CpuMpData->AddressMap.RendezvousFunnelAddress + (VOID *)(CpuMpData->AddressMap.RendezvousFunnelAddress +
CpuMpData->AddressMap.SwitchToRealPM16ModeOffset), CpuMpData->AddressMap.SwitchToRealPM16ModeOffset),
CpuMpData->AddressMap.SwitchToRealPM16ModeSize CpuMpData->AddressMap.SwitchToRealPM16ModeSize
); );
@@ -485,7 +493,7 @@ InitMpGlobalData (
// //
CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; ++Index) { for (Index = 0; Index < CpuMpData->CpuCount; ++Index) {
if (CpuInfoInHob != NULL && CpuInfoInHob[Index].ApTopOfStack != 0) { if ((CpuInfoInHob != NULL) && (CpuInfoInHob[Index].ApTopOfStack != 0)) {
StackBase = (UINTN)CpuInfoInHob[Index].ApTopOfStack - CpuMpData->CpuApStackSize; StackBase = (UINTN)CpuInfoInHob[Index].ApTopOfStack - CpuMpData->CpuApStackSize;
} else { } else {
StackBase = CpuMpData->Buffer + Index * CpuMpData->CpuApStackSize; StackBase = CpuMpData->Buffer + Index * CpuMpData->CpuApStackSize;
@@ -501,8 +509,12 @@ InitMpGlobalData (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n", DEBUG ((
(UINT64)StackBase, (UINT64)Index)); DEBUG_INFO,
"Stack Guard set at %lx [cpu%lu]!\n",
(UINT64)StackBase,
(UINT64)Index
));
} }
} }
@@ -514,9 +526,11 @@ InitMpGlobalData (
// Allocating it in advance since memory services are not available in // Allocating it in advance since memory services are not available in
// Exit Boot Services callback function. // Exit Boot Services callback function.
// //
ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES ( ApSafeBufferSize = EFI_PAGES_TO_SIZE (
EFI_SIZE_TO_PAGES (
CpuMpData->AddressMap.RelocateApLoopFuncSize CpuMpData->AddressMap.RelocateApLoopFuncSize
)); )
);
Address = BASE_4GB - 1; Address = BASE_4GB - 1;
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
@@ -526,7 +540,7 @@ InitMpGlobalData (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
mReservedApLoopFunc = (VOID *) (UINTN) Address; mReservedApLoopFunc = (VOID *)(UINTN)Address;
ASSERT (mReservedApLoopFunc != NULL); ASSERT (mReservedApLoopFunc != NULL);
// //
@@ -545,9 +559,11 @@ InitMpGlobalData (
); );
} }
ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES ( ApSafeBufferSize = EFI_PAGES_TO_SIZE (
EFI_SIZE_TO_PAGES (
CpuMpData->CpuCount * AP_SAFE_STACK_SIZE CpuMpData->CpuCount * AP_SAFE_STACK_SIZE
)); )
);
Address = BASE_4GB - 1; Address = BASE_4GB - 1;
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
@@ -557,7 +573,7 @@ InitMpGlobalData (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
mReservedTopOfApStack = (UINTN) Address + ApSafeBufferSize; mReservedTopOfApStack = (UINTN)Address + ApSafeBufferSize;
ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) == 0); ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) == 0);
CopyMem ( CopyMem (
mReservedApLoopFunc, mReservedApLoopFunc,
@@ -861,7 +877,7 @@ MpInitLibSwitchBSP (
// //
// Locate Timer Arch Protocol // Locate Timer Arch Protocol
// //
Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **) &Timer); Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **)&Timer);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Timer = NULL; Timer = NULL;
} }

66
UefiCpuPkg/Library/MpInitLib/Microcode.c
View File

@@ -47,7 +47,7 @@ MicrocodeDetect (
GetProcessorMicrocodeCpuId (&MicrocodeCpuId); GetProcessorMicrocodeCpuId (&MicrocodeCpuId);
if (ProcessorNumber != (UINTN) CpuMpData->BspNumber) { if (ProcessorNumber != (UINTN)CpuMpData->BspNumber) {
// //
// Direct use microcode of BSP if AP is the same as BSP. // Direct use microcode of BSP if AP is the same as BSP.
// Assume BSP calls this routine() before AP. // Assume BSP calls this routine() before AP.
@@ -55,8 +55,9 @@ MicrocodeDetect (
BspData = &(CpuMpData->CpuData[CpuMpData->BspNumber]); BspData = &(CpuMpData->CpuData[CpuMpData->BspNumber]);
if ((BspData->ProcessorSignature == MicrocodeCpuId.ProcessorSignature) && if ((BspData->ProcessorSignature == MicrocodeCpuId.ProcessorSignature) &&
(BspData->PlatformId == MicrocodeCpuId.PlatformId) && (BspData->PlatformId == MicrocodeCpuId.PlatformId) &&
(BspData->MicrocodeEntryAddr != 0)) { (BspData->MicrocodeEntryAddr != 0))
LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN) BspData->MicrocodeEntryAddr; {
LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN)BspData->MicrocodeEntryAddr;
LatestRevision = LatestMicrocode->UpdateRevision; LatestRevision = LatestMicrocode->UpdateRevision;
goto LoadMicrocode; goto LoadMicrocode;
} }
@@ -69,11 +70,11 @@ MicrocodeDetect (
// //
LatestRevision = 0; LatestRevision = 0;
LatestMicrocode = NULL; LatestMicrocode = NULL;
Microcode = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress; Microcode = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress;
MicrocodeEnd = (UINTN) Microcode + (UINTN) CpuMpData->MicrocodePatchRegionSize; MicrocodeEnd = (UINTN)Microcode + (UINTN)CpuMpData->MicrocodePatchRegionSize;
do { do {
if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN) Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) { if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN)Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) {
// //
// It is the padding data between the microcode patches for microcode patches alignment. // It is the padding data between the microcode patches for microcode patches alignment.
// Because the microcode patch is the multiple of 1-KByte, the padding data should not // Because the microcode patch is the multiple of 1-KByte, the padding data should not
@@ -81,14 +82,15 @@ MicrocodeDetect (
// alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to // alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to
// find the next possible microcode patch header. // find the next possible microcode patch header.
// //
Microcode = (CPU_MICROCODE_HEADER *) ((UINTN) Microcode + SIZE_1KB); Microcode = (CPU_MICROCODE_HEADER *)((UINTN)Microcode + SIZE_1KB);
continue; continue;
} }
LatestMicrocode = Microcode; LatestMicrocode = Microcode;
LatestRevision = LatestMicrocode->UpdateRevision; LatestRevision = LatestMicrocode->UpdateRevision;
Microcode = (CPU_MICROCODE_HEADER *) (((UINTN) Microcode) + GetMicrocodeLength (Microcode)); Microcode = (CPU_MICROCODE_HEADER *)(((UINTN)Microcode) + GetMicrocodeLength (Microcode));
} while ((UINTN) Microcode < MicrocodeEnd); } while ((UINTN)Microcode < MicrocodeEnd);
LoadMicrocode: LoadMicrocode:
if (LatestRevision != 0) { if (LatestRevision != 0) {
@@ -97,7 +99,7 @@ LoadMicrocode:
// patch header) for each processor even it's the same as the loaded one. // patch header) for each processor even it's the same as the loaded one.
// It will be used when building the microcode patch cache HOB. // It will be used when building the microcode patch cache HOB.
// //
CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN) LatestMicrocode; CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN)LatestMicrocode;
} }
if (LatestRevision > GetProcessorMicrocodeSignature ()) { if (LatestRevision > GetProcessorMicrocodeSignature ()) {
@@ -109,6 +111,7 @@ LoadMicrocode:
// //
LoadMicrocode (LatestMicrocode); LoadMicrocode (LatestMicrocode);
} }
// //
// It's possible that the microcode fails to load. Just capture the CPU microcode revision after loading. // It's possible that the microcode fails to load. Just capture the CPU microcode revision after loading.
// //
@@ -152,7 +155,7 @@ ShadowMicrocodePatchWorker (
for (Walker = MicrocodePatchInRam, Index = 0; Index < PatchCount; Index++) { for (Walker = MicrocodePatchInRam, Index = 0; Index < PatchCount; Index++) {
CopyMem ( CopyMem (
Walker, Walker,
(VOID *) Patches[Index].Address, (VOID *)Patches[Index].Address,
Patches[Index].Size Patches[Index].Size
); );
Walker += Patches[Index].Size; Walker += Patches[Index].Size;
@@ -161,13 +164,15 @@ ShadowMicrocodePatchWorker (
// //
// Update the microcode patch related fields in CpuMpData // Update the microcode patch related fields in CpuMpData
// //
CpuMpData->MicrocodePatchAddress = (UINTN) MicrocodePatchInRam; CpuMpData->MicrocodePatchAddress = (UINTN)MicrocodePatchInRam;
CpuMpData->MicrocodePatchRegionSize = TotalLoadSize; CpuMpData->MicrocodePatchRegionSize = TotalLoadSize;
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n", "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
__FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize __FUNCTION__,
CpuMpData->MicrocodePatchAddress,
CpuMpData->MicrocodePatchRegionSize
)); ));
return; return;
@@ -203,10 +208,10 @@ ShadowMicrocodePatchByPcd (
CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress); CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress);
CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize); CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);
MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress; MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress;
MicrocodeEnd = (UINTN) MicrocodeEntryPoint + MicrocodeEnd = (UINTN)MicrocodeEntryPoint +
(UINTN) CpuMpData->MicrocodePatchRegionSize; (UINTN)CpuMpData->MicrocodePatchRegionSize;
if ((MicrocodeEntryPoint == NULL) || ((UINTN) MicrocodeEntryPoint == MicrocodeEnd)) { if ((MicrocodeEntryPoint == NULL) || ((UINTN)MicrocodeEntryPoint == MicrocodeEnd)) {
// //
// There is no microcode patches // There is no microcode patches
// //
@@ -242,7 +247,7 @@ ShadowMicrocodePatchByPcd (
do { do {
Valid = IsValidMicrocode ( Valid = IsValidMicrocode (
MicrocodeEntryPoint, MicrocodeEntryPoint,
MicrocodeEnd - (UINTN) MicrocodeEntryPoint, MicrocodeEnd - (UINTN)MicrocodeEntryPoint,
0, 0,
MicrocodeCpuIds, MicrocodeCpuIds,
CpuMpData->CpuCount, CpuMpData->CpuCount,
@@ -252,7 +257,7 @@ ShadowMicrocodePatchByPcd (
// //
// Padding data between the microcode patches, skip 1KB to check next entry. // Padding data between the microcode patches, skip 1KB to check next entry.
// //
MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + SIZE_1KB); MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(((UINTN)MicrocodeEntryPoint) + SIZE_1KB);
continue; continue;
} }
@@ -277,6 +282,7 @@ ShadowMicrocodePatchByPcd (
if (PatchInfoBuffer == NULL) { if (PatchInfoBuffer == NULL) {
goto OnExit; goto OnExit;
} }
MaxPatchNumber = MaxPatchNumber * 2; MaxPatchNumber = MaxPatchNumber * 2;
} }
@@ -285,21 +291,23 @@ ShadowMicrocodePatchByPcd (
// //
// Store the information of this microcode patch // Store the information of this microcode patch
// //
PatchInfoBuffer[PatchCount - 1].Address = (UINTN) MicrocodeEntryPoint; PatchInfoBuffer[PatchCount - 1].Address = (UINTN)MicrocodeEntryPoint;
PatchInfoBuffer[PatchCount - 1].Size = TotalSize; PatchInfoBuffer[PatchCount - 1].Size = TotalSize;
TotalLoadSize += TotalSize; TotalLoadSize += TotalSize;
// //
// Process the next microcode patch // Process the next microcode patch
// //
MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) ((UINTN) MicrocodeEntryPoint + TotalSize); MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)((UINTN)MicrocodeEntryPoint + TotalSize);
} while ((UINTN) MicrocodeEntryPoint < MicrocodeEnd); } while ((UINTN)MicrocodeEntryPoint < MicrocodeEnd);
if (PatchCount != 0) { if (PatchCount != 0) {
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n", "%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n",
__FUNCTION__, PatchCount, TotalLoadSize __FUNCTION__,
PatchCount,
TotalLoadSize
)); ));
ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, TotalLoadSize); ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, TotalLoadSize);
@@ -309,6 +317,7 @@ OnExit:
if (PatchInfoBuffer != NULL) { if (PatchInfoBuffer != NULL) {
FreePool (PatchInfoBuffer); FreePool (PatchInfoBuffer);
} }
FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDKII_PEI_MICROCODE_CPU_ID))); FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDKII_PEI_MICROCODE_CPU_ID)));
} }
@@ -356,7 +365,7 @@ GetMicrocodePatchInfoFromHob (
GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid); GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid);
if (GuidHob == NULL) { if (GuidHob == NULL) {
DEBUG((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__)); DEBUG ((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__));
return FALSE; return FALSE;
} }
@@ -365,9 +374,12 @@ GetMicrocodePatchInfoFromHob (
*Address = MicrocodePathHob->MicrocodePatchAddress; *Address = MicrocodePathHob->MicrocodePatchAddress;
*RegionSize = MicrocodePathHob->MicrocodePatchRegionSize; *RegionSize = MicrocodePathHob->MicrocodePatchRegionSize;
DEBUG(( DEBUG ((
DEBUG_INFO, "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n", DEBUG_INFO,
__FUNCTION__, *Address, *RegionSize "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n",
__FUNCTION__,
*Address,
*RegionSize
)); ));
return TRUE; return TRUE;

275
UefiCpuPkg/Library/MpInitLib/MpLib.c
View File

@@ -15,7 +15,6 @@
EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID; EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;
/** /**
The function will check if BSP Execute Disable is enabled. The function will check if BSP Execute Disable is enabled.
@@ -83,7 +82,7 @@ FutureBSPProc (
{ {
CPU_MP_DATA *DataInHob; CPU_MP_DATA *DataInHob;
DataInHob = (CPU_MP_DATA *) Buffer; DataInHob = (CPU_MP_DATA *)Buffer;
AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo); AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo);
} }
@@ -239,8 +238,9 @@ RestoreVolatileRegisters (
AsmWriteGdtr (&VolatileRegisters->Gdtr); AsmWriteGdtr (&VolatileRegisters->Gdtr);
AsmWriteIdtr (&VolatileRegisters->Idtr); AsmWriteIdtr (&VolatileRegisters->Idtr);
if (VolatileRegisters->Tr != 0 && if ((VolatileRegisters->Tr != 0) &&
VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) { (VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit))
{
Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base + Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +
VolatileRegisters->Tr); VolatileRegisters->Tr);
if (Tss->Bits.P == 1) { if (Tss->Bits.P == 1) {
@@ -341,7 +341,7 @@ SortApicId (
volatile UINT32 *StartupApSignal; volatile UINT32 *StartupApSignal;
ApCount = CpuMpData->CpuCount - 1; ApCount = CpuMpData->CpuCount - 1;
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
if (ApCount != 0) { if (ApCount != 0) {
for (Index1 = 0; Index1 < ApCount; Index1++) { for (Index1 = 0; Index1 < ApCount; Index1++) {
Index3 = Index1; Index3 = Index1;
@@ -355,6 +355,7 @@ SortApicId (
ApicId = CpuInfoInHob[Index2].ApicId; ApicId = CpuInfoInHob[Index2].ApicId;
} }
} }
if (Index3 != Index1) { if (Index3 != Index1) {
CopyMem (&CpuInfo, &CpuInfoInHob[Index3], sizeof (CPU_INFO_IN_HOB)); CopyMem (&CpuInfo, &CpuInfoInHob[Index3], sizeof (CPU_INFO_IN_HOB));
CopyMem ( CopyMem (
@@ -380,7 +381,7 @@ SortApicId (
ApicId = GetInitialApicId (); ApicId = GetInitialApicId ();
for (Index1 = 0; Index1 < CpuMpData->CpuCount; Index1++) { for (Index1 = 0; Index1 < CpuMpData->CpuCount; Index1++) {
if (CpuInfoInHob[Index1].ApicId == ApicId) { if (CpuInfoInHob[Index1].ApicId == ApicId) {
CpuMpData->BspNumber = (UINT32) Index1; CpuMpData->BspNumber = (UINT32)Index1;
break; break;
} }
} }
@@ -416,7 +417,7 @@ ApInitializeSync (
UINTN ProcessorNumber; UINTN ProcessorNumber;
EFI_STATUS Status; EFI_STATUS Status;
CpuMpData = (CPU_MP_DATA *) Buffer; CpuMpData = (CPU_MP_DATA *)Buffer;
Status = GetProcessorNumber (CpuMpData, &ProcessorNumber); Status = GetProcessorNumber (CpuMpData, &ProcessorNumber);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// //
@@ -449,11 +450,11 @@ GetProcessorNumber (
CPU_INFO_IN_HOB *CpuInfoInHob; CPU_INFO_IN_HOB *CpuInfoInHob;
UINT32 CurrentApicId; UINT32 CurrentApicId;
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
TotalProcessorNumber = CpuMpData->CpuCount; TotalProcessorNumber = CpuMpData->CpuCount;
CurrentApicId = GetApicId (); CurrentApicId = GetApicId ();
for (Index = 0; Index < TotalProcessorNumber; Index ++) { for (Index = 0; Index < TotalProcessorNumber; Index++) {
if (CpuInfoInHob[Index].ApicId == CurrentApicId) { if (CpuInfoInHob[Index].ApicId == CurrentApicId) {
*ProcessorNumber = Index; *ProcessorNumber = Index;
return EFI_SUCCESS; return EFI_SUCCESS;
@@ -504,7 +505,7 @@ CollectProcessorCount (
// //
X2Apic = TRUE; X2Apic = TRUE;
} else { } else {
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; Index++) { for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
if (CpuInfoInHob[Index].InitialApicId >= 0xFF) { if (CpuInfoInHob[Index].InitialApicId >= 0xFF) {
X2Apic = TRUE; X2Apic = TRUE;
@@ -525,6 +526,7 @@ CollectProcessorCount (
while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) { while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {
CpuPause (); CpuPause ();
} }
// //
// Enable x2APIC on BSP // Enable x2APIC on BSP
// //
@@ -536,6 +538,7 @@ CollectProcessorCount (
SetApState (&CpuMpData->CpuData[Index], CpuStateIdle); SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);
} }
} }
DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ())); DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ()));
// //
// Sort BSP/Aps by CPU APIC ID in ascending order // Sort BSP/Aps by CPU APIC ID in ascending order
@@ -567,7 +570,7 @@ InitializeApData (
CPU_INFO_IN_HOB *CpuInfoInHob; CPU_INFO_IN_HOB *CpuInfoInHob;
MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId (); CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();
CpuInfoInHob[ProcessorNumber].ApicId = GetApicId (); CpuInfoInHob[ProcessorNumber].ApicId = GetApicId ();
CpuInfoInHob[ProcessorNumber].Health = BistData; CpuInfoInHob[ProcessorNumber].Health = BistData;
@@ -592,7 +595,7 @@ InitializeApData (
NULL NULL
); );
InitializeSpinLock(&CpuMpData->CpuData[ProcessorNumber].ApLock); InitializeSpinLock (&CpuMpData->CpuData[ProcessorNumber].ApLock);
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle); SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);
} }
@@ -613,18 +616,21 @@ GetProtectedMode16CS (
UINTN GdtEntryCount; UINTN GdtEntryCount;
UINT16 Index; UINT16 Index;
Index = (UINT16) -1; Index = (UINT16)-1;
AsmReadGdtr (&GdtrDesc); AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) { for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0 && if ((GdtEntry->Bits.L == 0) &&
GdtEntry->Bits.DB == 0 && (GdtEntry->Bits.DB == 0) &&
GdtEntry->Bits.Type > 8) { (GdtEntry->Bits.Type > 8))
{
break; break;
} }
GdtEntry++; GdtEntry++;
} }
ASSERT (Index != GdtEntryCount); ASSERT (Index != GdtEntryCount);
return Index * 8; return Index * 8;
} }
@@ -646,18 +652,21 @@ GetProtectedMode32CS (
UINTN GdtEntryCount; UINTN GdtEntryCount;
UINT16 Index; UINT16 Index;
Index = (UINT16) -1; Index = (UINT16)-1;
AsmReadGdtr (&GdtrDesc); AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) { for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0 && if ((GdtEntry->Bits.L == 0) &&
GdtEntry->Bits.DB == 1 && (GdtEntry->Bits.DB == 1) &&
GdtEntry->Bits.Type > 8) { (GdtEntry->Bits.Type > 8))
{
break; break;
} }
GdtEntry++; GdtEntry++;
} }
ASSERT (Index != GdtEntryCount); ASSERT (Index != GdtEntryCount);
return Index * 8; return Index * 8;
} }
@@ -692,9 +701,9 @@ MpInitLibSevEsAPReset (
Code32 = GetProtectedMode32CS (); Code32 = GetProtectedMode32CS ();
if (CpuMpData->WakeupBufferHigh != 0) { if (CpuMpData->WakeupBufferHigh != 0) {
APResetFn = (AP_RESET *) (CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset); APResetFn = (AP_RESET *)(CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset);
} else { } else {
APResetFn = (AP_RESET *) (CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset); APResetFn = (AP_RESET *)(CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset);
} }
BufferStart = CpuMpData->MpCpuExchangeInfo->BufferStart; BufferStart = CpuMpData->MpCpuExchangeInfo->BufferStart;
@@ -754,7 +763,7 @@ ApWakeupFunction (
// This is first time AP wakeup, get BIST information from AP stack // This is first time AP wakeup, get BIST information from AP stack
// //
ApTopOfStack = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize; ApTopOfStack = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize;
BistData = *(UINT32 *) ((UINTN) ApTopOfStack - sizeof (UINTN)); BistData = *(UINT32 *)((UINTN)ApTopOfStack - sizeof (UINTN));
// //
// CpuMpData->CpuData[0].VolatileRegisters is initialized based on BSP environment, // CpuMpData->CpuData[0].VolatileRegisters is initialized based on BSP environment,
// to initialize AP in InitConfig path. // to initialize AP in InitConfig path.
@@ -773,7 +782,7 @@ ApWakeupFunction (
// //
ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal; ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
InterlockedCompareExchange32 ( InterlockedCompareExchange32 (
(UINT32 *) ApStartupSignalBuffer, (UINT32 *)ApStartupSignalBuffer,
WAKEUP_AP_SIGNAL, WAKEUP_AP_SIGNAL,
0 0
); );
@@ -806,7 +815,7 @@ ApWakeupFunction (
if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateReady) { if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateReady) {
Procedure = (EFI_AP_PROCEDURE)CpuMpData->CpuData[ProcessorNumber].ApFunction; Procedure = (EFI_AP_PROCEDURE)CpuMpData->CpuData[ProcessorNumber].ApFunction;
Parameter = (VOID *) CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument; Parameter = (VOID *)CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument;
if (Procedure != NULL) { if (Procedure != NULL) {
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateBusy); SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateBusy);
// //
@@ -817,7 +826,7 @@ ApWakeupFunction (
// Invoke AP function here // Invoke AP function here
// //
Procedure (Parameter); Procedure (Parameter);
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
if (CpuMpData->SwitchBspFlag) { if (CpuMpData->SwitchBspFlag) {
// //
// Re-get the processor number due to BSP/AP maybe exchange in AP function // Re-get the processor number due to BSP/AP maybe exchange in AP function
@@ -828,8 +837,9 @@ ApWakeupFunction (
ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal; ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack; CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;
} else { } else {
if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () || if ((CpuInfoInHob[ProcessorNumber].ApicId != GetApicId ()) ||
CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()) { (CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()))
{
if (CurrentApicMode != GetApicMode ()) { if (CurrentApicMode != GetApicMode ()) {
// //
// If APIC mode change happened during AP function execution, // If APIC mode change happened during AP function execution,
@@ -847,6 +857,7 @@ ApWakeupFunction (
} }
} }
} }
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateFinished); SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateFinished);
} }
} }
@@ -861,7 +872,7 @@ ApWakeupFunction (
// //
// AP finished executing C code // AP finished executing C code
// //
InterlockedIncrement ((UINT32 *) &CpuMpData->FinishedCount); InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount);
if (CpuMpData->InitFlag == ApInitConfig) { if (CpuMpData->InitFlag == ApInitConfig) {
// //
@@ -870,7 +881,7 @@ ApWakeupFunction (
// performs another INIT-SIPI-SIPI sequence. // performs another INIT-SIPI-SIPI sequence.
// //
if (!CpuMpData->SevEsIsEnabled) { if (!CpuMpData->SevEsIsEnabled) {
InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting); InterlockedDecrement ((UINT32 *)&CpuMpData->MpCpuExchangeInfo->NumApsExecuting);
} }
} }
@@ -890,7 +901,7 @@ ApWakeupFunction (
BOOLEAN DoDecrement; BOOLEAN DoDecrement;
BOOLEAN InterruptState; BOOLEAN InterruptState;
DoDecrement = (BOOLEAN) (CpuMpData->InitFlag == ApInitConfig); DoDecrement = (BOOLEAN)(CpuMpData->InitFlag == ApInitConfig);
while (TRUE) { while (TRUE) {
Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB); Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
@@ -905,7 +916,7 @@ ApWakeupFunction (
// Perform the delayed decrement just before issuing the first // Perform the delayed decrement just before issuing the first
// VMGEXIT with AP_RESET_HOLD. // VMGEXIT with AP_RESET_HOLD.
// //
InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting); InterlockedDecrement ((UINT32 *)&CpuMpData->MpCpuExchangeInfo->NumApsExecuting);
} }
Status = VmgExit (Ghcb, SVM_EXIT_AP_RESET_HOLD, 0, 0); Status = VmgExit (Ghcb, SVM_EXIT_AP_RESET_HOLD, 0, 0);
@@ -928,16 +939,18 @@ ApWakeupFunction (
} else { } else {
CpuSleep (); CpuSleep ();
} }
CpuPause (); CpuPause ();
} }
} }
while (TRUE) { while (TRUE) {
DisableInterrupts (); DisableInterrupts ();
if (CpuMpData->ApLoopMode == ApInMwaitLoop) { if (CpuMpData->ApLoopMode == ApInMwaitLoop) {
// //
// Place AP in MWAIT-loop // Place AP in MWAIT-loop
// //
AsmMonitor ((UINTN) ApStartupSignalBuffer, 0, 0); AsmMonitor ((UINTN)ApStartupSignalBuffer, 0, 0);
if (*ApStartupSignalBuffer != WAKEUP_AP_SIGNAL) { if (*ApStartupSignalBuffer != WAKEUP_AP_SIGNAL) {
// //
// Check AP start-up signal again. // Check AP start-up signal again.
@@ -981,10 +994,11 @@ WaitApWakeup (
// Otherwise, write StartupApSignal again till AP waken up. // Otherwise, write StartupApSignal again till AP waken up.
// //
while (InterlockedCompareExchange32 ( while (InterlockedCompareExchange32 (
(UINT32 *) ApStartupSignalBuffer, (UINT32 *)ApStartupSignalBuffer,
WAKEUP_AP_SIGNAL, WAKEUP_AP_SIGNAL,
WAKEUP_AP_SIGNAL WAKEUP_AP_SIGNAL
) != 0) { ) != 0)
{
CpuPause (); CpuPause ();
} }
} }
@@ -1016,11 +1030,11 @@ FillExchangeInfoData (
ExchangeInfo->Cr3 = AsmReadCr3 (); ExchangeInfo->Cr3 = AsmReadCr3 ();
ExchangeInfo->CFunction = (UINTN) ApWakeupFunction; ExchangeInfo->CFunction = (UINTN)ApWakeupFunction;
ExchangeInfo->ApIndex = 0; ExchangeInfo->ApIndex = 0;
ExchangeInfo->NumApsExecuting = 0; ExchangeInfo->NumApsExecuting = 0;
ExchangeInfo->InitFlag = (UINTN) CpuMpData->InitFlag; ExchangeInfo->InitFlag = (UINTN)CpuMpData->InitFlag;
ExchangeInfo->CpuInfo = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; ExchangeInfo->CpuInfo = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
ExchangeInfo->CpuMpData = CpuMpData; ExchangeInfo->CpuMpData = CpuMpData;
ExchangeInfo->EnableExecuteDisable = IsBspExecuteDisableEnabled (); ExchangeInfo->EnableExecuteDisable = IsBspExecuteDisableEnabled ();
@@ -1036,17 +1050,17 @@ FillExchangeInfoData (
// check whether platform wants to enable it. // check whether platform wants to enable it.
// //
Cr4.UintN = AsmReadCr4 (); Cr4.UintN = AsmReadCr4 ();
ExchangeInfo->Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); ExchangeInfo->Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging)); DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging));
ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled; ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;
ExchangeInfo->GhcbBase = (UINTN) CpuMpData->GhcbBase; ExchangeInfo->GhcbBase = (UINTN)CpuMpData->GhcbBase;
// //
// Get the BSP's data of GDT and IDT // Get the BSP's data of GDT and IDT
// //
AsmReadGdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->GdtrProfile); AsmReadGdtr ((IA32_DESCRIPTOR *)&ExchangeInfo->GdtrProfile);
AsmReadIdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->IdtrProfile); AsmReadIdtr ((IA32_DESCRIPTOR *)&ExchangeInfo->IdtrProfile);
// //
// Find a 32-bit code segment // Find a 32-bit code segment
@@ -1054,11 +1068,12 @@ FillExchangeInfoData (
Selector = (IA32_SEGMENT_DESCRIPTOR *)ExchangeInfo->GdtrProfile.Base; Selector = (IA32_SEGMENT_DESCRIPTOR *)ExchangeInfo->GdtrProfile.Base;
Size = ExchangeInfo->GdtrProfile.Limit + 1; Size = ExchangeInfo->GdtrProfile.Limit + 1;
while (Size > 0) { while (Size > 0) {
if (Selector->Bits.L == 0 && Selector->Bits.Type >= 8) { if ((Selector->Bits.L == 0) && (Selector->Bits.Type >= 8)) {
ExchangeInfo->ModeTransitionSegment = ExchangeInfo->ModeTransitionSegment =
(UINT16)((UINTN)Selector - ExchangeInfo->GdtrProfile.Base); (UINT16)((UINTN)Selector - ExchangeInfo->GdtrProfile.Base);
break; break;
} }
Selector += 1; Selector += 1;
Size -= sizeof (IA32_SEGMENT_DESCRIPTOR); Size -= sizeof (IA32_SEGMENT_DESCRIPTOR);
} }
@@ -1111,18 +1126,18 @@ TimedWaitForApFinish (
@param[in] CpuMpData The pointer to CPU MP Data structure. @param[in] CpuMpData The pointer to CPU MP Data structure.
**/ **/
VOID VOID
BackupAndPrepareWakeupBuffer( BackupAndPrepareWakeupBuffer (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
) )
{ {
CopyMem ( CopyMem (
(VOID *) CpuMpData->BackupBuffer, (VOID *)CpuMpData->BackupBuffer,
(VOID *) CpuMpData->WakeupBuffer, (VOID *)CpuMpData->WakeupBuffer,
CpuMpData->BackupBufferSize CpuMpData->BackupBufferSize
); );
CopyMem ( CopyMem (
(VOID *) CpuMpData->WakeupBuffer, (VOID *)CpuMpData->WakeupBuffer,
(VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress, (VOID *)CpuMpData->AddressMap.RendezvousFunnelAddress,
CpuMpData->AddressMap.RendezvousFunnelSize + CpuMpData->AddressMap.RendezvousFunnelSize +
CpuMpData->AddressMap.SwitchToRealSize CpuMpData->AddressMap.SwitchToRealSize
); );
@@ -1134,13 +1149,13 @@ BackupAndPrepareWakeupBuffer(
@param[in] CpuMpData The pointer to CPU MP Data structure. @param[in] CpuMpData The pointer to CPU MP Data structure.
**/ **/
VOID VOID
RestoreWakeupBuffer( RestoreWakeupBuffer (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
) )
{ {
CopyMem ( CopyMem (
(VOID *) CpuMpData->WakeupBuffer, (VOID *)CpuMpData->WakeupBuffer,
(VOID *) CpuMpData->BackupBuffer, (VOID *)CpuMpData->BackupBuffer,
CpuMpData->BackupBufferSize CpuMpData->BackupBufferSize
); );
} }
@@ -1180,11 +1195,11 @@ AllocateResetVector (
UINTN ApResetVectorSize; UINTN ApResetVectorSize;
UINTN ApResetStackSize; UINTN ApResetStackSize;
if (CpuMpData->WakeupBuffer == (UINTN) -1) { if (CpuMpData->WakeupBuffer == (UINTN)-1) {
ApResetVectorSize = GetApResetVectorSize (&CpuMpData->AddressMap); ApResetVectorSize = GetApResetVectorSize (&CpuMpData->AddressMap);
CpuMpData->WakeupBuffer = GetWakeupBuffer (ApResetVectorSize); CpuMpData->WakeupBuffer = GetWakeupBuffer (ApResetVectorSize);
CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)
(CpuMpData->WakeupBuffer + (CpuMpData->WakeupBuffer +
CpuMpData->AddressMap.RendezvousFunnelSize + CpuMpData->AddressMap.RendezvousFunnelSize +
CpuMpData->AddressMap.SwitchToRealSize); CpuMpData->AddressMap.SwitchToRealSize);
@@ -1228,6 +1243,7 @@ AllocateResetVector (
} }
} }
} }
BackupAndPrepareWakeupBuffer (CpuMpData); BackupAndPrepareWakeupBuffer (CpuMpData);
} }
@@ -1262,7 +1278,7 @@ AllocateSevEsAPMemory (
IN OUT CPU_MP_DATA *CpuMpData IN OUT CPU_MP_DATA *CpuMpData
) )
{ {
if (CpuMpData->SevEsAPBuffer == (UINTN) -1) { if (CpuMpData->SevEsAPBuffer == (UINTN)-1) {
CpuMpData->SevEsAPBuffer = CpuMpData->SevEsAPBuffer =
CpuMpData->SevEsIsEnabled ? GetSevEsAPMemory () : 0; CpuMpData->SevEsIsEnabled ? GetSevEsAPMemory () : 0;
} }
@@ -1282,7 +1298,7 @@ SetSevEsJumpTable (
UINT32 Offset, InsnByte; UINT32 Offset, InsnByte;
UINT8 LoNib, HiNib; UINT8 LoNib, HiNib;
JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32 (PcdSevEsWorkAreaBase); JmpFar = (SEV_ES_AP_JMP_FAR *)(UINTN)FixedPcdGet32 (PcdSevEsWorkAreaBase);
ASSERT (JmpFar != NULL); ASSERT (JmpFar != NULL);
// //
@@ -1292,8 +1308,8 @@ SetSevEsJumpTable (
// //
Offset = FixedPcdGet32 (PcdSevEsWorkAreaBase); Offset = FixedPcdGet32 (PcdSevEsWorkAreaBase);
Offset += sizeof (JmpFar->InsnBuffer); Offset += sizeof (JmpFar->InsnBuffer);
LoNib = (UINT8) Offset; LoNib = (UINT8)Offset;
HiNib = (UINT8) (Offset >> 8); HiNib = (UINT8)(Offset >> 8);
// //
// Program the workarea (which is the initial AP boot address) with // Program the workarea (which is the initial AP boot address) with
@@ -1314,7 +1330,7 @@ SetSevEsJumpTable (
// 16-byte aligned, so Rip is set to 0). // 16-byte aligned, so Rip is set to 0).
// //
JmpFar->Rip = 0; JmpFar->Rip = 0;
JmpFar->Segment = (UINT16) (SipiVector >> 4); JmpFar->Segment = (UINT16)(SipiVector >> 4);
} }
/** /**
@@ -1348,7 +1364,8 @@ WakeUpAP (
ResetVectorRequired = FALSE; ResetVectorRequired = FALSE;
if (CpuMpData->WakeUpByInitSipiSipi || if (CpuMpData->WakeUpByInitSipiSipi ||
CpuMpData->InitFlag != ApInitDone) { (CpuMpData->InitFlag != ApInitDone))
{
ResetVectorRequired = TRUE; ResetVectorRequired = TRUE;
AllocateResetVector (CpuMpData); AllocateResetVector (CpuMpData);
AllocateSevEsAPMemory (CpuMpData); AllocateSevEsAPMemory (CpuMpData);
@@ -1375,18 +1392,19 @@ WakeUpAP (
// the AP procedure will be skipped for disabled AP because AP state // the AP procedure will be skipped for disabled AP because AP state
// is not CpuStateReady. // is not CpuStateReady.
// //
if (GetApState (CpuData) == CpuStateDisabled && !WakeUpDisabledAps) { if ((GetApState (CpuData) == CpuStateDisabled) && !WakeUpDisabledAps) {
continue; continue;
} }
CpuData->ApFunction = (UINTN) Procedure; CpuData->ApFunction = (UINTN)Procedure;
CpuData->ApFunctionArgument = (UINTN) ProcedureArgument; CpuData->ApFunctionArgument = (UINTN)ProcedureArgument;
SetApState (CpuData, CpuStateReady); SetApState (CpuData, CpuStateReady);
if (CpuMpData->InitFlag != ApInitConfig) { if (CpuMpData->InitFlag != ApInitConfig) {
*(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL; *(UINT32 *)CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;
} }
} }
} }
if (ResetVectorRequired) { if (ResetVectorRequired) {
// //
// For SEV-ES, the initial AP boot address will be defined by // For SEV-ES, the initial AP boot address will be defined by
@@ -1400,8 +1418,9 @@ WakeUpAP (
// //
// Wakeup all APs // Wakeup all APs
// //
SendInitSipiSipiAllExcludingSelf ((UINT32) ExchangeInfo->BufferStart); SendInitSipiSipiAllExcludingSelf ((UINT32)ExchangeInfo->BufferStart);
} }
if (CpuMpData->InitFlag == ApInitConfig) { if (CpuMpData->InitFlag == ApInitConfig) {
if (PcdGet32 (PcdCpuBootLogicalProcessorNumber) > 0) { if (PcdGet32 (PcdCpuBootLogicalProcessorNumber) > 0) {
// //
@@ -1462,7 +1481,7 @@ WakeUpAP (
); );
while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) { while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) {
CpuPause(); CpuPause ();
} }
} }
} else { } else {
@@ -1478,16 +1497,16 @@ WakeUpAP (
} }
} else { } else {
CpuData = &CpuMpData->CpuData[ProcessorNumber]; CpuData = &CpuMpData->CpuData[ProcessorNumber];
CpuData->ApFunction = (UINTN) Procedure; CpuData->ApFunction = (UINTN)Procedure;
CpuData->ApFunctionArgument = (UINTN) ProcedureArgument; CpuData->ApFunctionArgument = (UINTN)ProcedureArgument;
SetApState (CpuData, CpuStateReady); SetApState (CpuData, CpuStateReady);
// //
// Wakeup specified AP // Wakeup specified AP
// //
ASSERT (CpuMpData->InitFlag != ApInitConfig); ASSERT (CpuMpData->InitFlag != ApInitConfig);
*(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL; *(UINT32 *)CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;
if (ResetVectorRequired) { if (ResetVectorRequired) {
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
// //
// For SEV-ES, the initial AP boot address will be defined by // For SEV-ES, the initial AP boot address will be defined by
@@ -1500,9 +1519,10 @@ WakeUpAP (
SendInitSipiSipi ( SendInitSipiSipi (
CpuInfoInHob[ProcessorNumber].ApicId, CpuInfoInHob[ProcessorNumber].ApicId,
(UINT32) ExchangeInfo->BufferStart (UINT32)ExchangeInfo->BufferStart
); );
} }
// //
// Wait specified AP waken up // Wait specified AP waken up
// //
@@ -1628,25 +1648,30 @@ CheckTimeout (
if (Timeout == 0) { if (Timeout == 0) {
return FALSE; return FALSE;
} }
GetPerformanceCounterProperties (&Start, &End); GetPerformanceCounterProperties (&Start, &End);
Cycle = End - Start; Cycle = End - Start;
if (Cycle < 0) { if (Cycle < 0) {
Cycle = -Cycle; Cycle = -Cycle;
} }
Cycle++; Cycle++;
CurrentTime = GetPerformanceCounter(); CurrentTime = GetPerformanceCounter ();
Delta = (INT64) (CurrentTime - *PreviousTime); Delta = (INT64)(CurrentTime - *PreviousTime);
if (Start > End) { if (Start > End) {
Delta = -Delta; Delta = -Delta;
} }
if (Delta < 0) { if (Delta < 0) {
Delta += Cycle; Delta += Cycle;
} }
*TotalTime += Delta; *TotalTime += Delta;
*PreviousTime = CurrentTime; *PreviousTime = CurrentTime;
if (*TotalTime > Timeout) { if (*TotalTime > Timeout) {
return TRUE; return TRUE;
} }
return FALSE; return FALSE;
} }
@@ -1683,7 +1708,8 @@ TimedWaitForApFinish (
&CpuMpData->CurrentTime, &CpuMpData->CurrentTime,
&CpuMpData->TotalTime, &CpuMpData->TotalTime,
CpuMpData->ExpectedTime CpuMpData->ExpectedTime
)) { ))
{
CpuPause (); CpuPause ();
} }
@@ -1724,6 +1750,7 @@ ResetProcessorToIdleState (
while (CpuMpData->FinishedCount < 1) { while (CpuMpData->FinishedCount < 1) {
CpuPause (); CpuPause ();
} }
CpuMpData->InitFlag = ApInitDone; CpuMpData->InitFlag = ApInitDone;
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle); SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);
@@ -1790,10 +1817,11 @@ CheckThisAP (
// //
// If the AP finishes for StartupThisAP(), return EFI_SUCCESS. // If the AP finishes for StartupThisAP(), return EFI_SUCCESS.
// //
if (GetApState(CpuData) == CpuStateFinished) { if (GetApState (CpuData) == CpuStateFinished) {
if (CpuData->Finished != NULL) { if (CpuData->Finished != NULL) {
*(CpuData->Finished) = TRUE; *(CpuData->Finished) = TRUE;
} }
SetApState (CpuData, CpuStateIdle); SetApState (CpuData, CpuStateIdle);
return EFI_SUCCESS; return EFI_SUCCESS;
} else { } else {
@@ -1804,6 +1832,7 @@ CheckThisAP (
if (CpuData->Finished != NULL) { if (CpuData->Finished != NULL) {
*(CpuData->Finished) = FALSE; *(CpuData->Finished) = FALSE;
} }
// //
// Reset failed AP to idle state // Reset failed AP to idle state
// //
@@ -1812,6 +1841,7 @@ CheckThisAP (
return EFI_TIMEOUT; return EFI_TIMEOUT;
} }
} }
return EFI_NOT_READY; return EFI_NOT_READY;
} }
@@ -1855,10 +1885,10 @@ CheckAllAPs (
// Only BSP and corresponding AP access this unit of CPU Data. This means the AP will not modify the // Only BSP and corresponding AP access this unit of CPU Data. This means the AP will not modify the
// value of state after setting the it to CpuStateIdle, so BSP can safely make use of its value. // value of state after setting the it to CpuStateIdle, so BSP can safely make use of its value.
// //
if (GetApState(CpuData) == CpuStateFinished) { if (GetApState (CpuData) == CpuStateFinished) {
CpuMpData->RunningCount --; CpuMpData->RunningCount--;
CpuMpData->CpuData[ProcessorNumber].Waiting = FALSE; CpuMpData->CpuData[ProcessorNumber].Waiting = FALSE;
SetApState(CpuData, CpuStateIdle); SetApState (CpuData, CpuStateIdle);
// //
// If in Single Thread mode, then search for the next waiting AP for execution. // If in Single Thread mode, then search for the next waiting AP for execution.
@@ -1870,7 +1900,7 @@ CheckAllAPs (
WakeUpAP ( WakeUpAP (
CpuMpData, CpuMpData,
FALSE, FALSE,
(UINT32) NextProcessorNumber, (UINT32)NextProcessorNumber,
CpuMpData->Procedure, CpuMpData->Procedure,
CpuMpData->ProcArguments, CpuMpData->ProcArguments,
TRUE TRUE
@@ -1893,8 +1923,10 @@ CheckAllAPs (
if (CheckTimeout ( if (CheckTimeout (
&CpuMpData->CurrentTime, &CpuMpData->CurrentTime,
&CpuMpData->TotalTime, &CpuMpData->TotalTime,
CpuMpData->ExpectedTime) CpuMpData->ExpectedTime
) { )
)
{
// //
// If FailedCpuList is not NULL, record all failed APs in it. // If FailedCpuList is not NULL, record all failed APs in it.
// //
@@ -1903,6 +1935,7 @@ CheckAllAPs (
AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN)); AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN));
ASSERT (*CpuMpData->FailedCpuList != NULL); ASSERT (*CpuMpData->FailedCpuList != NULL);
} }
ListIndex = 0; ListIndex = 0;
for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) { for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {
@@ -1920,11 +1953,14 @@ CheckAllAPs (
} }
} }
} }
if (CpuMpData->FailedCpuList != NULL) { if (CpuMpData->FailedCpuList != NULL) {
(*CpuMpData->FailedCpuList)[ListIndex] = END_OF_CPU_LIST; (*CpuMpData->FailedCpuList)[ListIndex] = END_OF_CPU_LIST;
} }
return EFI_TIMEOUT; return EFI_TIMEOUT;
} }
return EFI_NOT_READY; return EFI_NOT_READY;
} }
@@ -1967,15 +2003,16 @@ MpInitLibInitialize (
OldCpuMpData = GetCpuMpDataFromGuidedHob (); OldCpuMpData = GetCpuMpDataFromGuidedHob ();
if (OldCpuMpData == NULL) { if (OldCpuMpData == NULL) {
MaxLogicalProcessorNumber = PcdGet32(PcdCpuMaxLogicalProcessorNumber); MaxLogicalProcessorNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);
} else { } else {
MaxLogicalProcessorNumber = OldCpuMpData->CpuCount; MaxLogicalProcessorNumber = OldCpuMpData->CpuCount;
} }
ASSERT (MaxLogicalProcessorNumber != 0); ASSERT (MaxLogicalProcessorNumber != 0);
AsmGetAddressMap (&AddressMap); AsmGetAddressMap (&AddressMap);
ApResetVectorSize = GetApResetVectorSize (&AddressMap); ApResetVectorSize = GetApResetVectorSize (&AddressMap);
ApStackSize = PcdGet32(PcdCpuApStackSize); ApStackSize = PcdGet32 (PcdCpuApStackSize);
ApLoopMode = GetApLoopMode (&MonitorFilterSize); ApLoopMode = GetApLoopMode (&MonitorFilterSize);
// //
@@ -1993,7 +2030,7 @@ MpInitLibInitialize (
MpBuffer = AllocatePages (EFI_SIZE_TO_PAGES (BufferSize)); MpBuffer = AllocatePages (EFI_SIZE_TO_PAGES (BufferSize));
ASSERT (MpBuffer != NULL); ASSERT (MpBuffer != NULL);
ZeroMem (MpBuffer, BufferSize); ZeroMem (MpBuffer, BufferSize);
Buffer = (UINTN) MpBuffer; Buffer = (UINTN)MpBuffer;
// //
// The layout of the Buffer is as below: // The layout of the Buffer is as below:
@@ -2016,31 +2053,33 @@ MpInitLibInitialize (
// CPU_INFO_IN_HOB (N) // CPU_INFO_IN_HOB (N)
// +--------------------+ // +--------------------+
// //
MonitorBuffer = (UINT8 *) (Buffer + ApStackSize * MaxLogicalProcessorNumber); MonitorBuffer = (UINT8 *)(Buffer + ApStackSize * MaxLogicalProcessorNumber);
BackupBufferAddr = (UINTN) MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber; BackupBufferAddr = (UINTN)MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber;
ApIdtBase = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8); ApIdtBase = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8);
CpuMpData = (CPU_MP_DATA *) (ApIdtBase + VolatileRegisters.Idtr.Limit + 1); CpuMpData = (CPU_MP_DATA *)(ApIdtBase + VolatileRegisters.Idtr.Limit + 1);
CpuMpData->Buffer = Buffer; CpuMpData->Buffer = Buffer;
CpuMpData->CpuApStackSize = ApStackSize; CpuMpData->CpuApStackSize = ApStackSize;
CpuMpData->BackupBuffer = BackupBufferAddr; CpuMpData->BackupBuffer = BackupBufferAddr;
CpuMpData->BackupBufferSize = ApResetVectorSize; CpuMpData->BackupBufferSize = ApResetVectorSize;
CpuMpData->WakeupBuffer = (UINTN) -1; CpuMpData->WakeupBuffer = (UINTN)-1;
CpuMpData->CpuCount = 1; CpuMpData->CpuCount = 1;
CpuMpData->BspNumber = 0; CpuMpData->BspNumber = 0;
CpuMpData->WaitEvent = NULL; CpuMpData->WaitEvent = NULL;
CpuMpData->SwitchBspFlag = FALSE; CpuMpData->SwitchBspFlag = FALSE;
CpuMpData->CpuData = (CPU_AP_DATA *) (CpuMpData + 1); CpuMpData->CpuData = (CPU_AP_DATA *)(CpuMpData + 1);
CpuMpData->CpuInfoInHob = (UINT64) (UINTN) (CpuMpData->CpuData + MaxLogicalProcessorNumber); CpuMpData->CpuInfoInHob = (UINT64)(UINTN)(CpuMpData->CpuData + MaxLogicalProcessorNumber);
InitializeSpinLock(&CpuMpData->MpLock); InitializeSpinLock (&CpuMpData->MpLock);
CpuMpData->SevEsIsEnabled = PcdGetBool (PcdSevEsIsEnabled); CpuMpData->SevEsIsEnabled = PcdGetBool (PcdSevEsIsEnabled);
CpuMpData->SevEsAPBuffer = (UINTN) -1; CpuMpData->SevEsAPBuffer = (UINTN)-1;
CpuMpData->GhcbBase = PcdGet64 (PcdGhcbBase); CpuMpData->GhcbBase = PcdGet64 (PcdGhcbBase);
// //
// Make sure no memory usage outside of the allocated buffer. // Make sure no memory usage outside of the allocated buffer.
// //
ASSERT ((CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) == ASSERT (
Buffer + BufferSize); (CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) ==
Buffer + BufferSize
);
// //
// Duplicate BSP's IDT to APs. // Duplicate BSP's IDT to APs.
@@ -2076,6 +2115,7 @@ MpInitLibInitialize (
CpuMpData->CpuData[Index].StartupApSignal = CpuMpData->CpuData[Index].StartupApSignal =
(UINT32 *)(MonitorBuffer + MonitorFilterSize * Index); (UINT32 *)(MonitorBuffer + MonitorFilterSize * Index);
} }
// //
// Enable the local APIC for Virtual Wire Mode. // Enable the local APIC for Virtual Wire Mode.
// //
@@ -2097,10 +2137,10 @@ MpInitLibInitialize (
CpuMpData->CpuCount = OldCpuMpData->CpuCount; CpuMpData->CpuCount = OldCpuMpData->CpuCount;
CpuMpData->BspNumber = OldCpuMpData->BspNumber; CpuMpData->BspNumber = OldCpuMpData->BspNumber;
CpuMpData->CpuInfoInHob = OldCpuMpData->CpuInfoInHob; CpuMpData->CpuInfoInHob = OldCpuMpData->CpuInfoInHob;
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; Index++) { for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
InitializeSpinLock(&CpuMpData->CpuData[Index].ApLock); InitializeSpinLock (&CpuMpData->CpuData[Index].ApLock);
CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0)? TRUE:FALSE; CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0) ? TRUE : FALSE;
CpuMpData->CpuData[Index].ApFunction = 0; CpuMpData->CpuData[Index].ApFunction = 0;
} }
} }
@@ -2108,7 +2148,8 @@ MpInitLibInitialize (
if (!GetMicrocodePatchInfoFromHob ( if (!GetMicrocodePatchInfoFromHob (
&CpuMpData->MicrocodePatchAddress, &CpuMpData->MicrocodePatchAddress,
&CpuMpData->MicrocodePatchRegionSize &CpuMpData->MicrocodePatchRegionSize
)) { ))
{
// //
// The microcode patch information cache HOB does not exist, which means // The microcode patch information cache HOB does not exist, which means
// the microcode patches data has not been loaded into memory yet // the microcode patches data has not been loaded into memory yet
@@ -2137,6 +2178,7 @@ MpInitLibInitialize (
// //
CpuMpData->InitFlag = ApInitReconfig; CpuMpData->InitFlag = ApInitReconfig;
} }
WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE); WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE);
// //
// Wait for all APs finished initialization // Wait for all APs finished initialization
@@ -2144,9 +2186,11 @@ MpInitLibInitialize (
while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) { while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {
CpuPause (); CpuPause ();
} }
if (OldCpuMpData != NULL) { if (OldCpuMpData != NULL) {
CpuMpData->InitFlag = ApInitDone; CpuMpData->InitFlag = ApInitDone;
} }
for (Index = 0; Index < CpuMpData->CpuCount; Index++) { for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
SetApState (&CpuMpData->CpuData[Index], CpuStateIdle); SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);
} }
@@ -2158,7 +2202,8 @@ MpInitLibInitialize (
DEBUG_CODE_BEGIN (); DEBUG_CODE_BEGIN ();
UINT32 ThreadId; UINT32 ThreadId;
UINT32 ExpectedMicrocodeRevision; UINT32 ExpectedMicrocodeRevision;
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; Index++) { for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId); GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId);
if (ThreadId == 0) { if (ThreadId == 0) {
@@ -2170,12 +2215,17 @@ MpInitLibInitialize (
if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) { if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) {
ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision; ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision;
} }
DEBUG (( DEBUG ((
DEBUG_INFO, "CPU[%04d]: Microcode revision = %08x, expected = %08x\n", DEBUG_INFO,
Index, CpuMpData->CpuData[Index].MicrocodeRevision, ExpectedMicrocodeRevision "CPU[%04d]: Microcode revision = %08x, expected = %08x\n",
Index,
CpuMpData->CpuData[Index].MicrocodeRevision,
ExpectedMicrocodeRevision
)); ));
} }
} }
DEBUG_CODE_END (); DEBUG_CODE_END ();
// //
// Initialize global data for MP support // Initialize global data for MP support
@@ -2216,7 +2266,7 @@ MpInitLibGetProcessorInfo (
UINTN OriginalProcessorNumber; UINTN OriginalProcessorNumber;
CpuMpData = GetCpuMpData (); CpuMpData = GetCpuMpData ();
CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
// //
// Lower 24 bits contains the actual processor number. // Lower 24 bits contains the actual processor number.
@@ -2240,14 +2290,16 @@ MpInitLibGetProcessorInfo (
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
ProcessorInfoBuffer->ProcessorId = (UINT64) CpuInfoInHob[ProcessorNumber].ApicId; ProcessorInfoBuffer->ProcessorId = (UINT64)CpuInfoInHob[ProcessorNumber].ApicId;
ProcessorInfoBuffer->StatusFlag = 0; ProcessorInfoBuffer->StatusFlag = 0;
if (ProcessorNumber == CpuMpData->BspNumber) { if (ProcessorNumber == CpuMpData->BspNumber) {
ProcessorInfoBuffer->StatusFlag |= PROCESSOR_AS_BSP_BIT; ProcessorInfoBuffer->StatusFlag |= PROCESSOR_AS_BSP_BIT;
} }
if (CpuMpData->CpuData[ProcessorNumber].CpuHealthy) { if (CpuMpData->CpuData[ProcessorNumber].CpuHealthy) {
ProcessorInfoBuffer->StatusFlag |= PROCESSOR_HEALTH_STATUS_BIT; ProcessorInfoBuffer->StatusFlag |= PROCESSOR_HEALTH_STATUS_BIT;
} }
if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateDisabled) { if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateDisabled) {
ProcessorInfoBuffer->StatusFlag &= ~PROCESSOR_ENABLED_BIT; ProcessorInfoBuffer->StatusFlag &= ~PROCESSOR_ENABLED_BIT;
} else { } else {
@@ -2405,10 +2457,11 @@ SwitchBSPWorker (
} else { } else {
SetApState (&CpuMpData->CpuData[CallerNumber], CpuStateIdle); SetApState (&CpuMpData->CpuData[CallerNumber], CpuStateIdle);
} }
// //
// Save new BSP number // Save new BSP number
// //
CpuMpData->BspNumber = (UINT32) ProcessorNumber; CpuMpData->BspNumber = (UINT32)ProcessorNumber;
// //
// Restore interrupt state. // Restore interrupt state.
@@ -2472,7 +2525,7 @@ EnableDisableApWorker (
if (HealthFlag != NULL) { if (HealthFlag != NULL) {
CpuMpData->CpuData[ProcessorNumber].CpuHealthy = CpuMpData->CpuData[ProcessorNumber].CpuHealthy =
(BOOLEAN) ((*HealthFlag & PROCESSOR_HEALTH_STATUS_BIT) != 0); (BOOLEAN)((*HealthFlag & PROCESSOR_HEALTH_STATUS_BIT) != 0);
} }
return EFI_SUCCESS; return EFI_SUCCESS;
@@ -2562,13 +2615,14 @@ MpInitLibGetNumberOfProcessors (
EnabledProcessorNumber = 0; EnabledProcessorNumber = 0;
for (Index = 0; Index < ProcessorNumber; Index++) { for (Index = 0; Index < ProcessorNumber; Index++) {
if (GetApState (&CpuMpData->CpuData[Index]) != CpuStateDisabled) { if (GetApState (&CpuMpData->CpuData[Index]) != CpuStateDisabled) {
EnabledProcessorNumber ++; EnabledProcessorNumber++;
} }
} }
if (NumberOfProcessors != NULL) { if (NumberOfProcessors != NULL) {
*NumberOfProcessors = ProcessorNumber; *NumberOfProcessors = ProcessorNumber;
} }
if (NumberOfEnabledProcessors != NULL) { if (NumberOfEnabledProcessors != NULL) {
*NumberOfEnabledProcessors = EnabledProcessorNumber; *NumberOfEnabledProcessors = EnabledProcessorNumber;
} }
@@ -2576,7 +2630,6 @@ MpInitLibGetNumberOfProcessors (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Worker function to execute a caller provided function on all enabled APs. Worker function to execute a caller provided function on all enabled APs.
@@ -2635,7 +2688,7 @@ StartupAllCPUsWorker (
*FailedCpuList = NULL; *FailedCpuList = NULL;
} }
if (CpuMpData->CpuCount == 1 && ExcludeBsp) { if ((CpuMpData->CpuCount == 1) && ExcludeBsp) {
return EFI_NOT_STARTED; return EFI_NOT_STARTED;
} }
@@ -2719,6 +2772,7 @@ StartupAllCPUsWorker (
if (ProcessorNumber == CallerNumber) { if (ProcessorNumber == CallerNumber) {
continue; continue;
} }
if (CpuMpData->CpuData[ProcessorNumber].Waiting) { if (CpuMpData->CpuData[ProcessorNumber].Waiting) {
WakeUpAP (CpuMpData, FALSE, ProcessorNumber, Procedure, ProcedureArgument, TRUE); WakeUpAP (CpuMpData, FALSE, ProcessorNumber, Procedure, ProcedureArgument, TRUE);
break; break;
@@ -2873,8 +2927,9 @@ GetCpuMpDataFromGuidedHob (
GuidHob = GetFirstGuidHob (&mCpuInitMpLibHobGuid); GuidHob = GetFirstGuidHob (&mCpuInitMpLibHobGuid);
if (GuidHob != NULL) { if (GuidHob != NULL) {
DataInHob = GET_GUID_HOB_DATA (GuidHob); DataInHob = GET_GUID_HOB_DATA (GuidHob);
CpuMpData = (CPU_MP_DATA *) (*(UINTN *) DataInHob); CpuMpData = (CPU_MP_DATA *)(*(UINTN *)DataInHob);
} }
return CpuMpData; return CpuMpData;
} }

5
UefiCpuPkg/Library/MpInitLib/MpLib.h
View File

@@ -322,7 +322,7 @@ typedef struct {
**/ **/
typedef typedef
VOID VOID
(EFIAPI AP_RESET) ( (EFIAPI AP_RESET)(
IN UINTN BufferStart, IN UINTN BufferStart,
IN UINT16 Code16, IN UINT16 Code16,
IN UINT16 Code32, IN UINT16 Code32,
@@ -347,7 +347,7 @@ extern EFI_GUID mCpuInitMpLibHobGuid;
**/ **/
typedef typedef
VOID VOID
(EFIAPI * ASM_RELOCATE_AP_LOOP) ( (EFIAPI *ASM_RELOCATE_AP_LOOP)(
IN BOOLEAN MwaitSupport, IN BOOLEAN MwaitSupport,
IN UINTN ApTargetCState, IN UINTN ApTargetCState,
IN UINTN PmCodeSegment, IN UINTN PmCodeSegment,
@@ -406,7 +406,6 @@ SaveCpuMpData (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
); );
/** /**
Get available system memory below 1MB by specified size. Get available system memory below 1MB by specified size.

42
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
View File

@@ -31,7 +31,6 @@ NotifyOnS3SmmInitDonePpi (
IN VOID *InvokePpi IN VOID *InvokePpi
); );
// //
// Global function // Global function
// //
@@ -76,7 +75,6 @@ NotifyOnS3SmmInitDonePpi (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Enable Debug Agent to support source debugging on AP function. Enable Debug Agent to support source debugging on AP function.
@@ -110,8 +108,9 @@ GetCpuMpData (
ASSERT (CpuMpData != NULL); ASSERT (CpuMpData != NULL);
} else { } else {
AsmReadIdtr (&Idtr); AsmReadIdtr (&Idtr);
CpuMpData = (CPU_MP_DATA *) (Idtr.Base + Idtr.Limit + 1); CpuMpData = (CPU_MP_DATA *)(Idtr.Base + Idtr.Limit + 1);
} }
return CpuMpData; return CpuMpData;
} }
@@ -126,13 +125,14 @@ SaveCpuMpData (
) )
{ {
UINT64 Data64; UINT64 Data64;
// //
// Build location of CPU MP DATA buffer in HOB // Build location of CPU MP DATA buffer in HOB
// //
Data64 = (UINT64) (UINTN) CpuMpData; Data64 = (UINT64)(UINTN)CpuMpData;
BuildGuidDataHob ( BuildGuidDataHob (
&mCpuInitMpLibHobGuid, &mCpuInitMpLibHobGuid,
(VOID *) &Data64, (VOID *)&Data64,
sizeof (UINT64) sizeof (UINT64)
); );
} }
@@ -176,8 +176,10 @@ CheckOverlapWithAllocatedBuffer (
break; break;
} }
} }
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
} }
return Overlapped; return Overlapped;
} }
@@ -217,13 +219,15 @@ GetWakeupBuffer (
EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED | EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED |
EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED
)) == 0) )) == 0)
) { )
{
// //
// Need memory under 1MB to be collected here // Need memory under 1MB to be collected here
// //
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength; WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
if (PcdGetBool (PcdSevEsIsEnabled) && if (PcdGetBool (PcdSevEsIsEnabled) &&
WakeupBufferEnd > mSevEsPeiWakeupBuffer) { (WakeupBufferEnd > mSevEsPeiWakeupBuffer))
{
// //
// SEV-ES Wakeup buffer should be under 1MB and under any previous one // SEV-ES Wakeup buffer should be under 1MB and under any previous one
// //
@@ -234,6 +238,7 @@ GetWakeupBuffer (
// //
WakeupBufferEnd = BASE_1MB; WakeupBufferEnd = BASE_1MB;
} }
while (WakeupBufferEnd > WakeupBufferSize) { while (WakeupBufferEnd > WakeupBufferSize) {
// //
// Wakeup buffer should be aligned on 4KB // Wakeup buffer should be aligned on 4KB
@@ -242,6 +247,7 @@ GetWakeupBuffer (
if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) { if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) {
break; break;
} }
if (CheckOverlapWithAllocatedBuffer (WakeupBufferStart, WakeupBufferEnd)) { if (CheckOverlapWithAllocatedBuffer (WakeupBufferStart, WakeupBufferEnd)) {
// //
// If this range is overlapped with existing allocated buffer, skip it // If this range is overlapped with existing allocated buffer, skip it
@@ -250,8 +256,13 @@ GetWakeupBuffer (
WakeupBufferEnd -= WakeupBufferSize; WakeupBufferEnd -= WakeupBufferSize;
continue; continue;
} }
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart, WakeupBufferSize)); DEBUG ((
DEBUG_INFO,
"WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart,
WakeupBufferSize
));
if (PcdGetBool (PcdSevEsIsEnabled)) { if (PcdGetBool (PcdSevEsIsEnabled)) {
// //
@@ -265,13 +276,14 @@ GetWakeupBuffer (
} }
} }
} }
// //
// Find the next HOB // Find the next HOB
// //
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
} }
return (UINTN) -1; return (UINTN)-1;
} }
/** /**
@@ -704,14 +716,14 @@ PlatformShadowMicrocode (
&gEdkiiPeiShadowMicrocodePpiGuid, &gEdkiiPeiShadowMicrocodePpiGuid,
0, 0,
NULL, NULL,
(VOID **) &ShadowMicrocodePpi (VOID **)&ShadowMicrocodePpi
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
CpuCount = CpuMpData->CpuCount; CpuCount = CpuMpData->CpuCount;
MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *) AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount); MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *)AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount);
if (MicrocodeCpuId == NULL) { if (MicrocodeCpuId == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
@@ -733,13 +745,15 @@ PlatformShadowMicrocode (
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
CpuMpData->MicrocodePatchAddress = (UINTN) Buffer; CpuMpData->MicrocodePatchAddress = (UINTN)Buffer;
CpuMpData->MicrocodePatchRegionSize = BufferSize; CpuMpData->MicrocodePatchRegionSize = BufferSize;
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n", "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
__FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize __FUNCTION__,
CpuMpData->MicrocodePatchAddress,
CpuMpData->MicrocodePatchRegionSize
)); ));
return EFI_SUCCESS; return EFI_SUCCESS;

4
UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
View File

@@ -103,9 +103,11 @@ MpInitLibGetProcessorInfo (
if (ProcessorInfoBuffer == NULL) { if (ProcessorInfoBuffer == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (ProcessorNumber != 0) { if (ProcessorNumber != 0) {
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
ProcessorInfoBuffer->ProcessorId = 0; ProcessorInfoBuffer->ProcessorId = 0;
ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT | ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT |
PROCESSOR_ENABLED_BIT | PROCESSOR_ENABLED_BIT |
@@ -123,6 +125,7 @@ MpInitLibGetProcessorInfo (
HealthData->Uint32 = 0; HealthData->Uint32 = 0;
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -402,6 +405,7 @@ MpInitLibWhoAmI (
if (ProcessorNumber == NULL) { if (ProcessorNumber == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
*ProcessorNumber = 0; *ProcessorNumber = 0;
return EFI_SUCCESS; return EFI_SUCCESS;
} }

467
UefiCpuPkg/Library/MtrrLib/MtrrLib.c
View File

File diff suppressed because it is too large Load Diff

115
UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
View File

@@ -87,6 +87,7 @@ VerifyMemoryRanges (
) )
{ {
UINTN Index; UINTN Index;
UT_ASSERT_EQUAL (ExpectedMemoryRangeCount, ActualRangeCount); UT_ASSERT_EQUAL (ExpectedMemoryRangeCount, ActualRangeCount);
for (Index = 0; Index < ExpectedMemoryRangeCount; Index++) { for (Index = 0; Index < ExpectedMemoryRangeCount; Index++) {
UT_ASSERT_EQUAL (ExpectedMemoryRanges[Index].BaseAddress, ActualRanges[Index].BaseAddress); UT_ASSERT_EQUAL (ExpectedMemoryRanges[Index].BaseAddress, ActualRanges[Index].BaseAddress);
@@ -110,6 +111,7 @@ DumpMemoryRanges (
) )
{ {
UINTN Index; UINTN Index;
for (Index = 0; Index < RangeCount; Index++) { for (Index = 0; Index < RangeCount; Index++) {
UT_LOG_INFO ("\t{ 0x%016llx, 0x%016llx, %a },\n", Ranges[Index].BaseAddress, Ranges[Index].Length, mCacheDescription[Ranges[Index].Type]); UT_LOG_INFO ("\t{ 0x%016llx, 0x%016llx, %a },\n", Ranges[Index].BaseAddress, Ranges[Index].Length, mCacheDescription[Ranges[Index].Type]);
} }
@@ -207,14 +209,23 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
MTRR_SETTINGS *Mtrrs[2]; MTRR_SETTINGS *Mtrrs[2];
SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
GenerateRandomMemoryTypeCombination ( GenerateRandomMemoryTypeCombination (
SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs), SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),
&UcCount, &WtCount, &WbCount, &WpCount, &WcCount &UcCount,
&WtCount,
&WbCount,
&WpCount,
&WcCount
); );
GenerateValidAndConfigurableMtrrPairs ( GenerateValidAndConfigurableMtrrPairs (
SystemParameter->PhysicalAddressBits, RawMtrrRange, SystemParameter->PhysicalAddressBits,
UcCount, WtCount, WbCount, WpCount, WcCount RawMtrrRange,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
); );
ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount; ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;
@@ -222,13 +233,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
GetEffectiveMemoryRanges ( GetEffectiveMemoryRanges (
SystemParameter->DefaultCacheType, SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits, SystemParameter->PhysicalAddressBits,
RawMtrrRange, ExpectedVariableMtrrUsage, RawMtrrRange,
ExpectedMemoryRanges, &ExpectedMemoryRangesCount ExpectedVariableMtrrUsage,
ExpectedMemoryRanges,
&ExpectedMemoryRangesCount
); );
UT_LOG_INFO ( UT_LOG_INFO (
"Total MTRR [%d]: UC=%d, WT=%d, WB=%d, WP=%d, WC=%d\n", "Total MTRR [%d]: UC=%d, WT=%d, WB=%d, WP=%d, WC=%d\n",
ExpectedVariableMtrrUsage, UcCount, WtCount, WbCount, WpCount, WcCount ExpectedVariableMtrrUsage,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
); );
UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount); UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);
DumpMemoryRanges (ExpectedMemoryRanges, ExpectedMemoryRangesCount); DumpMemoryRanges (ExpectedMemoryRanges, ExpectedMemoryRangesCount);
@@ -249,16 +267,23 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
Scratch = realloc (Scratch, ScratchSize); Scratch = realloc (Scratch, ScratchSize);
Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount); Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);
} }
UT_ASSERT_STATUS_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_STATUS_EQUAL (Status, RETURN_SUCCESS);
if (Mtrrs[MtrrIndex] == NULL) { if (Mtrrs[MtrrIndex] == NULL) {
ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs)); ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));
MtrrGetAllMtrrs (&LocalMtrrs); MtrrGetAllMtrrs (&LocalMtrrs);
} }
ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges); ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
CollectTestResult ( CollectTestResult (
SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount, SystemParameter->DefaultCacheType,
&LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage SystemParameter->PhysicalAddressBits,
SystemParameter->VariableMtrrCount,
&LocalMtrrs,
ActualMemoryRanges,
&ActualMemoryRangesCount,
&ActualVariableMtrrUsage
); );
UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount); UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);
@@ -297,7 +322,7 @@ UnitTestInvalidMemoryLayouts (
RETURN_STATUS Status; RETURN_STATUS Status;
UINTN ScratchSize; UINTN ScratchSize;
SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
RangeCount = Random32 (1, ARRAY_SIZE (Ranges)); RangeCount = Random32 (1, ARRAY_SIZE (Ranges));
MaxAddress = 1ull << SystemParameter->PhysicalAddressBits; MaxAddress = 1ull << SystemParameter->PhysicalAddressBits;
@@ -313,7 +338,9 @@ UnitTestInvalidMemoryLayouts (
Ranges[Index].Type = GenerateRandomCacheType (); Ranges[Index].Type = GenerateRandomCacheType ();
Status = MtrrSetMemoryAttribute ( Status = MtrrSetMemoryAttribute (
Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type Ranges[Index].BaseAddress,
Ranges[Index].Length,
Ranges[Index].Type
); );
UT_ASSERT_TRUE (RETURN_ERROR (Status)); UT_ASSERT_TRUE (RETURN_ERROR (Status));
} }
@@ -344,7 +371,7 @@ UnitTestIsMtrrSupported (
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
// //
@@ -413,7 +440,7 @@ UnitTestGetVariableMtrrCount (
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
// //
@@ -474,7 +501,7 @@ UnitTestGetFirmwareVariableMtrrCount (
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
@@ -579,7 +606,7 @@ UnitTestMtrrGetFixedMtrr (
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
@@ -594,6 +621,7 @@ UnitTestMtrrGetFixedMtrr (
for (ByteIndex = 0; ByteIndex < sizeof (UINT64); ByteIndex++) { for (ByteIndex = 0; ByteIndex < sizeof (UINT64); ByteIndex++) {
MsrValue = MsrValue | LShiftU64 (GenerateRandomCacheType (), ByteIndex * 8); MsrValue = MsrValue | LShiftU64 (GenerateRandomCacheType (), ByteIndex * 8);
} }
ExpectedFixedSettings.Mtrr[MsrIndex] = MsrValue; ExpectedFixedSettings.Mtrr[MsrIndex] = MsrValue;
AsmWriteMsr64 (mFixedMtrrsIndex[MsrIndex], MsrValue); AsmWriteMsr64 (mFixedMtrrsIndex[MsrIndex], MsrValue);
} }
@@ -642,7 +670,7 @@ UnitTestMtrrGetAllMtrrs (
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
@@ -652,6 +680,7 @@ UnitTestMtrrGetAllMtrrs (
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableMtrr[Index].Base); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableMtrr[Index].Base);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableMtrr[Index].Mask); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableMtrr[Index].Mask);
} }
Result = MtrrGetAllMtrrs (&Mtrrs); Result = MtrrGetAllMtrrs (&Mtrrs);
UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs); UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);
UT_ASSERT_MEM_EQUAL (Mtrrs.Variables.Mtrr, VariableMtrr, sizeof (MTRR_VARIABLE_SETTING) * SystemParameter.VariableMtrrCount); UT_ASSERT_MEM_EQUAL (Mtrrs.Variables.Mtrr, VariableMtrr, sizeof (MTRR_VARIABLE_SETTING) * SystemParameter.VariableMtrrCount);
@@ -702,7 +731,7 @@ UnitTestMtrrSetAllMtrrs (
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
@@ -717,6 +746,7 @@ UnitTestMtrrSetAllMtrrs (
for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) { for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {
GenerateRandomMtrrPair (SystemParameter.PhysicalAddressBits, GenerateRandomCacheType (), &Mtrrs.Variables.Mtrr[Index], NULL); GenerateRandomMtrrPair (SystemParameter.PhysicalAddressBits, GenerateRandomCacheType (), &Mtrrs.Variables.Mtrr[Index], NULL);
} }
Result = MtrrSetAllMtrrs (&Mtrrs); Result = MtrrSetAllMtrrs (&Mtrrs);
UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs); UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);
@@ -756,7 +786,7 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
MSR_IA32_MTRR_PHYSBASE_REGISTER Base; MSR_IA32_MTRR_PHYSBASE_REGISTER Base;
MSR_IA32_MTRR_PHYSMASK_REGISTER Mask; MSR_IA32_MTRR_PHYSMASK_REGISTER Mask;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
@@ -770,12 +800,13 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting[Index].Base); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting[Index].Base);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting[Index].Mask); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting[Index].Mask);
} }
Result = MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr); Result = MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr);
UT_ASSERT_EQUAL (Result, SystemParameter.VariableMtrrCount); UT_ASSERT_EQUAL (Result, SystemParameter.VariableMtrrCount);
for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) { for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {
Base.Uint64 = VariableMtrr[Index].BaseAddress; Base.Uint64 = VariableMtrr[Index].BaseAddress;
Base.Bits.Type = (UINT32) VariableMtrr[Index].Type; Base.Bits.Type = (UINT32)VariableMtrr[Index].Type;
UT_ASSERT_EQUAL (Base.Uint64, VariableSetting[Index].Base); UT_ASSERT_EQUAL (Base.Uint64, VariableSetting[Index].Base);
Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask; Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask;
@@ -849,7 +880,7 @@ UnitTestMtrrGetDefaultMemoryType (
CacheType[3] = CacheWriteProtected; CacheType[3] = CacheWriteProtected;
CacheType[4] = CacheWriteBack; CacheType[4] = CacheWriteBack;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
// //
@@ -926,14 +957,23 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
MTRR_SETTINGS *Mtrrs[2]; MTRR_SETTINGS *Mtrrs[2];
SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
GenerateRandomMemoryTypeCombination ( GenerateRandomMemoryTypeCombination (
SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs), SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),
&UcCount, &WtCount, &WbCount, &WpCount, &WcCount &UcCount,
&WtCount,
&WbCount,
&WpCount,
&WcCount
); );
GenerateValidAndConfigurableMtrrPairs ( GenerateValidAndConfigurableMtrrPairs (
SystemParameter->PhysicalAddressBits, RawMtrrRange, SystemParameter->PhysicalAddressBits,
UcCount, WtCount, WbCount, WpCount, WcCount RawMtrrRange,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
); );
ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount; ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;
@@ -941,8 +981,10 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
GetEffectiveMemoryRanges ( GetEffectiveMemoryRanges (
SystemParameter->DefaultCacheType, SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits, SystemParameter->PhysicalAddressBits,
RawMtrrRange, ExpectedVariableMtrrUsage, RawMtrrRange,
ExpectedMemoryRanges, &ExpectedMemoryRangesCount ExpectedVariableMtrrUsage,
ExpectedMemoryRanges,
&ExpectedMemoryRangesCount
); );
UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount); UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);
@@ -964,7 +1006,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
ExpectedMemoryRanges[Index].Type ExpectedMemoryRanges[Index].Type
); );
UT_ASSERT_TRUE (Status == RETURN_SUCCESS || Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL); UT_ASSERT_TRUE (Status == RETURN_SUCCESS || Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL);
if (Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL) { if ((Status == RETURN_OUT_OF_RESOURCES) || (Status == RETURN_BUFFER_TOO_SMALL)) {
return UNIT_TEST_SKIPPED; return UNIT_TEST_SKIPPED;
} }
} }
@@ -973,10 +1015,16 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs)); ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));
MtrrGetAllMtrrs (&LocalMtrrs); MtrrGetAllMtrrs (&LocalMtrrs);
} }
ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges); ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
CollectTestResult ( CollectTestResult (
SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount, SystemParameter->DefaultCacheType,
&LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage SystemParameter->PhysicalAddressBits,
SystemParameter->VariableMtrrCount,
&LocalMtrrs,
ActualMemoryRanges,
&ActualMemoryRangesCount,
&ActualVariableMtrrUsage
); );
UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount); UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);
DumpMemoryRanges (ActualMemoryRanges, ActualMemoryRangesCount); DumpMemoryRanges (ActualMemoryRanges, ActualMemoryRangesCount);
@@ -989,7 +1037,6 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
return UNIT_TEST_PASSED; return UNIT_TEST_PASSED;
} }
/** /**
Prep routine for UnitTestGetFirmwareVariableMtrrCount(). Prep routine for UnitTestGetFirmwareVariableMtrrCount().
@@ -1003,7 +1050,7 @@ SavePcdValue (
{ {
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
LocalContext->NumberOfReservedVariableMtrrs = PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs); LocalContext->NumberOfReservedVariableMtrrs = PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);
return UNIT_TEST_PASSED; return UNIT_TEST_PASSED;
} }
@@ -1021,7 +1068,7 @@ RestorePcdValue (
{ {
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, LocalContext->NumberOfReservedVariableMtrrs); PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, LocalContext->NumberOfReservedVariableMtrrs);
} }
@@ -1077,6 +1124,7 @@ UnitTestingEntry (
Status = EFI_OUT_OF_RESOURCES; Status = EFI_OUT_OF_RESOURCES;
goto EXIT; goto EXIT;
} }
AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext); AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext);
@@ -1095,6 +1143,7 @@ UnitTestingEntry (
AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributesInMtrrSettings", "MtrrSetMemoryAttributesInMtrrSettings", UnitTestMtrrSetMemoryAttributesInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributesInMtrrSettings", "MtrrSetMemoryAttributesInMtrrSettings", UnitTestMtrrSetMemoryAttributesInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
} }
} }
// //
// Execute the tests. // Execute the tests.
// //
@@ -1125,7 +1174,7 @@ main (
UINTN Count; UINTN Count;
DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, UNIT_TEST_APP_VERSION)); DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, UNIT_TEST_APP_VERSION));
srand ((unsigned int) time (NULL)); srand ((unsigned int)time (NULL));
// //
// MtrrLibUnitTest generate-random-numbers <path to MtrrLib/UnitTest/RandomNumber.c> <random-number count> // MtrrLibUnitTest generate-random-numbers <path to MtrrLib/UnitTest/RandomNumber.c> <random-number count>

1
UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
View File

@@ -192,4 +192,5 @@ GenerateRandomNumbers (
CHAR8 *FilePath, CHAR8 *FilePath,
UINTN Count UINTN Count
); );
#endif #endif

90
UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
View File

@@ -10,7 +10,7 @@
MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = { MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = {
CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProtected, CacheWriteBack CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProtected, CacheWriteBack
}; };
UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTRR]; UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTRR];
MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VARIABLE_MTRR]; MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VARIABLE_MTRR];
@@ -78,8 +78,10 @@ GenerateRandomNumbers (
if (Index % 10 == 0) { if (Index % 10 == 0) {
fprintf (File, "\n "); fprintf (File, "\n ");
} }
fprintf (File, " %d,", rand ()); fprintf (File, " %d,", rand ());
} }
fprintf (File, "\n};\n"); fprintf (File, "\n};\n");
fclose (File); fclose (File);
} }
@@ -124,18 +126,21 @@ UnitTestMtrrLibAsmCpuid (
if (Edx != NULL) { if (Edx != NULL) {
*Edx = mCpuidVersionInfoEdx.Uint32; *Edx = mCpuidVersionInfoEdx.Uint32;
} }
return Index; return Index;
break; break;
case CPUID_EXTENDED_FUNCTION: case CPUID_EXTENDED_FUNCTION:
if (Eax != NULL) { if (Eax != NULL) {
*Eax = CPUID_VIR_PHY_ADDRESS_SIZE; *Eax = CPUID_VIR_PHY_ADDRESS_SIZE;
} }
return Index; return Index;
break; break;
case CPUID_VIR_PHY_ADDRESS_SIZE: case CPUID_VIR_PHY_ADDRESS_SIZE:
if (Eax != NULL) { if (Eax != NULL) {
*Eax = mCpuidVirPhyAddressSizeEax.Uint32; *Eax = mCpuidVirPhyAddressSizeEax.Uint32;
} }
return Index; return Index;
break; break;
} }
@@ -143,7 +148,7 @@ UnitTestMtrrLibAsmCpuid (
// //
// Should never fall through to here // Should never fall through to here
// //
ASSERT(FALSE); ASSERT (FALSE);
return Index; return Index;
} }
@@ -163,7 +168,7 @@ UnitTestMtrrLibAsmCpuid (
**/ **/
UINT64 UINT64
EFIAPI EFIAPI
UnitTestMtrrLibAsmReadMsr64( UnitTestMtrrLibAsmReadMsr64 (
IN UINT32 MsrIndex IN UINT32 MsrIndex
) )
{ {
@@ -176,7 +181,8 @@ UnitTestMtrrLibAsmReadMsr64(
} }
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) && if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) { (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
{
if (MsrIndex % 2 == 0) { if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1; Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
return mVariableMtrrsPhysBase[Index].Uint64; return mVariableMtrrsPhysBase[Index].Uint64;
@@ -197,7 +203,7 @@ UnitTestMtrrLibAsmReadMsr64(
// //
// Should never fall through to here // Should never fall through to here
// //
ASSERT(FALSE); ASSERT (FALSE);
return 0; return 0;
} }
@@ -220,7 +226,7 @@ UnitTestMtrrLibAsmReadMsr64(
**/ **/
UINT64 UINT64
EFIAPI EFIAPI
UnitTestMtrrLibAsmWriteMsr64( UnitTestMtrrLibAsmWriteMsr64 (
IN UINT32 MsrIndex, IN UINT32 MsrIndex,
IN UINT64 Value IN UINT64 Value
) )
@@ -235,7 +241,8 @@ UnitTestMtrrLibAsmWriteMsr64(
} }
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) && if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) { (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
{
if (MsrIndex % 2 == 0) { if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1; Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
mVariableMtrrsPhysBase[Index].Uint64 = Value; mVariableMtrrsPhysBase[Index].Uint64 = Value;
@@ -260,7 +267,7 @@ UnitTestMtrrLibAsmWriteMsr64(
// //
// Should never fall through to here // Should never fall through to here
// //
ASSERT(FALSE); ASSERT (FALSE);
return 0; return 0;
} }
@@ -328,7 +335,7 @@ InitializeSystem (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *) Context); return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *)Context);
} }
/** /**
@@ -366,10 +373,10 @@ CollectTestResult (
*MtrrCount = 0; *MtrrCount = 0;
for (Index = 0; Index < VariableMtrrCount; Index++) { for (Index = 0; Index < VariableMtrrCount; Index++) {
if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) { if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) {
RawMemoryRanges[*MtrrCount].BaseAddress = Mtrrs->Variables.Mtrr[Index].Base & MtrrValidAddressMask; RawMemoryRanges[*MtrrCount].BaseAddress = Mtrrs->Variables.Mtrr[Index].Base & MtrrValidAddressMask;
RawMemoryRanges[*MtrrCount].Type = RawMemoryRanges[*MtrrCount].Type =
((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type; ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type;
RawMemoryRanges[*MtrrCount].Length = RawMemoryRanges[*MtrrCount].Length =
((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1; ((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;
(*MtrrCount)++; (*MtrrCount)++;
@@ -392,7 +399,7 @@ Random32 (
UINT32 Limit UINT32 Limit
) )
{ {
return (UINT32) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start; return (UINT32)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start;
} }
/** /**
@@ -408,7 +415,7 @@ Random64 (
UINT64 Limit UINT64 Limit
) )
{ {
return (UINT64) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start; return (UINT64)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start;
} }
/** /**
@@ -468,7 +475,6 @@ GenerateRandomMtrrPair (
} }
} }
/** /**
Check whether the Range overlaps with any one in Ranges. Check whether the Range overlaps with any one in Ranges.
@@ -491,11 +497,13 @@ RangesOverlap (
// 1. range#2.base is in the middle of range#1 // 1. range#2.base is in the middle of range#1
// 2. range#1.base is in the middle of range#2 // 2. range#1.base is in the middle of range#2
// //
if ((Range->BaseAddress <= Ranges[Count].BaseAddress && Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length) if ( ((Range->BaseAddress <= Ranges[Count].BaseAddress) && (Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length))
|| (Ranges[Count].BaseAddress <= Range->BaseAddress && Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)) { || ((Ranges[Count].BaseAddress <= Range->BaseAddress) && (Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)))
{
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }
@@ -586,12 +594,13 @@ GenerateRandomCacheType (
**/ **/
INT32 INT32
CompareFuncUint64 ( CompareFuncUint64 (
CONST VOID * Left, CONST VOID *Left,
CONST VOID * Right CONST VOID *Right
) )
{ {
INT64 Delta; INT64 Delta;
Delta = (*(UINT64*)Left - *(UINT64*)Right);
Delta = (*(UINT64 *)Left - *(UINT64 *)Right);
if (Delta > 0) { if (Delta > 0) {
return 1; return 1;
} else if (Delta == 0) { } else if (Delta == 0) {
@@ -618,6 +627,7 @@ DetermineMemoryCacheType (
) )
{ {
UINT32 Index; UINT32 Index;
Range->Type = CacheInvalid; Range->Type = CacheInvalid;
for (Index = 0; Index < RangeCount; Index++) { for (Index = 0; Index < RangeCount; Index++) {
if (RangesOverlap (Range, &Ranges[Index], 1)) { if (RangesOverlap (Range, &Ranges[Index], 1)) {
@@ -649,10 +659,12 @@ GetNextDifferentElementInSortedArray (
) )
{ {
UINT64 CurrentElement; UINT64 CurrentElement;
CurrentElement = Array[Index]; CurrentElement = Array[Index];
while (CurrentElement == Array[Index] && Index < Count) { while (CurrentElement == Array[Index] && Index < Count) {
Index++; Index++;
} }
return Index; return Index;
} }
@@ -678,6 +690,7 @@ RemoveDuplicatesInSortedArray (
NewCount++; NewCount++;
Index = GetNextDifferentElementInSortedArray (Index, Array, *Count); Index = GetNextDifferentElementInSortedArray (Index, Array, *Count);
} }
*Count = NewCount; *Count = NewCount;
} }
@@ -713,6 +726,7 @@ GetOverlapBitFlag (
{ {
UINT64 OverlapBitFlag; UINT64 OverlapBitFlag;
UINT32 Index; UINT32 Index;
OverlapBitFlag = 0; OverlapBitFlag = 0;
for (Index = 0; Index < RawMemoryRangeCount; Index++) { for (Index = 0; Index < RawMemoryRangeCount; Index++) {
if (AddressInRange (Address, RawMemoryRanges[Index])) { if (AddressInRange (Address, RawMemoryRanges[Index])) {
@@ -740,9 +754,18 @@ CheckOverlapBitFlagsRelation (
IN UINT64 Flag2 IN UINT64 Flag2
) )
{ {
if (Flag1 == Flag2) return 0; if (Flag1 == Flag2) {
if ((Flag1 | Flag2) == Flag2) return 1; return 0;
if ((Flag1 | Flag2) == Flag1) return 2; }
if ((Flag1 | Flag2) == Flag2) {
return 1;
}
if ((Flag1 | Flag2) == Flag1) {
return 2;
}
return 3; return 3;
} }
@@ -764,15 +787,16 @@ IsEndpointInRanges (
) )
{ {
UINT32 Index; UINT32 Index;
for (Index = 0; Index < RangeCount; Index++) { for (Index = 0; Index < RangeCount; Index++) {
if (AddressInRange (Endpoint, Ranges[Index])) { if (AddressInRange (Endpoint, Ranges[Index])) {
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }
/** /**
Compact adjacent ranges of the same type. Compact adjacent ranges of the same type.
@@ -802,7 +826,7 @@ CompactAndExtendEffectiveMtrrMemoryRanges (
NewRangesCountActual = 0; NewRangesCountActual = 0;
NewRangesCountAtMost = *EffectiveMtrrMemoryRangesCount + 2; // At most with 2 more range entries. NewRangesCountAtMost = *EffectiveMtrrMemoryRangesCount + 2; // At most with 2 more range entries.
NewRanges = (MTRR_MEMORY_RANGE *) calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE)); NewRanges = (MTRR_MEMORY_RANGE *)calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE));
OldRanges = *EffectiveMtrrMemoryRanges; OldRanges = *EffectiveMtrrMemoryRanges;
if (OldRanges[0].BaseAddress > 0) { if (OldRanges[0].BaseAddress > 0) {
NewRanges[NewRangesCountActual].BaseAddress = 0; NewRanges[NewRangesCountActual].BaseAddress = 0;
@@ -815,21 +839,22 @@ CompactAndExtendEffectiveMtrrMemoryRanges (
while (OldRangesIndex < *EffectiveMtrrMemoryRangesCount) { while (OldRangesIndex < *EffectiveMtrrMemoryRangesCount) {
CurrentRangeTypeInOldRanges = OldRanges[OldRangesIndex].Type; CurrentRangeTypeInOldRanges = OldRanges[OldRangesIndex].Type;
CurrentRangeInNewRanges = NULL; CurrentRangeInNewRanges = NULL;
if (NewRangesCountActual > 0) // We need to check CurrentNewRange first before generate a new NewRange. if (NewRangesCountActual > 0) {
{ // We need to check CurrentNewRange first before generate a new NewRange.
CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1]; CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1];
} }
if (CurrentRangeInNewRanges != NULL && CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges) {
if ((CurrentRangeInNewRanges != NULL) && (CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges)) {
CurrentRangeInNewRanges->Length += OldRanges[OldRangesIndex].Length; CurrentRangeInNewRanges->Length += OldRanges[OldRangesIndex].Length;
} else { } else {
NewRanges[NewRangesCountActual].BaseAddress = OldRanges[OldRangesIndex].BaseAddress; NewRanges[NewRangesCountActual].BaseAddress = OldRanges[OldRangesIndex].BaseAddress;
NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length; NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;
NewRanges[NewRangesCountActual].Type = CurrentRangeTypeInOldRanges; NewRanges[NewRangesCountActual].Type = CurrentRangeTypeInOldRanges;
while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) {
{
OldRangesIndex++; OldRangesIndex++;
NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length; NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;
} }
NewRangesCountActual++; NewRangesCountActual++;
} }
@@ -955,18 +980,23 @@ GetEffectiveMemoryRanges (
AllRangePieces[AllRangePiecesCountActual].Length = 1; AllRangePieces[AllRangePiecesCountActual].Length = 1;
AllRangePiecesCountActual++; AllRangePiecesCountActual++;
} }
break; break;
case 3: // (1, 2) case 3: // (1, 2)
AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index] + 1; AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index] + 1;
AllRangePieces[AllRangePiecesCountActual].Length = (AllEndPointsInclusive[Index + 1] - 1) - (AllEndPointsInclusive[Index] + 1) + 1; AllRangePieces[AllRangePiecesCountActual].Length = (AllEndPointsInclusive[Index + 1] - 1) - (AllEndPointsInclusive[Index] + 1) + 1;
if (AllRangePieces[AllRangePiecesCountActual].Length == 0) // Only in case 3 can exists Length=0, we should skip such "segment". if (AllRangePieces[AllRangePiecesCountActual].Length == 0) {
// Only in case 3 can exists Length=0, we should skip such "segment".
break; break;
}
AllRangePiecesCountActual++; AllRangePiecesCountActual++;
if (!IsEndpointInRanges (AllEndPointsInclusive[Index], AllRangePieces, AllRangePiecesCountActual)) { if (!IsEndpointInRanges (AllEndPointsInclusive[Index], AllRangePieces, AllRangePiecesCountActual)) {
AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index]; AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index];
AllRangePieces[AllRangePiecesCountActual].Length = 1; AllRangePieces[AllRangePiecesCountActual].Length = 1;
AllRangePiecesCountActual++; AllRangePiecesCountActual++;
} }
break; break;
default: default:
ASSERT (FALSE); ASSERT (FALSE);

96
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
View File

@@ -8,7 +8,7 @@
#include "RegisterCpuFeatures.h" #include "RegisterCpuFeatures.h"
CHAR16 *mDependTypeStr[] = {L"None", L"Thread", L"Core", L"Package", L"Invalid" }; CHAR16 *mDependTypeStr[] = { L"None", L"Thread", L"Core", L"Package", L"Invalid" };
/** /**
Worker function to save PcdCpuFeaturesCapability. Worker function to save PcdCpuFeaturesCapability.
@@ -71,7 +71,7 @@ FillProcessorInfo (
} }
DisplayedModel = Eax.Bits.Model; DisplayedModel = Eax.Bits.Model;
if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) { if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {
DisplayedModel |= (Eax.Bits.ExtendedModelId << 4); DisplayedModel |= (Eax.Bits.ExtendedModelId << 4);
} }
@@ -143,14 +143,15 @@ CpuInitDataInitialize (
if (CpuFeature->GetConfigDataFunc != NULL) { if (CpuFeature->GetConfigDataFunc != NULL) {
CpuFeature->ConfigData = CpuFeature->GetConfigDataFunc (NumberOfCpus); CpuFeature->ConfigData = CpuFeature->GetConfigDataFunc (NumberOfCpus);
} }
Entry = Entry->ForwardLink; Entry = Entry->ForwardLink;
} }
CpuFeaturesData->NumberOfCpus = (UINT32) NumberOfCpus; CpuFeaturesData->NumberOfCpus = (UINT32)NumberOfCpus;
AcpiCpuData = GetAcpiCpuData (); AcpiCpuData = GetAcpiCpuData ();
ASSERT (AcpiCpuData != NULL); ASSERT (AcpiCpuData != NULL);
CpuFeaturesData->AcpiCpuData= AcpiCpuData; CpuFeaturesData->AcpiCpuData = AcpiCpuData;
CpuStatus = &AcpiCpuData->CpuFeatureInitData.CpuStatus; CpuStatus = &AcpiCpuData->CpuFeatureInitData.CpuStatus;
Location = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus)); Location = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus));
@@ -182,12 +183,14 @@ CpuInitDataInitialize (
if (Package < ProcessorInfoBuffer.Location.Package) { if (Package < ProcessorInfoBuffer.Location.Package) {
Package = ProcessorInfoBuffer.Location.Package; Package = ProcessorInfoBuffer.Location.Package;
} }
// //
// Collect CPU max core count info. // Collect CPU max core count info.
// //
if (Core < ProcessorInfoBuffer.Location.Core) { if (Core < ProcessorInfoBuffer.Location.Core) {
Core = ProcessorInfoBuffer.Location.Core; Core = ProcessorInfoBuffer.Location.Core;
} }
// //
// Collect CPU max thread count info. // Collect CPU max thread count info.
// //
@@ -195,13 +198,17 @@ CpuInitDataInitialize (
Thread = ProcessorInfoBuffer.Location.Thread; Thread = ProcessorInfoBuffer.Location.Thread;
} }
} }
CpuStatus->PackageCount = Package + 1; CpuStatus->PackageCount = Package + 1;
CpuStatus->MaxCoreCount = Core + 1; CpuStatus->MaxCoreCount = Core + 1;
CpuStatus->MaxThreadCount = Thread + 1; CpuStatus->MaxThreadCount = Thread + 1;
DEBUG ((DEBUG_INFO, "Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n", DEBUG ((
DEBUG_INFO,
"Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n",
CpuStatus->PackageCount, CpuStatus->PackageCount,
CpuStatus->MaxCoreCount, CpuStatus->MaxCoreCount,
CpuStatus->MaxThreadCount)); CpuStatus->MaxThreadCount
));
// //
// Collect valid core count in each package because not all cores are valid. // Collect valid core count in each package because not all cores are valid.
@@ -228,7 +235,10 @@ CpuInitDataInitialize (
for (CoreIndex = 0; CoreIndex < CpuStatus->MaxCoreCount; CoreIndex++) { for (CoreIndex = 0; CoreIndex < CpuStatus->MaxCoreCount; CoreIndex++) {
if (ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex] != 0) { if (ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex] != 0) {
DEBUG (( DEBUG ((
DEBUG_INFO, " P%02d C%04d, Thread Count = %d\n", PackageIndex, CoreIndex, DEBUG_INFO,
" P%02d C%04d, Thread Count = %d\n",
PackageIndex,
CoreIndex,
ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex] ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex]
)); ));
} }
@@ -300,6 +310,7 @@ CpuInitDataInitialize (
if (Location->Core == FirstCore[Location->Package]) { if (Location->Core == FirstCore[Location->Package]) {
CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Core = 1; CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Core = 1;
} }
if (Location->Thread == FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]) { if (Location->Thread == FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]) {
CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Thread = 1; CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Thread = 1;
} }
@@ -416,6 +427,7 @@ IsBitMaskMatch (
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }
@@ -462,6 +474,7 @@ CollectProcessorData (
CpuFeaturesData->BitMaskSize CpuFeaturesData->BitMaskSize
); );
} }
Entry = Entry->ForwardLink; Entry = Entry->ForwardLink;
} }
} }
@@ -493,7 +506,7 @@ DumpRegisterTableOnProcessor (
RegisterTable = &CpuFeaturesData->RegisterTable[ProcessorNumber]; RegisterTable = &CpuFeaturesData->RegisterTable[ProcessorNumber];
DEBUG ((DebugPrintErrorLevel, "RegisterTable->TableLength = %d\n", RegisterTable->TableLength)); DEBUG ((DebugPrintErrorLevel, "RegisterTable->TableLength = %d\n", RegisterTable->TableLength));
RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
for (FeatureIndex = 0; FeatureIndex < RegisterTable->TableLength; FeatureIndex++) { for (FeatureIndex = 0; FeatureIndex < RegisterTable->TableLength; FeatureIndex++) {
RegisterTableEntry = &RegisterTableEntryHead[FeatureIndex]; RegisterTableEntry = &RegisterTableEntryHead[FeatureIndex];
@@ -502,8 +515,8 @@ DumpRegisterTableOnProcessor (
DEBUG (( DEBUG ((
DebugPrintErrorLevel, DebugPrintErrorLevel,
"Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", "Processor: %04d: Index %04d, MSR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
(UINT32) ProcessorNumber, (UINT32)ProcessorNumber,
(UINT32) FeatureIndex, (UINT32)FeatureIndex,
RegisterTableEntry->Index, RegisterTableEntry->Index,
RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitLength, RegisterTableEntry->ValidBitLength,
@@ -514,8 +527,8 @@ DumpRegisterTableOnProcessor (
DEBUG (( DEBUG ((
DebugPrintErrorLevel, DebugPrintErrorLevel,
"Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", "Processor: %04d: Index %04d, CR : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
(UINT32) ProcessorNumber, (UINT32)ProcessorNumber,
(UINT32) FeatureIndex, (UINT32)FeatureIndex,
RegisterTableEntry->Index, RegisterTableEntry->Index,
RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitLength, RegisterTableEntry->ValidBitLength,
@@ -526,8 +539,8 @@ DumpRegisterTableOnProcessor (
DEBUG (( DEBUG ((
DebugPrintErrorLevel, DebugPrintErrorLevel,
"Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", "Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
(UINT32) ProcessorNumber, (UINT32)ProcessorNumber,
(UINT32) FeatureIndex, (UINT32)FeatureIndex,
RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32), RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32),
RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitLength, RegisterTableEntry->ValidBitLength,
@@ -538,8 +551,8 @@ DumpRegisterTableOnProcessor (
DEBUG (( DEBUG ((
DebugPrintErrorLevel, DebugPrintErrorLevel,
"Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n", "Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",
(UINT32) ProcessorNumber, (UINT32)ProcessorNumber,
(UINT32) FeatureIndex, (UINT32)FeatureIndex,
RegisterTableEntry->Index, RegisterTableEntry->Index,
RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitLength, RegisterTableEntry->ValidBitLength,
@@ -550,8 +563,8 @@ DumpRegisterTableOnProcessor (
DEBUG (( DEBUG ((
DebugPrintErrorLevel, DebugPrintErrorLevel,
"Processor: %04d: Index %04d, SEMAP: %s\r\n", "Processor: %04d: Index %04d, SEMAP: %s\r\n",
(UINT32) ProcessorNumber, (UINT32)ProcessorNumber,
(UINT32) FeatureIndex, (UINT32)FeatureIndex,
mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)] mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)]
)); ));
break; break;
@@ -585,7 +598,7 @@ BiggestDep (
Bigger = MAX (BeforeDep, AfterDep); Bigger = MAX (BeforeDep, AfterDep);
Bigger = MAX (Bigger, NoneNeibBeforeDep); Bigger = MAX (Bigger, NoneNeibBeforeDep);
return MAX(Bigger, NoneNeibAfterDep); return MAX (Bigger, NoneNeibAfterDep);
} }
/** /**
@@ -626,6 +639,7 @@ AnalysisProcessorFeatures (
// //
SupportedMaskAnd (CpuFeaturesData->CapabilityPcd, CpuInitOrder->FeaturesSupportedMask, CpuFeaturesData->BitMaskSize); SupportedMaskAnd (CpuFeaturesData->CapabilityPcd, CpuInitOrder->FeaturesSupportedMask, CpuFeaturesData->BitMaskSize);
} }
// //
// Calculate the last setting // Calculate the last setting
// //
@@ -650,9 +664,11 @@ AnalysisProcessorFeatures (
} else { } else {
DEBUG ((DEBUG_INFO, "[Unsupport] ")); DEBUG ((DEBUG_INFO, "[Unsupport] "));
} }
DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize); DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize);
Entry = Entry->ForwardLink; Entry = Entry->ForwardLink;
} }
DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n")); DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));
DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize); DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize);
DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n")); DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n"));
@@ -680,8 +696,10 @@ AnalysisProcessorFeatures (
ASSERT (CpuFeatureInOrder != NULL); ASSERT (CpuFeatureInOrder != NULL);
InsertTailList (&CpuInitOrder->OrderList, &CpuFeatureInOrder->Link); InsertTailList (&CpuInitOrder->OrderList, &CpuFeatureInOrder->Link);
} }
Entry = Entry->ForwardLink; Entry = Entry->ForwardLink;
} }
// //
// Go through ordered feature list to initialize CPU features // Go through ordered feature list to initialize CPU features
// //
@@ -736,23 +754,24 @@ AnalysisProcessorFeatures (
// Check whether next feature has After type dependence with not neighborhood CPU // Check whether next feature has After type dependence with not neighborhood CPU
// Features in former CPU features. // Features in former CPU features.
// //
NoneNeibAfterDep = DetectNoneNeighborhoodFeatureScope(NextCpuFeatureInOrder, FALSE, &CpuInitOrder->OrderList); NoneNeibAfterDep = DetectNoneNeighborhoodFeatureScope (NextCpuFeatureInOrder, FALSE, &CpuInitOrder->OrderList);
} else { } else {
BeforeDep = NoneDepType; BeforeDep = NoneDepType;
AfterDep = NoneDepType; AfterDep = NoneDepType;
NoneNeibAfterDep = NoneDepType; NoneNeibAfterDep = NoneDepType;
} }
// //
// Check whether current feature has Before type dependence with none neighborhood // Check whether current feature has Before type dependence with none neighborhood
// CPU features in after Cpu features. // CPU features in after Cpu features.
// //
NoneNeibBeforeDep = DetectNoneNeighborhoodFeatureScope(CpuFeatureInOrder, TRUE, &CpuInitOrder->OrderList); NoneNeibBeforeDep = DetectNoneNeighborhoodFeatureScope (CpuFeatureInOrder, TRUE, &CpuInitOrder->OrderList);
// //
// Get the biggest dependence and add semaphore for it. // Get the biggest dependence and add semaphore for it.
// PackageDepType > CoreDepType > ThreadDepType > NoneDepType. // PackageDepType > CoreDepType > ThreadDepType > NoneDepType.
// //
BeforeDep = BiggestDep(BeforeDep, AfterDep, NoneNeibBeforeDep, NoneNeibAfterDep); BeforeDep = BiggestDep (BeforeDep, AfterDep, NoneNeibBeforeDep, NoneNeibAfterDep);
if (BeforeDep > ThreadDepType) { if (BeforeDep > ThreadDepType) {
CPU_REGISTER_TABLE_WRITE32 (ProcessorNumber, Semaphore, 0, BeforeDep); CPU_REGISTER_TABLE_WRITE32 (ProcessorNumber, Semaphore, 0, BeforeDep);
} }
@@ -839,6 +858,7 @@ ReadWriteCr (
} else { } else {
AsmWriteCr0 (*CrValue); AsmWriteCr0 (*CrValue);
} }
break; break;
case 2: case 2:
if (Read) { if (Read) {
@@ -846,6 +866,7 @@ ReadWriteCr (
} else { } else {
AsmWriteCr2 (*CrValue); AsmWriteCr2 (*CrValue);
} }
break; break;
case 3: case 3:
if (Read) { if (Read) {
@@ -853,6 +874,7 @@ ReadWriteCr (
} else { } else {
AsmWriteCr3 (*CrValue); AsmWriteCr3 (*CrValue);
} }
break; break;
case 4: case 4:
if (Read) { if (Read) {
@@ -860,9 +882,10 @@ ReadWriteCr (
} else { } else {
AsmWriteCr4 (*CrValue); AsmWriteCr4 (*CrValue);
} }
break; break;
default: default:
return EFI_UNSUPPORTED;; return EFI_UNSUPPORTED;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
@@ -903,10 +926,9 @@ ProgramProcessorRegister (
// //
// Traverse Register Table of this logical processor // Traverse Register Table of this logical processor
// //
RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
for (Index = 0; Index < RegisterTable->TableLength; Index++) { for (Index = 0; Index < RegisterTable->TableLength; Index++) {
RegisterTableEntry = &RegisterTableEntryHead[Index]; RegisterTableEntry = &RegisterTableEntryHead[Index];
// //
@@ -921,6 +943,7 @@ ProgramProcessorRegister (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
break; break;
} }
if (RegisterTableEntry->TestThenWrite) { if (RegisterTableEntry->TestThenWrite) {
CurrentValue = BitFieldRead64 ( CurrentValue = BitFieldRead64 (
Value, Value,
@@ -931,7 +954,8 @@ ProgramProcessorRegister (
break; break;
} }
} }
Value = (UINTN) BitFieldWrite64 (
Value = (UINTN)BitFieldWrite64 (
Value, Value,
RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
@@ -981,6 +1005,7 @@ ProgramProcessorRegister (
RegisterTableEntry->Value RegisterTableEntry->Value
); );
} }
break; break;
// //
// MemoryMapped operations // MemoryMapped operations
@@ -1007,6 +1032,7 @@ ProgramProcessorRegister (
} else { } else {
AsmEnableCache (); AsmEnableCache ();
} }
break; break;
case Semaphore: case Semaphore:
@@ -1051,15 +1077,17 @@ ProgramProcessorRegister (
// //
// First Notify ALL THREADs in current Core that this thread is ready. // First Notify ALL THREADs in current Core that this thread is ready.
// //
for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) { for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {
LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
} }
// //
// Second, check whether all VALID THREADs (not all threads) in current core are ready. // Second, check whether all VALID THREADs (not all threads) in current core are ready.
// //
for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex ++) { for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {
LibWaitForSemaphore (&SemaphorePtr[CurrentThread]); LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);
} }
break; break;
case PackageDepType: case PackageDepType:
@@ -1089,20 +1117,23 @@ ProgramProcessorRegister (
// //
// First Notify ALL THREADS in current package that this thread is ready. // First Notify ALL THREADS in current package that this thread is ready.
// //
for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex ++) { for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {
LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
} }
// //
// Second, check whether VALID THREADS (not all threads) in current package are ready. // Second, check whether VALID THREADS (not all threads) in current package are ready.
// //
for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex ++) { for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {
LibWaitForSemaphore (&SemaphorePtr[CurrentThread]); LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);
} }
break; break;
default: default:
break; break;
} }
break; break;
default: default:
@@ -1131,7 +1162,7 @@ SetProcessorRegister (
UINTN Index; UINTN Index;
ACPI_CPU_DATA *AcpiCpuData; ACPI_CPU_DATA *AcpiCpuData;
CpuFeaturesData = (CPU_FEATURES_DATA *) Buffer; CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;
AcpiCpuData = CpuFeaturesData->AcpiCpuData; AcpiCpuData = CpuFeaturesData->AcpiCpuData;
RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable; RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable;
@@ -1146,6 +1177,7 @@ SetProcessorRegister (
break; break;
} }
} }
ASSERT (RegisterTable != NULL); ASSERT (RegisterTable != NULL);
ProgramProcessorRegister ( ProgramProcessorRegister (
@@ -1172,7 +1204,7 @@ CpuFeaturesDetect (
{ {
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData(); CpuFeaturesData = GetCpuFeaturesData ();
CpuInitDataInitialize (); CpuInitDataInitialize ();

6
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
View File

@@ -13,7 +13,7 @@
#include "RegisterCpuFeatures.h" #include "RegisterCpuFeatures.h"
CPU_FEATURES_DATA mCpuFeaturesData = {0}; CPU_FEATURES_DATA mCpuFeaturesData = { 0 };
/** /**
Worker function to get CPU_FEATURES_DATA pointer. Worker function to get CPU_FEATURES_DATA pointer.
@@ -71,7 +71,7 @@ GetProcessorIndex (
EFI_MP_SERVICES_PROTOCOL *MpServices; EFI_MP_SERVICES_PROTOCOL *MpServices;
MpServices = CpuFeaturesData->MpService.Protocol; MpServices = CpuFeaturesData->MpService.Protocol;
Status = MpServices->WhoAmI(MpServices, &ProcessorIndex); Status = MpServices->WhoAmI (MpServices, &ProcessorIndex);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return ProcessorIndex; return ProcessorIndex;
} }
@@ -263,6 +263,7 @@ CpuFeaturesInitialize (
do { do {
Status = gBS->CheckEvent (MpEvent); Status = gBS->CheckEvent (MpEvent);
} while (Status == EFI_NOT_READY); } while (Status == EFI_NOT_READY);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -273,4 +274,3 @@ CpuFeaturesInitialize (
SwitchNewBsp (CpuFeaturesData->BspNumber); SwitchNewBsp (CpuFeaturesData->BspNumber);
} }
} }

7
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
View File

@@ -41,7 +41,7 @@ GetCpuFeaturesData (
GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid); GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid);
if (GuidHob != NULL) { if (GuidHob != NULL) {
DataInHob = GET_GUID_HOB_DATA (GuidHob); DataInHob = GET_GUID_HOB_DATA (GuidHob);
CpuInitData = (CPU_FEATURES_DATA *) (*(UINTN *) DataInHob); CpuInitData = (CPU_FEATURES_DATA *)(*(UINTN *)DataInHob);
ASSERT (CpuInitData != NULL); ASSERT (CpuInitData != NULL);
} else { } else {
CpuInitData = AllocateZeroPool (sizeof (CPU_FEATURES_DATA)); CpuInitData = AllocateZeroPool (sizeof (CPU_FEATURES_DATA));
@@ -49,10 +49,10 @@ GetCpuFeaturesData (
// //
// Build location of CPU MP DATA buffer in HOB // Build location of CPU MP DATA buffer in HOB
// //
Data64 = (UINT64) (UINTN) CpuInitData; Data64 = (UINT64)(UINTN)CpuInitData;
BuildGuidDataHob ( BuildGuidDataHob (
&mRegisterCpuFeaturesHobGuid, &mRegisterCpuFeaturesHobGuid,
(VOID *) &Data64, (VOID *)&Data64,
sizeof (UINT64) sizeof (UINT64)
); );
} }
@@ -306,4 +306,3 @@ CpuFeaturesInitialize (
SwitchNewBsp (CpuFeaturesData->BspNumber); SwitchNewBsp (CpuFeaturesData->BspNumber);
} }
} }

125
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
View File

@@ -24,10 +24,11 @@ DumpCpuFeatureMask (
UINTN Index; UINTN Index;
UINT8 *Data8; UINT8 *Data8;
Data8 = (UINT8 *) FeatureMask; Data8 = (UINT8 *)FeatureMask;
for (Index = 0; Index < BitMaskSize; Index++) { for (Index = 0; Index < BitMaskSize; Index++) {
DEBUG ((DEBUG_INFO, " %02x ", *Data8++)); DEBUG ((DEBUG_INFO, " %02x ", *Data8++));
} }
DEBUG ((DEBUG_INFO, "\n")); DEBUG ((DEBUG_INFO, "\n"));
} }
@@ -44,7 +45,6 @@ DumpCpuFeature (
IN UINT32 BitMaskSize IN UINT32 BitMaskSize
) )
{ {
if (CpuFeature->FeatureName != NULL) { if (CpuFeature->FeatureName != NULL) {
DEBUG ((DEBUG_INFO, "FeatureName: %a\n", CpuFeature->FeatureName)); DEBUG ((DEBUG_INFO, "FeatureName: %a\n", CpuFeature->FeatureName));
} else { } else {
@@ -82,6 +82,7 @@ IsBitMaskMatchCheck (
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }
@@ -185,17 +186,20 @@ DetectFeatureScope (
if (Before) { if (Before) {
if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) && if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask)) { IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask))
{
return PackageDepType; return PackageDepType;
} }
if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) && if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask)) { IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask))
{
return CoreDepType; return CoreDepType;
} }
if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) && if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask)) { IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask))
{
return ThreadDepType; return ThreadDepType;
} }
@@ -203,17 +207,20 @@ DetectFeatureScope (
} }
if ((CpuFeature->PackageAfterFeatureBitMask != NULL) && if ((CpuFeature->PackageAfterFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask)) { IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask))
{
return PackageDepType; return PackageDepType;
} }
if ((CpuFeature->CoreAfterFeatureBitMask != NULL) && if ((CpuFeature->CoreAfterFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask)) { IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask))
{
return CoreDepType; return CoreDepType;
} }
if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) && if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask)) { IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask))
{
return ThreadDepType; return ThreadDepType;
} }
@@ -238,17 +245,20 @@ DetectNoneNeighborhoodFeatureScope (
{ {
if (Before) { if (Before) {
if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) && if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask)) { FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask))
{
return PackageDepType; return PackageDepType;
} }
if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) && if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask)) { FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask))
{
return CoreDepType; return CoreDepType;
} }
if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) && if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask)) { FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask))
{
return ThreadDepType; return ThreadDepType;
} }
@@ -256,17 +266,20 @@ DetectNoneNeighborhoodFeatureScope (
} }
if ((CpuFeature->PackageAfterFeatureBitMask != NULL) && if ((CpuFeature->PackageAfterFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask)) { FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask))
{
return PackageDepType; return PackageDepType;
} }
if ((CpuFeature->CoreAfterFeatureBitMask != NULL) && if ((CpuFeature->CoreAfterFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask)) { FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask))
{
return CoreDepType; return CoreDepType;
} }
if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) && if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask)) { FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask))
{
return ThreadDepType; return ThreadDepType;
} }
@@ -303,8 +316,8 @@ AdjustFeaturesDependence (
CPU_FEATURE_DEPENDENCE_TYPE PreDependType; CPU_FEATURE_DEPENDENCE_TYPE PreDependType;
CPU_FEATURE_DEPENDENCE_TYPE CurrentDependType; CPU_FEATURE_DEPENDENCE_TYPE CurrentDependType;
PreDependType = DetectFeatureScope(PreviousFeature, Before, FindFeature->FeatureMask); PreDependType = DetectFeatureScope (PreviousFeature, Before, FindFeature->FeatureMask);
CurrentDependType = DetectFeatureScope(CurrentFeature, Before, FindFeature->FeatureMask); CurrentDependType = DetectFeatureScope (CurrentFeature, Before, FindFeature->FeatureMask);
// //
// If previous feature has no dependence with the find featue. // If previous feature has no dependence with the find featue.
@@ -363,7 +376,6 @@ AdjustEntry (
if (Before) { if (Before) {
PreviousEntry = GetPreviousNode (FeatureList, FindEntry); PreviousEntry = GetPreviousNode (FeatureList, FindEntry);
} else { } else {
PreviousEntry = GetNextNode (FeatureList, FindEntry); PreviousEntry = GetNextNode (FeatureList, FindEntry);
} }
@@ -407,7 +419,6 @@ AdjustEntry (
} }
} }
/** /**
Checks and adjusts current CPU features per dependency relationship. Checks and adjusts current CPU features per dependency relationship.
@@ -441,6 +452,7 @@ InsertToBeforeEntry (
Swapped = TRUE; Swapped = TRUE;
break; break;
} }
CheckEntry = CheckEntry->ForwardLink; CheckEntry = CheckEntry->ForwardLink;
} }
@@ -480,6 +492,7 @@ InsertToAfterEntry (
Swapped = TRUE; Swapped = TRUE;
break; break;
} }
CheckEntry = CheckEntry->ForwardLink; CheckEntry = CheckEntry->ForwardLink;
} }
@@ -526,8 +539,10 @@ CheckCpuFeaturesDependency (
Swapped = TRUE; Swapped = TRUE;
break; break;
} }
CheckEntry = CheckEntry->ForwardLink; CheckEntry = CheckEntry->ForwardLink;
} }
if (Swapped) { if (Swapped) {
CurrentEntry = NextEntry; CurrentEntry = NextEntry;
continue; continue;
@@ -553,8 +568,10 @@ CheckCpuFeaturesDependency (
Swapped = TRUE; Swapped = TRUE;
break; break;
} }
CheckEntry = CheckEntry->ForwardLink; CheckEntry = CheckEntry->ForwardLink;
} }
if (Swapped) { if (Swapped) {
CurrentEntry = NextEntry; CurrentEntry = NextEntry;
continue; continue;
@@ -643,6 +660,7 @@ RegisterCpuFeatureWorker (
FeatureExist = TRUE; FeatureExist = TRUE;
break; break;
} }
Entry = Entry->ForwardLink; Entry = Entry->ForwardLink;
} }
@@ -661,55 +679,71 @@ RegisterCpuFeatureWorker (
if (CpuFeature->GetConfigDataFunc != NULL) { if (CpuFeature->GetConfigDataFunc != NULL) {
CpuFeatureEntry->GetConfigDataFunc = CpuFeature->GetConfigDataFunc; CpuFeatureEntry->GetConfigDataFunc = CpuFeature->GetConfigDataFunc;
} }
if (CpuFeature->SupportFunc != NULL) { if (CpuFeature->SupportFunc != NULL) {
CpuFeatureEntry->SupportFunc = CpuFeature->SupportFunc; CpuFeatureEntry->SupportFunc = CpuFeature->SupportFunc;
} }
if (CpuFeature->InitializeFunc != NULL) { if (CpuFeature->InitializeFunc != NULL) {
CpuFeatureEntry->InitializeFunc = CpuFeature->InitializeFunc; CpuFeatureEntry->InitializeFunc = CpuFeature->InitializeFunc;
} }
if (CpuFeature->FeatureName != NULL) { if (CpuFeature->FeatureName != NULL) {
if (CpuFeatureEntry->FeatureName == NULL) { if (CpuFeatureEntry->FeatureName == NULL) {
CpuFeatureEntry->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE); CpuFeatureEntry->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE);
ASSERT (CpuFeatureEntry->FeatureName != NULL); ASSERT (CpuFeatureEntry->FeatureName != NULL);
} }
Status = AsciiStrCpyS (CpuFeatureEntry->FeatureName, CPU_FEATURE_NAME_SIZE, CpuFeature->FeatureName); Status = AsciiStrCpyS (CpuFeatureEntry->FeatureName, CPU_FEATURE_NAME_SIZE, CpuFeature->FeatureName);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
FreePool (CpuFeature->FeatureName); FreePool (CpuFeature->FeatureName);
} }
if (CpuFeature->ThreadBeforeFeatureBitMask != NULL) { if (CpuFeature->ThreadBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->ThreadBeforeFeatureBitMask != NULL) { if (CpuFeatureEntry->ThreadBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->ThreadBeforeFeatureBitMask); FreePool (CpuFeatureEntry->ThreadBeforeFeatureBitMask);
} }
CpuFeatureEntry->ThreadBeforeFeatureBitMask = CpuFeature->ThreadBeforeFeatureBitMask; CpuFeatureEntry->ThreadBeforeFeatureBitMask = CpuFeature->ThreadBeforeFeatureBitMask;
} }
if (CpuFeature->ThreadAfterFeatureBitMask != NULL) { if (CpuFeature->ThreadAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->ThreadAfterFeatureBitMask != NULL) { if (CpuFeatureEntry->ThreadAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->ThreadAfterFeatureBitMask); FreePool (CpuFeatureEntry->ThreadAfterFeatureBitMask);
} }
CpuFeatureEntry->ThreadAfterFeatureBitMask = CpuFeature->ThreadAfterFeatureBitMask; CpuFeatureEntry->ThreadAfterFeatureBitMask = CpuFeature->ThreadAfterFeatureBitMask;
} }
if (CpuFeature->CoreBeforeFeatureBitMask != NULL) { if (CpuFeature->CoreBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->CoreBeforeFeatureBitMask != NULL) { if (CpuFeatureEntry->CoreBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->CoreBeforeFeatureBitMask); FreePool (CpuFeatureEntry->CoreBeforeFeatureBitMask);
} }
CpuFeatureEntry->CoreBeforeFeatureBitMask = CpuFeature->CoreBeforeFeatureBitMask; CpuFeatureEntry->CoreBeforeFeatureBitMask = CpuFeature->CoreBeforeFeatureBitMask;
} }
if (CpuFeature->CoreAfterFeatureBitMask != NULL) { if (CpuFeature->CoreAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->CoreAfterFeatureBitMask != NULL) { if (CpuFeatureEntry->CoreAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->CoreAfterFeatureBitMask); FreePool (CpuFeatureEntry->CoreAfterFeatureBitMask);
} }
CpuFeatureEntry->CoreAfterFeatureBitMask = CpuFeature->CoreAfterFeatureBitMask; CpuFeatureEntry->CoreAfterFeatureBitMask = CpuFeature->CoreAfterFeatureBitMask;
} }
if (CpuFeature->PackageBeforeFeatureBitMask != NULL) { if (CpuFeature->PackageBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->PackageBeforeFeatureBitMask != NULL) { if (CpuFeatureEntry->PackageBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->PackageBeforeFeatureBitMask); FreePool (CpuFeatureEntry->PackageBeforeFeatureBitMask);
} }
CpuFeatureEntry->PackageBeforeFeatureBitMask = CpuFeature->PackageBeforeFeatureBitMask; CpuFeatureEntry->PackageBeforeFeatureBitMask = CpuFeature->PackageBeforeFeatureBitMask;
} }
if (CpuFeature->PackageAfterFeatureBitMask != NULL) { if (CpuFeature->PackageAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->PackageAfterFeatureBitMask != NULL) { if (CpuFeatureEntry->PackageAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->PackageAfterFeatureBitMask); FreePool (CpuFeatureEntry->PackageAfterFeatureBitMask);
} }
CpuFeatureEntry->PackageAfterFeatureBitMask = CpuFeature->PackageAfterFeatureBitMask; CpuFeatureEntry->PackageAfterFeatureBitMask = CpuFeature->PackageAfterFeatureBitMask;
} }
@@ -719,6 +753,7 @@ RegisterCpuFeatureWorker (
FreePool (CpuFeature->FeatureMask); FreePool (CpuFeature->FeatureMask);
FreePool (CpuFeature); FreePool (CpuFeature);
} }
// //
// Verify CPU features dependency can change CPU feature order // Verify CPU features dependency can change CPU feature order
// //
@@ -751,7 +786,7 @@ SetCpuFeaturesBitMask (
} }
CpuFeaturesBitMask += (Feature / 8); CpuFeaturesBitMask += (Feature / 8);
*CpuFeaturesBitMask |= (UINT8) (1 << (Feature % 8)); *CpuFeaturesBitMask |= (UINT8)(1 << (Feature % 8));
} }
/** /**
@@ -844,7 +879,7 @@ RegisterCpuFeature (
// //
ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesCapability)); ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesCapability));
ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesSupport)); ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesSupport));
CpuFeaturesData->BitMaskSize = (UINT32) PcdGetSize (PcdCpuFeaturesSetting); CpuFeaturesData->BitMaskSize = (UINT32)PcdGetSize (PcdCpuFeaturesSetting);
} }
VA_START (Marker, InitializeFunc); VA_START (Marker, InitializeFunc);
@@ -853,19 +888,27 @@ RegisterCpuFeature (
// //
// It's invalid to require a feature is before AND after all other features. // It's invalid to require a feature is before AND after all other features.
// //
ASSERT ((Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)) ASSERT (
!= (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)); (Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL))
!= (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)
);
// //
// It's invalid to require feature A is before AND after before feature B, // It's invalid to require feature A is before AND after before feature B,
// either in thread level, core level or package level. // either in thread level, core level or package level.
// //
ASSERT ((Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)) ASSERT (
!= (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)); (Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER))
ASSERT ((Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)) != (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)
!= (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)); );
ASSERT ((Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)) ASSERT (
!= (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)); (Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER))
!= (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)
);
ASSERT (
(Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))
!= (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)
);
if (Feature < CPU_FEATURE_THREAD_BEFORE) { if (Feature < CPU_FEATURE_THREAD_BEFORE) {
BeforeAll = ((Feature & CPU_FEATURE_BEFORE_ALL) != 0) ? TRUE : FALSE; BeforeAll = ((Feature & CPU_FEATURE_BEFORE_ALL) != 0) ? TRUE : FALSE;
AfterAll = ((Feature & CPU_FEATURE_AFTER_ALL) != 0) ? TRUE : FALSE; AfterAll = ((Feature & CPU_FEATURE_AFTER_ALL) != 0) ? TRUE : FALSE;
@@ -885,8 +928,10 @@ RegisterCpuFeature (
} else if ((Feature & CPU_FEATURE_PACKAGE_AFTER) != 0) { } else if ((Feature & CPU_FEATURE_PACKAGE_AFTER) != 0) {
SetCpuFeaturesBitMask (&PackageAfterFeatureBitMask, Feature & ~CPU_FEATURE_PACKAGE_AFTER, CpuFeaturesData->BitMaskSize); SetCpuFeaturesBitMask (&PackageAfterFeatureBitMask, Feature & ~CPU_FEATURE_PACKAGE_AFTER, CpuFeaturesData->BitMaskSize);
} }
Feature = VA_ARG (Marker, UINT32); Feature = VA_ARG (Marker, UINT32);
} }
VA_END (Marker); VA_END (Marker);
CpuFeature = AllocateZeroPool (sizeof (CPU_FEATURES_ENTRY)); CpuFeature = AllocateZeroPool (sizeof (CPU_FEATURES_ENTRY));
@@ -936,7 +981,7 @@ GetAcpiCpuData (
UINTN Index; UINTN Index;
EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer; EFI_PROCESSOR_INFORMATION ProcessorInfoBuffer;
AcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress); AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
if (AcpiCpuData == NULL) { if (AcpiCpuData == NULL) {
AcpiCpuData = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA))); AcpiCpuData = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA)));
ASSERT (AcpiCpuData != NULL); ASSERT (AcpiCpuData != NULL);
@@ -952,8 +997,9 @@ GetAcpiCpuData (
AcpiCpuData->NumberOfCpus = (UINT32)NumberOfCpus; AcpiCpuData->NumberOfCpus = (UINT32)NumberOfCpus;
} }
if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0 || if ((AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) ||
AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) { (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0))
{
// //
// Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for all CPUs // Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for all CPUs
// //
@@ -976,9 +1022,11 @@ GetAcpiCpuData (
RegisterTable[NumberOfCpus + Index].AllocatedSize = 0; RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;
RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0; RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;
} }
if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) { if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) {
AcpiCpuData->CpuFeatureInitData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable; AcpiCpuData->CpuFeatureInitData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;
} }
if (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) { if (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) {
AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus); AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);
} }
@@ -1011,8 +1059,8 @@ EnlargeRegisterTable (
// //
if (RegisterTable->AllocatedSize > 0) { if (RegisterTable->AllocatedSize > 0) {
CopyMem ( CopyMem (
(VOID *) (UINTN) Address, (VOID *)(UINTN)Address,
(VOID *) (UINTN) RegisterTable->RegisterTableEntry, (VOID *)(UINTN)RegisterTable->RegisterTableEntry,
RegisterTable->AllocatedSize RegisterTable->AllocatedSize
); );
@@ -1064,8 +1112,8 @@ CpuRegisterTableWriteWorker (
if (CpuFeaturesData->RegisterTable == NULL) { if (CpuFeaturesData->RegisterTable == NULL) {
AcpiCpuData = GetAcpiCpuData (); AcpiCpuData = GetAcpiCpuData ();
ASSERT ((AcpiCpuData != NULL) && (AcpiCpuData->CpuFeatureInitData.RegisterTable != 0)); ASSERT ((AcpiCpuData != NULL) && (AcpiCpuData->CpuFeatureInitData.RegisterTable != 0));
CpuFeaturesData->RegisterTable = (CPU_REGISTER_TABLE *) (UINTN) AcpiCpuData->CpuFeatureInitData.RegisterTable; CpuFeaturesData->RegisterTable = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable;
CpuFeaturesData->PreSmmRegisterTable = (CPU_REGISTER_TABLE *) (UINTN) AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable; CpuFeaturesData->PreSmmRegisterTable = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable;
} }
if (PreSmmFlag) { if (PreSmmFlag) {
@@ -1081,10 +1129,10 @@ CpuRegisterTableWriteWorker (
// //
// Append entry in the register table. // Append entry in the register table.
// //
RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType; RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType;
RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32) Index; RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32)Index;
RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32) RShiftU64 (Index, 32); RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32)RShiftU64 (Index, 32);
RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart; RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart;
RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength; RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength;
RegisterTableEntry[RegisterTable->TableLength].Value = Value; RegisterTableEntry[RegisterTable->TableLength].Value = Value;
@@ -1216,6 +1264,7 @@ IsCpuFeatureSetInCpuPcd (
if ((Feature >> 3) >= CpuBitMaskSize) { if ((Feature >> 3) >= CpuBitMaskSize) {
return FALSE; return FALSE;
} }
return ((*(CpuBitMask + (Feature >> 3)) & (1 << (Feature & 0x07))) != 0); return ((*(CpuBitMask + (Feature >> 3)) & (1 << (Feature & 0x07))) != 0);
} }

8
UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
View File

@@ -30,7 +30,7 @@ InternalX86GetTimerFrequency (
UINTN Divisor; UINTN Divisor;
GetApicTimerState (&Divisor, NULL, NULL); GetApicTimerState (&Divisor, NULL, NULL);
return PcdGet32(PcdFSBClock) / (UINT32)Divisor; return PcdGet32 (PcdFSBClock) / (UINT32)Divisor;
} }
/** /**
@@ -212,7 +212,7 @@ GetPerformanceCounterProperties (
*EndValue = 0; *EndValue = 0;
} }
return (UINT64) InternalX86GetTimerFrequency (); return (UINT64)InternalX86GetTimerFrequency ();
} }
/** /**
@@ -252,8 +252,8 @@ GetTimeInNanoSecond (
// i.e. highest bit set in Remainder should <= 33. // i.e. highest bit set in Remainder should <= 33.
// //
Shift = MAX (0, HighBitSet64 (Remainder) - 33); Shift = MAX (0, HighBitSet64 (Remainder) - 33);
Remainder = RShiftU64 (Remainder, (UINTN) Shift); Remainder = RShiftU64 (Remainder, (UINTN)Shift);
Frequency = RShiftU64 (Frequency, (UINTN) Shift); Frequency = RShiftU64 (Frequency, (UINTN)Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL); NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds; return NanoSeconds;

2
UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
View File

@@ -35,7 +35,7 @@ StmGen4GPageTable (
UINT32 *Pte; UINT32 *Pte;
UINT32 Address; UINT32 Address;
Pte = (UINT32*)(UINTN)PageTableBase; Pte = (UINT32 *)(UINTN)PageTableBase;
Address = 0; Address = 0;
for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) { for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) {

35
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
View File

@@ -86,7 +86,7 @@ CpuFeaturesLibInitialization (
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
FamilyId = (RegEax >> 8) & 0xf; FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf; ModelId = (RegEax >> 4) & 0xf;
if (FamilyId == 0x06 || FamilyId == 0x0f) { if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0); ModelId = ModelId | ((RegEax >> 12) & 0xf0);
} }
@@ -110,7 +110,7 @@ CpuFeaturesLibInitialization (
// SMRR Physical Base and SMM Physical Mask MSRs are not available. // SMRR Physical Base and SMM Physical Mask MSRs are not available.
// //
if (FamilyId == 0x06) { if (FamilyId == 0x06) {
if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) { if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {
mSmrrSupported = FALSE; mSmrrSupported = FALSE;
} }
} }
@@ -123,7 +123,7 @@ CpuFeaturesLibInitialization (
// Processor Family MSRs // Processor Family MSRs
// //
if (FamilyId == 0x06) { if (FamilyId == 0x06) {
if (ModelId == 0x17 || ModelId == 0x0f) { if ((ModelId == 0x17) || (ModelId == 0x0f)) {
mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE; mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK; mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
} }
@@ -216,7 +216,7 @@ SmmCpuFeaturesInitializeProcessor (
// accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A) // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
// is set, then the MSR is locked and can not be modified. // is set, then the MSR is locked and can not be modified.
// //
if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) { if (mSmrrSupported && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {
FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL); FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);
if ((FeatureControl & BIT3) == 0) { if ((FeatureControl & BIT3) == 0) {
if ((FeatureControl & BIT0) == 0) { if ((FeatureControl & BIT0) == 0) {
@@ -242,7 +242,8 @@ SmmCpuFeaturesInitializeProcessor (
// //
if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
(CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) || (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) { ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
{
// //
// Print message and halt if CPU is Monarch // Print message and halt if CPU is Monarch
// //
@@ -263,7 +264,7 @@ SmmCpuFeaturesInitializeProcessor (
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
FamilyId = (RegEax >> 8) & 0xf; FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf; ModelId = (RegEax >> 4) & 0xf;
if (FamilyId == 0x06 || FamilyId == 0x0f) { if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0); ModelId = ModelId | ((RegEax >> 12) & 0xf0);
} }
@@ -276,10 +277,11 @@ SmmCpuFeaturesInitializeProcessor (
// Intel(R) Core(TM) Processor Family MSRs. // Intel(R) Core(TM) Processor Family MSRs.
// //
if (FamilyId == 0x06) { if (FamilyId == 0x06) {
if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 || if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) ||
ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F || (ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) ||
ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C || (ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) ||
ModelId == 0x8C) { (ModelId == 0x8C))
{
// //
// Check to see if the CPU supports the SMM Code Access Check feature // Check to see if the CPU supports the SMM Code Access Check feature
// Do not access this MSR unless the CPU supports the SmmRegFeatureControl // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
@@ -382,7 +384,7 @@ SmmCpuFeaturesDisableSmrr (
) )
{ {
if (mSmrrSupported && mNeedConfigureMtrrs) { if (mSmrrSupported && mNeedConfigureMtrrs) {
AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID); AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);
} }
} }
@@ -397,7 +399,7 @@ SmmCpuFeaturesReenableSmrr (
) )
{ {
if (mSmrrSupported && mNeedConfigureMtrrs) { if (mSmrrSupported && mNeedConfigureMtrrs) {
AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID); AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);
} }
} }
@@ -458,9 +460,10 @@ SmmCpuFeaturesIsSmmRegisterSupported (
IN SMM_REG_NAME RegName IN SMM_REG_NAME RegName
) )
{ {
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
return TRUE; return TRUE;
} }
return FALSE; return FALSE;
} }
@@ -483,9 +486,10 @@ SmmCpuFeaturesGetSmmRegister (
IN SMM_REG_NAME RegName IN SMM_REG_NAME RegName
) )
{ {
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL); return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
} }
return 0; return 0;
} }
@@ -508,7 +512,7 @@ SmmCpuFeaturesSetSmmRegister (
IN UINT64 Value IN UINT64 Value
) )
{ {
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) { if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value); AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
} }
} }
@@ -610,4 +614,3 @@ SmmCpuFeaturesAllocatePageTableMemory (
{ {
return NULL; return NULL;
} }

124
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
View File

@@ -38,7 +38,7 @@ BOOLEAN mLockLoadMonitor = FALSE;
// Template of STM_RSC_END structure for copying. // Template of STM_RSC_END structure for copying.
// //
GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode = { GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode = {
{END_OF_RESOURCES, sizeof (STM_RSC_END)}, { END_OF_RESOURCES, sizeof (STM_RSC_END) },
}; };
GLOBAL_REMOVE_IF_UNREFERENCED UINT8 *mStmResourcesPtr = NULL; GLOBAL_REMOVE_IF_UNREFERENCED UINT8 *mStmResourcesPtr = NULL;
@@ -60,9 +60,6 @@ EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = {
GetMonitorState, GetMonitorState,
}; };
#define CPUID1_EDX_XD_SUPPORT 0x100000 #define CPUID1_EDX_XD_SUPPORT 0x100000
// //
@@ -146,7 +143,7 @@ SmmCpuFeaturesLibStmConstructor (
// //
// Retrieve MSEG location from MSEG SRAM HOB // Retrieve MSEG location from MSEG SRAM HOB
// //
SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob); SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);
if (SmramDescriptor->PhysicalSize > 0) { if (SmramDescriptor->PhysicalSize > 0) {
mMsegBase = (UINTN)SmramDescriptor->CpuStart; mMsegBase = (UINTN)SmramDescriptor->CpuStart;
mMsegSize = (UINTN)SmramDescriptor->PhysicalSize; mMsegSize = (UINTN)SmramDescriptor->PhysicalSize;
@@ -162,6 +159,7 @@ SmmCpuFeaturesLibStmConstructor (
DEBUG ((DEBUG_ERROR, "Not enough SMRAM resource to allocate MSEG size %08x\n", PcdGet32 (PcdCpuMsegSize))); DEBUG ((DEBUG_ERROR, "Not enough SMRAM resource to allocate MSEG size %08x\n", PcdGet32 (PcdCpuMsegSize)));
} }
} }
if (mMsegBase > 0) { if (mMsegBase > 0) {
DEBUG ((DEBUG_INFO, "MsegBase: 0x%08x, MsegSize: 0x%08x\n", mMsegBase, mMsegSize)); DEBUG ((DEBUG_INFO, "MsegBase: 0x%08x, MsegSize: 0x%08x\n", mMsegBase, mMsegSize));
} }
@@ -293,23 +291,23 @@ SmmCpuFeaturesInstallSmiHandler (
// //
// Set the value at the top of the CPU stack to the CPU Index // Set the value at the top of the CPU stack to the CPU Index
// //
*(UINTN*)(UINTN)gStmSmiStack = CpuIndex; *(UINTN *)(UINTN)gStmSmiStack = CpuIndex;
// //
// Copy template to CPU specific SMI handler location // Copy template to CPU specific SMI handler location
// //
CopyMem ( CopyMem (
(VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET), (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET),
(VOID*)gcStmSmiHandlerTemplate, (VOID *)gcStmSmiHandlerTemplate,
gcStmSmiHandlerSize gcStmSmiHandlerSize
); );
Psd->SmmSmiHandlerRip = SmBase + SMM_HANDLER_OFFSET + gcStmSmiHandlerOffset; Psd->SmmSmiHandlerRip = SmBase + SMM_HANDLER_OFFSET + gcStmSmiHandlerOffset;
Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof(UINTN); Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof (UINTN);
Psd->SmmCr3 = Cr3; Psd->SmmCr3 = Cr3;
DEBUG((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32(PcdCpuSmmStmExceptionStackSize))); DEBUG ((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
DEBUG((DEBUG_INFO, "Pages - %x\n", EFI_SIZE_TO_PAGES(PcdGet32(PcdCpuSmmStmExceptionStackSize)))); DEBUG ((DEBUG_INFO, "Pages - %x\n", EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize))));
Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize))); Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
Psd->StmProtectionExceptionHandler.SpeRsp += EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize))); Psd->StmProtectionExceptionHandler.SpeRsp += EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));
@@ -330,12 +328,12 @@ SmmCpuFeaturesInstallSmiHandler (
Hob = GetFirstHob (EFI_HOB_TYPE_CPU); Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
if (Hob != NULL) { if (Hob != NULL) {
Psd->PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; Psd->PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else { } else {
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) { if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
Psd->PhysicalAddressBits = (UINT8) RegEax; Psd->PhysicalAddressBits = (UINT8)RegEax;
} else { } else {
Psd->PhysicalAddressBits = 36; Psd->PhysicalAddressBits = 36;
} }
@@ -385,6 +383,7 @@ SmmEndOfDxeEventNotify (
break; break;
} }
} }
if (Rsdp == NULL) { if (Rsdp == NULL) {
for (Index = 0; Index < gST->NumberOfTableEntries; Index++) { for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), &gEfiAcpi10TableGuid)) { if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), &gEfiAcpi10TableGuid)) {
@@ -502,26 +501,30 @@ HandleSingleResource (
return FALSE; return FALSE;
} }
} }
break; break;
case IO_RANGE: case IO_RANGE:
case TRAPPED_IO_RANGE: case TRAPPED_IO_RANGE:
ResourceLo = (UINT64) Resource->Io.Base; ResourceLo = (UINT64)Resource->Io.Base;
ResourceHi = (UINT64) Resource->Io.Base + (UINT64) Resource->Io.Length; ResourceHi = (UINT64)Resource->Io.Base + (UINT64)Resource->Io.Length;
RecordLo = (UINT64) Record->Io.Base; RecordLo = (UINT64)Record->Io.Base;
RecordHi = (UINT64) Record->Io.Base + (UINT64) Record->Io.Length; RecordHi = (UINT64)Record->Io.Base + (UINT64)Record->Io.Length;
break; break;
case PCI_CFG_RANGE: case PCI_CFG_RANGE:
if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) || if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) ||
(Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) { (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex))
{
return FALSE; return FALSE;
} }
if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {
if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof (STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {
return FALSE; return FALSE;
} }
ResourceLo = (UINT64) Resource->PciCfg.Base;
ResourceHi = (UINT64) Resource->PciCfg.Base + (UINT64) Resource->PciCfg.Length; ResourceLo = (UINT64)Resource->PciCfg.Base;
RecordLo = (UINT64) Record->PciCfg.Base; ResourceHi = (UINT64)Resource->PciCfg.Base + (UINT64)Resource->PciCfg.Length;
RecordHi = (UINT64) Record->PciCfg.Base + (UINT64) Record->PciCfg.Length; RecordLo = (UINT64)Record->PciCfg.Base;
RecordHi = (UINT64)Record->PciCfg.Base + (UINT64)Record->PciCfg.Length;
if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) { if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) {
if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) { if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {
Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes; Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes;
@@ -530,6 +533,7 @@ HandleSingleResource (
return FALSE; return FALSE;
} }
} }
break; break;
case MACHINE_SPECIFIC_REG: case MACHINE_SPECIFIC_REG:
// //
@@ -538,12 +542,14 @@ HandleSingleResource (
if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) { if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) {
return FALSE; return FALSE;
} }
Record->Msr.ReadMask |= Resource->Msr.ReadMask; Record->Msr.ReadMask |= Resource->Msr.ReadMask;
Record->Msr.WriteMask |= Resource->Msr.WriteMask; Record->Msr.WriteMask |= Resource->Msr.WriteMask;
return TRUE; return TRUE;
default: default:
return FALSE; return FALSE;
} }
// //
// If resources are disjoint // If resources are disjoint
// //
@@ -557,6 +563,7 @@ HandleSingleResource (
if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) { if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) {
return TRUE; return TRUE;
} }
// //
// Resources are overlapping. // Resources are overlapping.
// Resource and record are merged. // Resource and record are merged.
@@ -572,12 +579,12 @@ HandleSingleResource (
break; break;
case IO_RANGE: case IO_RANGE:
case TRAPPED_IO_RANGE: case TRAPPED_IO_RANGE:
Record->Io.Base = (UINT16) ResourceLo; Record->Io.Base = (UINT16)ResourceLo;
Record->Io.Length = (UINT16) (ResourceHi - ResourceLo); Record->Io.Length = (UINT16)(ResourceHi - ResourceLo);
break; break;
case PCI_CFG_RANGE: case PCI_CFG_RANGE:
Record->PciCfg.Base = (UINT16) ResourceLo; Record->PciCfg.Base = (UINT16)ResourceLo;
Record->PciCfg.Length = (UINT16) (ResourceHi - ResourceLo); Record->PciCfg.Length = (UINT16)(ResourceHi - ResourceLo);
break; break;
default: default:
return FALSE; return FALSE;
@@ -606,6 +613,7 @@ AddSingleResource (
if (Record->Header.RscType == END_OF_RESOURCES) { if (Record->Header.RscType == END_OF_RESOURCES) {
break; break;
} }
// //
// Go to next record if resource and record types don't match. // Go to next record if resource and record types don't match.
// //
@@ -613,12 +621,14 @@ AddSingleResource (
Record = (STM_RSC *)((UINTN)Record + Record->Header.Length); Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);
continue; continue;
} }
// //
// Record is handled inside of procedure - don't adjust. // Record is handled inside of procedure - don't adjust.
// //
if (HandleSingleResource (Resource, Record)) { if (HandleSingleResource (Resource, Record)) {
return ; return;
} }
Record = (STM_RSC *)((UINTN)Record + Record->Header.Length); Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);
} }
@@ -626,19 +636,19 @@ AddSingleResource (
// Add resource to the end of area. // Add resource to the end of area.
// //
CopyMem ( CopyMem (
mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode), mStmResourcesPtr + mStmResourceSizeUsed - sizeof (mRscEndNode),
Resource, Resource,
Resource->Header.Length Resource->Header.Length
); );
CopyMem ( CopyMem (
mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length, mStmResourcesPtr + mStmResourceSizeUsed - sizeof (mRscEndNode) + Resource->Header.Length,
&mRscEndNode, &mRscEndNode,
sizeof(mRscEndNode) sizeof (mRscEndNode)
); );
mStmResourceSizeUsed += Resource->Header.Length; mStmResourceSizeUsed += Resource->Header.Length;
mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed; mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed;
return ; return;
} }
/** /**
@@ -670,12 +680,14 @@ AddResource (
for (Index = 0; Index < Count; Index++) { for (Index = 0; Index < Count; Index++) {
if (Resource->Header.RscType == END_OF_RESOURCES) { if (Resource->Header.RscType == END_OF_RESOURCES) {
return ; return;
} }
AddSingleResource (Resource); AddSingleResource (Resource);
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length); Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
} }
return ;
return;
} }
/** /**
@@ -726,6 +738,7 @@ ValidateResource (
if (Resource->Header.Length != sizeof (STM_RSC_END)) { if (Resource->Header.Length != sizeof (STM_RSC_END)) {
return FALSE; return FALSE;
} }
// //
// If we are passed actual number of resources to add, // If we are passed actual number of resources to add,
// END_OF_RESOURCES structure between them is considered an // END_OF_RESOURCES structure between them is considered an
@@ -739,6 +752,7 @@ ValidateResource (
// //
return TRUE; return TRUE;
} }
break; break;
case MEM_RANGE: case MEM_RANGE:
@@ -750,6 +764,7 @@ ValidateResource (
if (Resource->Mem.RWXAttributes > FULL_ACCS) { if (Resource->Mem.RWXAttributes > FULL_ACCS) {
return FALSE; return FALSE;
} }
break; break;
case IO_RANGE: case IO_RANGE:
@@ -761,35 +776,42 @@ ValidateResource (
if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) { if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) {
return FALSE; return FALSE;
} }
break; break;
case PCI_CFG_RANGE: case PCI_CFG_RANGE:
DEBUG ((DEBUG_INFO, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction)); DEBUG ((DEBUG_INFO, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction));
if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) { if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof (STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {
return FALSE; return FALSE;
} }
for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) { for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) {
if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) { if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) {
return FALSE; return FALSE;
} }
} }
if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) { if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) {
return FALSE; return FALSE;
} }
break; break;
case MACHINE_SPECIFIC_REG: case MACHINE_SPECIFIC_REG:
if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) { if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) {
return FALSE; return FALSE;
} }
break; break;
default : default:
DEBUG ((DEBUG_ERROR, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType)); DEBUG ((DEBUG_ERROR, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType));
return FALSE; return FALSE;
} }
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length); Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
} }
return TRUE; return TRUE;
} }
@@ -837,6 +859,7 @@ GetResourceSize (
if (Resource->Header.RscType == END_OF_RESOURCES) { if (Resource->Header.RscType == END_OF_RESOURCES) {
break; break;
} }
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length); Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
} }
@@ -884,7 +907,7 @@ AddPiResource (
// //
// First time allocation // First time allocation
// //
NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof(mRscEndNode))); NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof (mRscEndNode)));
DEBUG ((DEBUG_INFO, "Allocate - 0x%08x\n", NewResourceSize)); DEBUG ((DEBUG_INFO, "Allocate - 0x%08x\n", NewResourceSize));
Status = gSmst->SmmAllocatePages ( Status = gSmst->SmmAllocatePages (
AllocateAnyPages, AllocateAnyPages,
@@ -901,9 +924,9 @@ AddPiResource (
// //
mStmResourcesPtr = (UINT8 *)(UINTN)NewResource; mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;
mStmResourceTotalSize = NewResourceSize; mStmResourceTotalSize = NewResourceSize;
CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof (mRscEndNode));
mStmResourceSizeUsed = sizeof(mRscEndNode); mStmResourceSizeUsed = sizeof (mRscEndNode);
mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof (mRscEndNode);
// //
// Let SmmCore change resource ptr // Let SmmCore change resource ptr
@@ -925,6 +948,7 @@ AddPiResource (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
CopyMem ((VOID *)(UINTN)NewResource, mStmResourcesPtr, mStmResourceSizeUsed); CopyMem ((VOID *)(UINTN)NewResource, mStmResourcesPtr, mStmResourceSizeUsed);
mStmResourceSizeAvailable = NewResourceSize - mStmResourceSizeUsed; mStmResourceSizeAvailable = NewResourceSize - mStmResourceSizeUsed;
@@ -975,12 +999,13 @@ DeletePiResource (
ASSERT (FALSE); ASSERT (FALSE);
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
// //
// Delete all // Delete all
// //
CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode)); CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof (mRscEndNode));
mStmResourceSizeUsed = sizeof(mRscEndNode); mStmResourceSizeUsed = sizeof (mRscEndNode);
mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode); mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof (mRscEndNode);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -1101,8 +1126,8 @@ StmCheckStmImage (
// //
// We will create page table, just in case that SINIT does not create it. // We will create page table, just in case that SINIT does not create it.
// //
if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6)) { if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE (6)) {
MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6); MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE (6);
} }
} }
@@ -1201,7 +1226,7 @@ LoadMonitor (
} }
// Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence. // Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence.
TpmMeasureAndLogData( TpmMeasureAndLogData (
0, // PcrIndex 0, // PcrIndex
TXT_EVTYPE_STM_HASH, // EventType TXT_EVTYPE_STM_HASH, // EventType
NULL, // EventLog NULL, // EventLog
@@ -1226,7 +1251,7 @@ LoadMonitor (
**/ **/
VOID * VOID *
GetStmResource( GetStmResource (
VOID VOID
) )
{ {
@@ -1251,9 +1276,9 @@ NotifyStmResourceChange (
Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);
Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource; Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
} }
return ;
}
return;
}
/** /**
This is STM setup BIOS callback. This is STM setup BIOS callback.
@@ -1278,4 +1303,3 @@ SmmStmTeardown (
{ {
mStmState &= ~EFI_SM_MONITOR_STATE_ACTIVATED; mStmState &= ~EFI_SM_MONITOR_STATE_ACTIVATED;
} }

1
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
View File

@@ -45,7 +45,6 @@ SmmStmExceptionHandler (
IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
); );
/** /**
Get STM state. Get STM state.

4
UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
View File

@@ -37,11 +37,11 @@ StmGen4GPageTable (
UINT64 *Pte; UINT64 *Pte;
UINT64 *Pml4; UINT64 *Pml4;
Pml4 = (UINT64*)(UINTN)PageTableBase; Pml4 = (UINT64 *)(UINTN)PageTableBase;
PageTableBase += SIZE_4KB; PageTableBase += SIZE_4KB;
*Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P; *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;
Pde = (UINT64*)(UINTN)PageTableBase; Pde = (UINT64 *)(UINTN)PageTableBase;
PageTableBase += SIZE_4KB; PageTableBase += SIZE_4KB;
Pte = (UINT64 *)(UINTN)PageTableBase; Pte = (UINT64 *)(UINTN)PageTableBase;

12
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c
View File

@@ -167,7 +167,7 @@ SetCommunicationContext (
); );
ASSERT (Hob.Raw); ASSERT (Hob.Raw);
CopyMem ((VOID *)Hob.Raw, SmmCommunicationContext, sizeof(*SmmCommunicationContext)); CopyMem ((VOID *)Hob.Raw, SmmCommunicationContext, sizeof (*SmmCommunicationContext));
} }
/** /**
@@ -192,7 +192,7 @@ InternalSmstGetVendorTableByGuid (
EFI_SMM_SYSTEM_TABLE2_64 *Smst64; EFI_SMM_SYSTEM_TABLE2_64 *Smst64;
EFI_CONFIGURATION_TABLE64 *SmmConfigurationTable64; EFI_CONFIGURATION_TABLE64 *SmmConfigurationTable64;
if ((sizeof(UINTN) == sizeof(UINT32)) && (Signature == SMM_S3_RESUME_SMM_64)) { if ((sizeof (UINTN) == sizeof (UINT32)) && (Signature == SMM_S3_RESUME_SMM_64)) {
// //
// 32 PEI + 64 DXE // 32 PEI + 64 DXE
// //
@@ -206,6 +206,7 @@ InternalSmstGetVendorTableByGuid (
return (VOID *)(UINTN)SmmConfigurationTable64[Index].VendorTable; return (VOID *)(UINTN)SmmConfigurationTable64[Index].VendorTable;
} }
} }
return NULL; return NULL;
} else { } else {
DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmConfigurationTable: %x\n", Smst->SmmConfigurationTable)); DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmConfigurationTable: %x\n", Smst->SmmConfigurationTable));
@@ -217,6 +218,7 @@ InternalSmstGetVendorTableByGuid (
return (VOID *)SmmConfigurationTable[Index].VendorTable; return (VOID *)SmmConfigurationTable[Index].VendorTable;
} }
} }
return NULL; return NULL;
} }
} }
@@ -236,7 +238,7 @@ InitCommunicationContext (
GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid); GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);
ASSERT (GuidHob != NULL); ASSERT (GuidHob != NULL);
SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob); SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);
SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart; SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;
DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmS3ResumeState: %x\n", SmmS3ResumeState)); DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmS3ResumeState: %x\n", SmmS3ResumeState));
@@ -251,7 +253,7 @@ InitCommunicationContext (
SetCommunicationContext (SmmCommunicationContext); SetCommunicationContext (SmmCommunicationContext);
return ; return;
} }
/** /**
@@ -333,7 +335,7 @@ Communicate (
// Send command // Send command
// //
SmiCommand = (UINT8)SmmCommunicationContext->SwSmiNumber; SmiCommand = (UINT8)SmmCommunicationContext->SwSmiNumber;
Size = sizeof(SmiCommand); Size = sizeof (SmiCommand);
Status = SmmControl->Trigger ( Status = SmmControl->Trigger (
(EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (),
SmmControl, SmmControl,

10
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c
View File

@@ -39,7 +39,7 @@ SetCommunicationContext (
gSmst, gSmst,
&gEfiPeiSmmCommunicationPpiGuid, &gEfiPeiSmmCommunicationPpiGuid,
&mSmmCommunicationContext, &mSmmCommunicationContext,
sizeof(mSmmCommunicationContext) sizeof (mSmmCommunicationContext)
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -122,7 +122,7 @@ Done:
@return Allocated address for output. @return Allocated address for output.
**/ **/
VOID* VOID *
AllocateAcpiNvsMemoryBelow4G ( AllocateAcpiNvsMemoryBelow4G (
IN UINTN Size IN UINTN Size
) )
@@ -130,7 +130,7 @@ AllocateAcpiNvsMemoryBelow4G (
UINTN Pages; UINTN Pages;
EFI_PHYSICAL_ADDRESS Address; EFI_PHYSICAL_ADDRESS Address;
EFI_STATUS Status; EFI_STATUS Status;
VOID* Buffer; VOID *Buffer;
Pages = EFI_SIZE_TO_PAGES (Size); Pages = EFI_SIZE_TO_PAGES (Size);
Address = 0xffffffff; Address = 0xffffffff;
@@ -143,7 +143,7 @@ AllocateAcpiNvsMemoryBelow4G (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
Buffer = (VOID *) (UINTN) Address; Buffer = (VOID *)(UINTN)Address;
ZeroMem (Buffer, Size); ZeroMem (Buffer, Size);
return Buffer; return Buffer;
@@ -192,7 +192,7 @@ PiSmmCommunicationSmmEntryPoint (
DEBUG ((DEBUG_INFO, "SmmCommunication SwSmi: %x\n", (UINTN)SmmSwDispatchContext.SwSmiInputValue)); DEBUG ((DEBUG_INFO, "SmmCommunication SwSmi: %x\n", (UINTN)SmmSwDispatchContext.SwSmiInputValue));
BufferPtrAddress = AllocateAcpiNvsMemoryBelow4G (sizeof(EFI_PHYSICAL_ADDRESS)); BufferPtrAddress = AllocateAcpiNvsMemoryBelow4G (sizeof (EFI_PHYSICAL_ADDRESS));
ASSERT (BufferPtrAddress != NULL); ASSERT (BufferPtrAddress != NULL);
DEBUG ((DEBUG_INFO, "SmmCommunication BufferPtrAddress: 0x%016lx, BufferPtr: 0x%016lx\n", (EFI_PHYSICAL_ADDRESS)(UINTN)BufferPtrAddress, *BufferPtrAddress)); DEBUG ((DEBUG_INFO, "SmmCommunication BufferPtrAddress: 0x%016lx, BufferPtr: 0x%016lx\n", (EFI_PHYSICAL_ADDRESS)(UINTN)BufferPtrAddress, *BufferPtrAddress));

96
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
View File

@@ -87,7 +87,7 @@ UINT8 mApHltLoopCodeTemplate[] = {
0xFA, // cli 0xFA, // cli
0xF4, // hlt 0xF4, // hlt
0xEB, 0xFC // jmp $-2 0xEB, 0xFC // jmp $-2
}; };
/** /**
Sync up the MTRR values for all processors. Sync up the MTRR values for all processors.
@@ -99,6 +99,7 @@ EFIAPI
LoadMtrrData ( LoadMtrrData (
EFI_PHYSICAL_ADDRESS MtrrTable EFI_PHYSICAL_ADDRESS MtrrTable
) )
/*++ /*++
Routine Description: Routine Description:
@@ -114,7 +115,7 @@ Returns:
{ {
MTRR_SETTINGS *MtrrSettings; MTRR_SETTINGS *MtrrSettings;
MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable; MtrrSettings = (MTRR_SETTINGS *)(UINTN)MtrrTable;
MtrrSetAllMtrrs (MtrrSettings); MtrrSetAllMtrrs (MtrrSettings);
} }
@@ -182,6 +183,7 @@ ReadWriteCr (
} else { } else {
AsmWriteCr0 (*CrValue); AsmWriteCr0 (*CrValue);
} }
break; break;
case 2: case 2:
if (Read) { if (Read) {
@@ -189,6 +191,7 @@ ReadWriteCr (
} else { } else {
AsmWriteCr2 (*CrValue); AsmWriteCr2 (*CrValue);
} }
break; break;
case 3: case 3:
if (Read) { if (Read) {
@@ -196,6 +199,7 @@ ReadWriteCr (
} else { } else {
AsmWriteCr3 (*CrValue); AsmWriteCr3 (*CrValue);
} }
break; break;
case 4: case 4:
if (Read) { if (Read) {
@@ -203,9 +207,10 @@ ReadWriteCr (
} else { } else {
AsmWriteCr4 (*CrValue); AsmWriteCr4 (*CrValue);
} }
break; break;
default: default:
return EFI_UNSUPPORTED;; return EFI_UNSUPPORTED;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
@@ -246,10 +251,9 @@ ProgramProcessorRegister (
// //
// Traverse Register Table of this logical processor // Traverse Register Table of this logical processor
// //
RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
for (Index = 0; Index < RegisterTable->TableLength; Index++) { for (Index = 0; Index < RegisterTable->TableLength; Index++) {
RegisterTableEntry = &RegisterTableEntryHead[Index]; RegisterTableEntry = &RegisterTableEntryHead[Index];
// //
@@ -264,6 +268,7 @@ ProgramProcessorRegister (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
break; break;
} }
if (RegisterTableEntry->TestThenWrite) { if (RegisterTableEntry->TestThenWrite) {
CurrentValue = BitFieldRead64 ( CurrentValue = BitFieldRead64 (
Value, Value,
@@ -274,7 +279,8 @@ ProgramProcessorRegister (
break; break;
} }
} }
Value = (UINTN) BitFieldWrite64 (
Value = (UINTN)BitFieldWrite64 (
Value, Value,
RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
@@ -327,6 +333,7 @@ ProgramProcessorRegister (
RegisterTableEntry->Value RegisterTableEntry->Value
); );
} }
break; break;
// //
// MemoryMapped operations // MemoryMapped operations
@@ -353,6 +360,7 @@ ProgramProcessorRegister (
} else { } else {
AsmEnableCache (); AsmEnableCache ();
} }
break; break;
case Semaphore: case Semaphore:
@@ -404,15 +412,17 @@ ProgramProcessorRegister (
// //
// First Notify ALL THREADs in current Core that this thread is ready. // First Notify ALL THREADs in current Core that this thread is ready.
// //
for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) { for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {
S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
} }
// //
// Second, check whether all VALID THREADs (not all threads) in current core are ready. // Second, check whether all VALID THREADs (not all threads) in current core are ready.
// //
for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex ++) { for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {
S3WaitForSemaphore (&SemaphorePtr[CurrentThread]); S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
} }
break; break;
case PackageDepType: case PackageDepType:
@@ -442,20 +452,23 @@ ProgramProcessorRegister (
// //
// First Notify ALL THREADS in current package that this thread is ready. // First Notify ALL THREADS in current package that this thread is ready.
// //
for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex ++) { for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {
S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]); S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
} }
// //
// Second, check whether VALID THREADS (not all threads) in current package are ready. // Second, check whether VALID THREADS (not all threads) in current package are ready.
// //
for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex ++) { for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {
S3WaitForSemaphore (&SemaphorePtr[CurrentThread]); S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
} }
break; break;
default: default:
break; break;
} }
break; break;
default: default:
@@ -490,6 +503,7 @@ SetRegister (
} else { } else {
RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->RegisterTable; RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->RegisterTable;
} }
if (RegisterTables == NULL) { if (RegisterTables == NULL) {
return; return;
} }
@@ -504,6 +518,7 @@ SetRegister (
break; break;
} }
} }
ASSERT (RegisterTable != NULL); ASSERT (RegisterTable != NULL);
if (FeatureInitData->ApLocation != 0) { if (FeatureInitData->ApLocation != 0) {
@@ -558,9 +573,9 @@ InitializeAp (
// //
// Place AP into the safe code, count down the number with lock mechanism in the safe code. // Place AP into the safe code, count down the number with lock mechanism in the safe code.
// //
TopOfStack = (UINTN) Stack + sizeof (Stack); TopOfStack = (UINTN)Stack + sizeof (Stack);
TopOfStack &= ~(UINTN) (CPU_STACK_ALIGNMENT - 1); TopOfStack &= ~(UINTN)(CPU_STACK_ALIGNMENT - 1);
CopyMem ((VOID *) (UINTN) mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate)); CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));
TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish); TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);
} }
@@ -592,25 +607,25 @@ PrepareApStartupVector (
// Copy AP startup code to startup vector, and then redirect the long jump // Copy AP startup code to startup vector, and then redirect the long jump
// instructions for mode switching. // instructions for mode switching.
// //
CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size); CopyMem ((VOID *)(UINTN)StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
*(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset); *(UINT32 *)(UINTN)(StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32)(StartupVector + AddressMap.PModeEntryOffset);
if (AddressMap.LongJumpOffset != 0) { if (AddressMap.LongJumpOffset != 0) {
*(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset); *(UINT32 *)(UINTN)(StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32)(StartupVector + AddressMap.LModeEntryOffset);
} }
// //
// Get the start address of exchange data between BSP and AP. // Get the start address of exchange data between BSP and AP.
// //
mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size); mExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)(StartupVector + AddressMap.Size);
ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO)); ZeroMem ((VOID *)mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR)); CopyMem ((VOID *)(UINTN)&mExchangeInfo->GdtrProfile, (VOID *)(UINTN)mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR)); CopyMem ((VOID *)(UINTN)&mExchangeInfo->IdtrProfile, (VOID *)(UINTN)mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress; mExchangeInfo->StackStart = (VOID *)(UINTN)mAcpiCpuData.StackAddress;
mExchangeInfo->StackSize = mAcpiCpuData.StackSize; mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
mExchangeInfo->BufferStart = (UINT32) StartupVector; mExchangeInfo->BufferStart = (UINT32)StartupVector;
mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ()); mExchangeInfo->Cr3 = (UINT32)(AsmReadCr3 ());
mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits; mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
} }
@@ -639,8 +654,9 @@ InitializeCpuBeforeRebase (
} else { } else {
ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus); ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
} }
mNumberToFinish = (UINT32)(mNumberOfCpus - 1); mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
mExchangeInfo->ApFunction = (VOID *) (UINTN) InitializeAp; mExchangeInfo->ApFunction = (VOID *)(UINTN)InitializeAp;
// //
// Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots. // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.
@@ -674,6 +690,7 @@ InitializeCpuAfterRebase (
} else { } else {
ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus); ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
} }
mNumberToFinish = (UINT32)(mNumberOfCpus - 1); mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
// //
@@ -770,15 +787,15 @@ SmmRestoreCpu (
// //
// Save the IA32 IDT Descriptor // Save the IA32 IDT Descriptor
// //
AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr); AsmReadIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);
// //
// Setup X64 IDT table // Setup X64 IDT table
// //
ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32); ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);
X64Idtr.Base = (UINTN) IdtEntryTable; X64Idtr.Base = (UINTN)IdtEntryTable;
X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1); X64Idtr.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);
AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr); AsmWriteIdtr ((IA32_DESCRIPTOR *)&X64Idtr);
// //
// Setup the default exception handler // Setup the default exception handler
@@ -822,11 +839,11 @@ SmmRestoreCpu (
// //
mRestoreSmmConfigurationInS3 = TRUE; mRestoreSmmConfigurationInS3 = TRUE;
DEBUG (( DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs)); DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs));
DEBUG (( DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint)); DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint));
DEBUG (( DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1)); DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1));
DEBUG (( DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2)); DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2));
DEBUG (( DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer)); DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer));
// //
// If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase
@@ -854,7 +871,7 @@ SmmRestoreCpu (
// //
// Restore IA32 IDT table // Restore IA32 IDT table
// //
AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr); AsmWriteIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);
AsmDisablePaging64 ( AsmDisablePaging64 (
SmmS3ResumeState->ReturnCs, SmmS3ResumeState->ReturnCs,
(UINT32)SmmS3ResumeState->ReturnEntryPoint, (UINT32)SmmS3ResumeState->ReturnEntryPoint,
@@ -902,7 +919,7 @@ InitSmmS3ResumeState (
)); ));
CpuDeadLoop (); CpuDeadLoop ();
} else { } else {
SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob); SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);
DEBUG ((DEBUG_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor)); DEBUG ((DEBUG_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));
DEBUG ((DEBUG_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart)); DEBUG ((DEBUG_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));
@@ -928,6 +945,7 @@ InitSmmS3ResumeState (
if (sizeof (UINTN) == sizeof (UINT64)) { if (sizeof (UINTN) == sizeof (UINT64)) {
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64; SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
} }
if (sizeof (UINTN) == sizeof (UINT32)) { if (sizeof (UINTN) == sizeof (UINT32)) {
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32; SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
} }
@@ -950,7 +968,7 @@ InitSmmS3ResumeState (
&Address &Address
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
mApHltLoopCode = (UINT8 *) (UINTN) Address; mApHltLoopCode = (UINT8 *)(UINTN)Address;
} }
/** /**
@@ -1140,8 +1158,8 @@ GetAcpiCpuData (
GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize); GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);
ASSERT (GdtForAp != NULL); ASSERT (GdtForAp != NULL);
IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1)); IdtForAp = (VOID *)((UINTN)GdtForAp + (Gdtr->Limit + 1));
MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1)); MachineCheckHandlerForAp = (VOID *)((UINTN)IdtForAp + (Idtr->Limit + 1));
CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1); CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);
CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1); CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);
@@ -1175,7 +1193,7 @@ GetAcpiCpuData (
); );
ASSERT (mCpuFlags.PackageSemaphoreCount != NULL); ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);
InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock); InitializeSpinLock ((SPIN_LOCK *)&mCpuFlags.MemoryMappedLock);
} }
} }

21
UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
View File

@@ -46,7 +46,7 @@ SmmGetProcessorInfo (
// //
// Check parameter // Check parameter
// //
if (ProcessorNumber >= mMaxNumberOfCpus || ProcessorInfoBuffer == NULL) { if ((ProcessorNumber >= mMaxNumberOfCpus) || (ProcessorInfoBuffer == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -90,8 +90,9 @@ SmmSwitchBsp (
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
if (gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone || if ((gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone) ||
gSmst->CurrentlyExecutingCpu == ProcessorNumber) { (gSmst->CurrentlyExecutingCpu == ProcessorNumber))
{
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@@ -132,7 +133,7 @@ SmmAddProcessor (
// //
// Check parameter // Check parameter
// //
if (ProcessorNumber == NULL || ProcessorId == INVALID_APIC_ID) { if ((ProcessorNumber == NULL) || (ProcessorId == INVALID_APIC_ID)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -151,8 +152,9 @@ SmmAddProcessor (
// of the APIC ID to SMBASE. // of the APIC ID to SMBASE.
// //
for (Index = 0; Index < mMaxNumberOfCpus; Index++) { for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (mCpuHotPlugData.ApicId[Index] == ProcessorId && if ((mCpuHotPlugData.ApicId[Index] == ProcessorId) &&
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) { (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID))
{
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId; gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0; gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
GetProcessorLocationByApicId ( GetProcessorLocationByApicId (
@@ -197,8 +199,9 @@ SmmRemoveProcessor (
// //
// Check parameter // Check parameter
// //
if (ProcessorNumber >= mMaxNumberOfCpus || if ((ProcessorNumber >= mMaxNumberOfCpus) ||
gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID) { (gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -259,6 +262,7 @@ SmmWhoAmI (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
// //
// This should not happen // This should not happen
// //
@@ -363,4 +367,3 @@ InitializeSmmCpuServices (
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return Status; return Status;
} }

46
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
View File

@@ -72,13 +72,14 @@ SmmInitPageTable (
if (FeaturePcdGet (PcdCpuSmmProfileEnable) || if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||
HEAP_GUARD_NONSTOP_MODE || HEAP_GUARD_NONSTOP_MODE ||
NULL_DETECTION_NONSTOP_MODE) { NULL_DETECTION_NONSTOP_MODE)
{
// //
// Set own Page Fault entry instead of the default one, because SMM Profile // Set own Page Fault entry instead of the default one, because SMM Profile
// feature depends on IRET instruction to do Single Step // feature depends on IRET instruction to do Single Step
// //
PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile; PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base; IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
IdtEntry += EXCEPT_IA32_PAGE_FAULT; IdtEntry += EXCEPT_IA32_PAGE_FAULT;
IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress; IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
IdtEntry->Bits.Reserved_0 = 0; IdtEntry->Bits.Reserved_0 = 0;
@@ -98,6 +99,7 @@ SmmInitPageTable (
if (FeaturePcdGet (PcdCpuSmmStackGuard)) { if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
InitializeIDTSmmStackGuard (); InitializeIDTSmmStackGuard ();
} }
return Gen4GPageTable (TRUE); return Gen4GPageTable (TRUE);
} }
@@ -143,13 +145,15 @@ SmiPFHandler (
// or SMM page protection violation. // or SMM page protection violation.
// //
if ((PFAddress >= mCpuHotPlugData.SmrrBase) && if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) { (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))
{
DumpCpuContext (InterruptType, SystemContext); DumpCpuContext (InterruptType, SystemContext);
CpuIndex = GetCpuIndex (); CpuIndex = GetCpuIndex ();
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize); GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize);
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) && if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(PFAddress >= GuardPageAddress) && (PFAddress >= GuardPageAddress) &&
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) { (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))
{
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n")); DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else { } else {
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) { if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
@@ -169,6 +173,7 @@ SmiPFHandler (
goto Exit; goto Exit;
} }
} }
CpuDeadLoop (); CpuDeadLoop ();
goto Exit; goto Exit;
} }
@@ -177,7 +182,8 @@ SmiPFHandler (
// If a page fault occurs in non-SMRAM range. // If a page fault occurs in non-SMRAM range.
// //
if ((PFAddress < mCpuHotPlugData.SmrrBase) || if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) { (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))
{
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) { if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
DumpCpuContext (InterruptType, SystemContext); DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress)); DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));
@@ -191,8 +197,9 @@ SmiPFHandler (
// //
// If NULL pointer was just accessed // If NULL pointer was just accessed
// //
if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 && if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&
(PFAddress < EFI_PAGE_SIZE)) { (PFAddress < EFI_PAGE_SIZE))
{
DumpCpuContext (InterruptType, SystemContext); DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n")); DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));
DEBUG_CODE ( DEBUG_CODE (
@@ -259,7 +266,7 @@ SetPageTableAttributes (
// //
if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) { if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) {
DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n")); DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n"));
return ; return;
} }
// //
@@ -267,7 +274,7 @@ SetPageTableAttributes (
// //
if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n")); DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n"));
return ; return;
} }
DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n")); DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
@@ -276,14 +283,15 @@ SetPageTableAttributes (
// Disable write protection, because we need mark page table to be write protected. // Disable write protection, because we need mark page table to be write protected.
// We need *write* page table memory, to mark itself to be *read only*. // We need *write* page table memory, to mark itself to be *read only*.
// //
CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
if (CetEnabled) { if (CetEnabled) {
// //
// CET must be disabled if WP is disabled. // CET must be disabled if WP is disabled.
// //
DisableCet(); DisableCet ();
} }
AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
do { do {
DEBUG ((DEBUG_INFO, "Start...\n")); DEBUG ((DEBUG_INFO, "Start...\n"));
@@ -304,15 +312,17 @@ SetPageTableAttributes (
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted);
for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) { for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) { if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M // 2M
continue; continue;
} }
L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L1PageTable == NULL) { if (L1PageTable == NULL) {
continue; continue;
} }
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted);
} }
@@ -322,15 +332,15 @@ SetPageTableAttributes (
// //
// Enable write protection, after page table updated. // Enable write protection, after page table updated.
// //
AsmWriteCr0 (AsmReadCr0() | CR0_WP); AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
if (CetEnabled) { if (CetEnabled) {
// //
// re-enable CET. // re-enable CET.
// //
EnableCet(); EnableCet ();
} }
return ; return;
} }
/** /**
@@ -343,7 +353,7 @@ SaveCr2 (
OUT UINTN *Cr2 OUT UINTN *Cr2
) )
{ {
return ; return;
} }
/** /**
@@ -356,7 +366,7 @@ RestoreCr2 (
IN UINTN Cr2 IN UINTN Cr2
) )
{ {
return ; return;
} }
/** /**

16
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c
View File

@@ -85,13 +85,13 @@ InitGdt (
// write GDT and TSS, so AllocateCodePages() could not be used here // write GDT and TSS, so AllocateCodePages() could not be used here
// as code pages will be set to RO. // as code pages will be set to RO.
// //
GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); GdtTssTables = (UINT8 *)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL); ASSERT (GdtTssTables != NULL);
mGdtBuffer = (UINTN)GdtTssTables; mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize; GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) { for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE); CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE);
// //
// Fixup TSS descriptors // Fixup TSS descriptors
// //
@@ -118,7 +118,7 @@ InitGdt (
// Setup ShadowStack for stack switch // Setup ShadowStack for stack switch
// //
if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) { if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {
InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof(UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index); InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index);
*(UINT32 *)(TssBase + TSS_IA32_SSP_OFFSET) = (UINT32)InterruptShadowStack; *(UINT32 *)(TssBase + TSS_IA32_SSP_OFFSET) = (UINT32)InterruptShadowStack;
} }
} }
@@ -128,13 +128,13 @@ InitGdt (
// //
GdtTssTableSize = gcSmiGdtr.Limit + 1; GdtTssTableSize = gcSmiGdtr.Limit + 1;
mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); GdtTssTables = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL); ASSERT (GdtTssTables != NULL);
mGdtBuffer = (UINTN)GdtTssTables; mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize; GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) { for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1); CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);
} }
} }
@@ -188,17 +188,17 @@ InitShadowStack (
if (FeaturePcdGet (PcdCpuSmmStackGuard)) { if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
SmmShadowStackSize += EFI_PAGES_TO_SIZE (2); SmmShadowStackSize += EFI_PAGES_TO_SIZE (2);
} }
mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));
mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));
PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4); PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp)); DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack)); DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));
DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize)); DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));
if (FeaturePcdGet (PcdCpuSmmStackGuard)) { if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64)); mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64));
PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4); PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);
DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp)); DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));
} }
} }
} }

2
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
View File

@@ -20,7 +20,7 @@ InitSmmS3Cr3 (
{ {
mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (TRUE); mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (TRUE);
return ; return;
} }
/** /**

187
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
View File

@@ -43,22 +43,24 @@ WaitForSemaphore (
{ {
UINT32 Value; UINT32 Value;
for (;;) { for ( ; ;) {
Value = *Sem; Value = *Sem;
if (Value != 0 && if ((Value != 0) &&
InterlockedCompareExchange32 ( (InterlockedCompareExchange32 (
(UINT32*)Sem, (UINT32 *)Sem,
Value, Value,
Value - 1 Value - 1
) == Value) { ) == Value))
{
break; break;
} }
CpuPause (); CpuPause ();
} }
return Value - 1; return Value - 1;
} }
/** /**
Performs an atomic compare exchange operation to release semaphore. Performs an atomic compare exchange operation to release semaphore.
The compare exchange operation must be performed using The compare exchange operation must be performed using
@@ -80,10 +82,11 @@ ReleaseSemaphore (
Value = *Sem; Value = *Sem;
} while (Value + 1 != 0 && } while (Value + 1 != 0 &&
InterlockedCompareExchange32 ( InterlockedCompareExchange32 (
(UINT32*)Sem, (UINT32 *)Sem,
Value, Value,
Value + 1 Value + 1
) != Value); ) != Value);
return Value + 1; return Value + 1;
} }
@@ -107,9 +110,11 @@ LockdownSemaphore (
do { do {
Value = *Sem; Value = *Sem;
} while (InterlockedCompareExchange32 ( } while (InterlockedCompareExchange32 (
(UINT32*)Sem, (UINT32 *)Sem,
Value, (UINT32)-1 Value,
(UINT32)-1
) != Value); ) != Value);
return Value; return Value;
} }
@@ -178,21 +183,23 @@ AllCpusInSmmWithExceptions (
CpuData = mSmmMpSyncData->CpuData; CpuData = mSmmMpSyncData->CpuData;
ProcessorInfo = gSmmCpuPrivate->ProcessorInfo; ProcessorInfo = gSmmCpuPrivate->ProcessorInfo;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) { for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (!(*(CpuData[Index].Present)) && ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) { if (!(*(CpuData[Index].Present)) && (ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {
if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0) { if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0)) {
continue; continue;
} }
if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0) {
if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0)) {
continue; continue;
} }
if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0) {
if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0)) {
continue; continue;
} }
return FALSE; return FALSE;
} }
} }
return TRUE; return TRUE;
} }
@@ -223,7 +230,7 @@ IsLmceOsEnabled (
} }
McgExtCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL); McgExtCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
return (BOOLEAN) (McgExtCtrl.Bits.LMCE_EN == 1); return (BOOLEAN)(McgExtCtrl.Bits.LMCE_EN == 1);
} }
/** /**
@@ -244,7 +251,7 @@ IsLmceSignaled (
MSR_IA32_MCG_STATUS_REGISTER McgStatus; MSR_IA32_MCG_STATUS_REGISTER McgStatus;
McgStatus.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS); McgStatus.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
return (BOOLEAN) (McgStatus.Bits.LMCE_S == 1); return (BOOLEAN)(McgStatus.Bits.LMCE_S == 1);
} }
/** /**
@@ -268,7 +275,7 @@ SmmWaitForApArrival (
LmceSignal = FALSE; LmceSignal = FALSE;
if (mMachineCheckSupported) { if (mMachineCheckSupported) {
LmceEn = IsLmceOsEnabled (); LmceEn = IsLmceOsEnabled ();
LmceSignal = IsLmceSignaled(); LmceSignal = IsLmceSignaled ();
} }
// //
@@ -287,8 +294,9 @@ SmmWaitForApArrival (
// //
for (Timer = StartSyncTimer (); for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) && !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) &&
!AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED ); !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);
) { )
{
CpuPause (); CpuPause ();
} }
@@ -313,7 +321,7 @@ SmmWaitForApArrival (
// Send SMI IPIs to bring outside processors in // Send SMI IPIs to bring outside processors in
// //
for (Index = 0; Index < mMaxNumberOfCpus; Index++) { for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) { if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {
SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId); SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
} }
} }
@@ -323,8 +331,9 @@ SmmWaitForApArrival (
// //
for (Timer = StartSyncTimer (); for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) && !IsSyncTimerTimeout (Timer) &&
!AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED ); !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);
) { )
{
CpuPause (); CpuPause ();
} }
} }
@@ -332,7 +341,6 @@ SmmWaitForApArrival (
return; return;
} }
/** /**
Replace OS MTRR's with SMI MTRR's. Replace OS MTRR's with SMI MTRR's.
@@ -372,16 +380,16 @@ WaitForAllAPsNotBusy (
// //
// Ignore BSP and APs which not call in SMM. // Ignore BSP and APs which not call in SMM.
// //
if (!IsPresentAp(Index)) { if (!IsPresentAp (Index)) {
continue; continue;
} }
if (BlockMode) { if (BlockMode) {
AcquireSpinLock(mSmmMpSyncData->CpuData[Index].Busy); AcquireSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
ReleaseSpinLock(mSmmMpSyncData->CpuData[Index].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
} else { } else {
if (AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) { if (AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) {
ReleaseSpinLock(mSmmMpSyncData->CpuData[Index].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
} else { } else {
return FALSE; return FALSE;
} }
@@ -488,7 +496,7 @@ BSPHandler (
// we cleared it after SMI handlers are run, we would miss the SMI that // we cleared it after SMI handlers are run, we would miss the SMI that
// occurs after SMI handlers are done and before SMI status bit is cleared. // occurs after SMI handlers are done and before SMI status bit is cleared.
// //
ClearTopLevelSmiResult = ClearTopLevelSmiStatus(); ClearTopLevelSmiResult = ClearTopLevelSmiStatus ();
ASSERT (ClearTopLevelSmiResult == TRUE); ASSERT (ClearTopLevelSmiResult == TRUE);
// //
@@ -499,12 +507,11 @@ BSPHandler (
// //
// If Traditional Sync Mode or need to configure MTRRs: gather all available APs. // If Traditional Sync Mode or need to configure MTRRs: gather all available APs.
// //
if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) { if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {
// //
// Wait for APs to arrive // Wait for APs to arrive
// //
SmmWaitForApArrival(); SmmWaitForApArrival ();
// //
// Lock the counter down and retrieve the number of APs // Lock the counter down and retrieve the number of APs
@@ -517,7 +524,7 @@ BSPHandler (
// //
WaitForAllAPs (ApCount); WaitForAllAPs (ApCount);
if (SmmCpuFeaturesNeedConfigureMtrrs()) { if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
// //
// Signal all APs it's time for backup MTRRs // Signal all APs it's time for backup MTRRs
// //
@@ -531,7 +538,7 @@ BSPHandler (
// We do the backup first and then set MTRR to avoid race condition for threads // We do the backup first and then set MTRR to avoid race condition for threads
// in the same core. // in the same core.
// //
MtrrGetAllMtrrs(&Mtrrs); MtrrGetAllMtrrs (&Mtrrs);
// //
// Wait for all APs to complete their MTRR saving // Wait for all APs to complete their MTRR saving
@@ -587,8 +594,7 @@ BSPHandler (
// make those APs to exit SMI synchronously. APs which arrive later will be excluded and // make those APs to exit SMI synchronously. APs which arrive later will be excluded and
// will run through freely. // will run through freely.
// //
if (SyncMode != SmmCpuSyncModeTradition && !SmmCpuFeaturesNeedConfigureMtrrs()) { if ((SyncMode != SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfigureMtrrs ()) {
// //
// Lock the counter down and retrieve the number of APs // Lock the counter down and retrieve the number of APs
// //
@@ -601,9 +607,10 @@ BSPHandler (
PresentCount = 0; PresentCount = 0;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) { for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (*(mSmmMpSyncData->CpuData[Index].Present)) { if (*(mSmmMpSyncData->CpuData[Index].Present)) {
PresentCount ++; PresentCount++;
} }
} }
if (PresentCount > ApCount) { if (PresentCount > ApCount) {
break; break;
} }
@@ -621,7 +628,7 @@ BSPHandler (
// //
WaitForAllAPs (ApCount); WaitForAllAPs (ApCount);
if (SmmCpuFeaturesNeedConfigureMtrrs()) { if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
// //
// Signal APs to restore MTRRs // Signal APs to restore MTRRs
// //
@@ -631,7 +638,7 @@ BSPHandler (
// Restore OS MTRRs // Restore OS MTRRs
// //
SmmCpuFeaturesReenableSmrr (); SmmCpuFeaturesReenableSmrr ();
MtrrSetAllMtrrs(&Mtrrs); MtrrSetAllMtrrs (&Mtrrs);
// //
// Wait for all APs to complete MTRR programming // Wait for all APs to complete MTRR programming
@@ -711,7 +718,8 @@ APHandler (
for (Timer = StartSyncTimer (); for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) && !IsSyncTimerTimeout (Timer) &&
!(*mSmmMpSyncData->InsideSmm); !(*mSmmMpSyncData->InsideSmm);
) { )
{
CpuPause (); CpuPause ();
} }
@@ -737,7 +745,8 @@ APHandler (
for (Timer = StartSyncTimer (); for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) && !IsSyncTimerTimeout (Timer) &&
!(*mSmmMpSyncData->InsideSmm); !(*mSmmMpSyncData->InsideSmm);
) { )
{
CpuPause (); CpuPause ();
} }
@@ -768,14 +777,14 @@ APHandler (
// //
*(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE; *(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE;
if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) { if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {
// //
// Notify BSP of arrival at this point // Notify BSP of arrival at this point
// //
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
} }
if (SmmCpuFeaturesNeedConfigureMtrrs()) { if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
// //
// Wait for the signal from BSP to backup MTRRs // Wait for the signal from BSP to backup MTRRs
// //
@@ -784,7 +793,7 @@ APHandler (
// //
// Backup OS MTRRs // Backup OS MTRRs
// //
MtrrGetAllMtrrs(&Mtrrs); MtrrGetAllMtrrs (&Mtrrs);
// //
// Signal BSP the completion of this AP // Signal BSP the completion of this AP
@@ -830,8 +839,8 @@ APHandler (
// //
// Invoke the scheduled procedure // Invoke the scheduled procedure
// //
ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure) ( ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure)(
(VOID*)mSmmMpSyncData->CpuData[CpuIndex].Parameter (VOID *)mSmmMpSyncData->CpuData[CpuIndex].Parameter
); );
if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) { if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) {
*mSmmMpSyncData->CpuData[CpuIndex].Status = ProcedureStatus; *mSmmMpSyncData->CpuData[CpuIndex].Status = ProcedureStatus;
@@ -847,7 +856,7 @@ APHandler (
ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);
} }
if (SmmCpuFeaturesNeedConfigureMtrrs()) { if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
// //
// Notify BSP the readiness of this AP to program MTRRs // Notify BSP the readiness of this AP to program MTRRs
// //
@@ -862,7 +871,7 @@ APHandler (
// Restore OS MTRRs // Restore OS MTRRs
// //
SmmCpuFeaturesReenableSmrr (); SmmCpuFeaturesReenableSmrr ();
MtrrSetAllMtrrs(&Mtrrs); MtrrSetAllMtrrs (&Mtrrs);
} }
// //
@@ -884,7 +893,6 @@ APHandler (
// Notify BSP the readiness of this AP to exit SMM // Notify BSP the readiness of this AP to exit SMM
// //
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run); ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
} }
/** /**
@@ -926,6 +934,7 @@ Gen4GPageTable (
High2MBoundary = (mSmmStackArrayEnd - mSmmStackSize - mSmmShadowStackSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1); High2MBoundary = (mSmmStackArrayEnd - mSmmStackSize - mSmmShadowStackSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1);
PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1; PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1;
} }
// //
// Allocate the page table // Allocate the page table
// //
@@ -933,7 +942,7 @@ Gen4GPageTable (
ASSERT (PageTable != NULL); ASSERT (PageTable != NULL);
PageTable = (VOID *)((UINTN)PageTable); PageTable = (VOID *)((UINTN)PageTable);
Pte = (UINT64*)PageTable; Pte = (UINT64 *)PageTable;
// //
// Zero out all page table entries first // Zero out all page table entries first
@@ -947,6 +956,7 @@ Gen4GPageTable (
Pte[Index] = ((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAddressEncMask | Pte[Index] = ((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAddressEncMask |
(Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS); (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);
} }
Pte += EFI_PAGE_SIZE / sizeof (*Pte); Pte += EFI_PAGE_SIZE / sizeof (*Pte);
// //
@@ -956,17 +966,17 @@ Gen4GPageTable (
Pte[Index] = (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATTRIBUTE_BITS; Pte[Index] = (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;
} }
Pdpte = (UINT64*)PageTable; Pdpte = (UINT64 *)PageTable;
if (FeaturePcdGet (PcdCpuSmmStackGuard)) { if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5); Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);
GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE; GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE;
for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) { for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {
Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); Pte = (UINT64 *)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
// //
// Fill in Page Table Entries // Fill in Page Table Entries
// //
Pte = (UINT64*)Pages; Pte = (UINT64 *)Pages;
PageAddress = PageIndex; PageAddress = PageIndex;
for (Index = 0; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) { for (Index = 0; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {
if (PageAddress == GuardPage) { if (PageAddress == GuardPage) {
@@ -981,17 +991,19 @@ Gen4GPageTable (
} else { } else {
Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS; Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
} }
PageAddress+= EFI_PAGE_SIZE;
PageAddress += EFI_PAGE_SIZE;
} }
Pages += EFI_PAGE_SIZE; Pages += EFI_PAGE_SIZE;
} }
} }
if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) { if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) {
Pte = (UINT64*)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); Pte = (UINT64 *)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
if ((Pte[0] & IA32_PG_PS) == 0) { if ((Pte[0] & IA32_PG_PS) == 0) {
// 4K-page entries are already mapped. Just hide the first one anyway. // 4K-page entries are already mapped. Just hide the first one anyway.
Pte = (UINT64*)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1)); Pte = (UINT64 *)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));
Pte[0] &= ~(UINT64)IA32_PG_P; // Hide page 0 Pte[0] &= ~(UINT64)IA32_PG_P; // Hide page 0
} else { } else {
// Create 4K-page entries // Create 4K-page entries
@@ -1000,7 +1012,7 @@ Gen4GPageTable (
Pte[0] = (UINT64)(Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS); Pte[0] = (UINT64)(Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
Pte = (UINT64*)Pages; Pte = (UINT64 *)Pages;
PageAddress = 0; PageAddress = 0;
Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left
for (Index = 1; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) { for (Index = 1; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {
@@ -1076,6 +1088,7 @@ AllocateTokenBuffer (
DEBUG ((DEBUG_ERROR, "PcdCpuSmmMpTokenCountPerChunk should not be Zero!\n")); DEBUG ((DEBUG_ERROR, "PcdCpuSmmMpTokenCountPerChunk should not be Zero!\n"));
CpuDeadLoop (); CpuDeadLoop ();
} }
DEBUG ((DEBUG_INFO, "CpuSmm: SpinLock Size = 0x%x, PcdCpuSmmMpTokenCountPerChunk = 0x%x\n", SpinLockSize, TokenCountPerChunk)); DEBUG ((DEBUG_INFO, "CpuSmm: SpinLock Size = 0x%x, PcdCpuSmmMpTokenCountPerChunk = 0x%x\n", SpinLockSize, TokenCountPerChunk));
// //
@@ -1125,6 +1138,7 @@ GetFreeToken (
if (gSmmCpuPrivate->FirstFreeToken == &gSmmCpuPrivate->TokenList) { if (gSmmCpuPrivate->FirstFreeToken == &gSmmCpuPrivate->TokenList) {
gSmmCpuPrivate->FirstFreeToken = AllocateTokenBuffer (); gSmmCpuPrivate->FirstFreeToken = AllocateTokenBuffer ();
} }
NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken); NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken);
gSmmCpuPrivate->FirstFreeToken = GetNextNode (&gSmmCpuPrivate->TokenList, gSmmCpuPrivate->FirstFreeToken); gSmmCpuPrivate->FirstFreeToken = GetNextNode (&gSmmCpuPrivate->TokenList, gSmmCpuPrivate->FirstFreeToken);
@@ -1207,31 +1221,39 @@ InternalSmmStartupThisAp (
PROCEDURE_TOKEN *ProcToken; PROCEDURE_TOKEN *ProcToken;
if (CpuIndex >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus) { if (CpuIndex >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus) {
DEBUG((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus)); DEBUG ((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (CpuIndex == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) { if (CpuIndex == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
DEBUG((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex)); DEBUG ((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId == INVALID_APIC_ID) { if (gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId == INVALID_APIC_ID) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) { if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
if (mSmmMpSyncData->EffectiveSyncMode == SmmCpuSyncModeTradition) { if (mSmmMpSyncData->EffectiveSyncMode == SmmCpuSyncModeTradition) {
DEBUG((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex)); DEBUG ((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex));
} }
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (gSmmCpuPrivate->Operation[CpuIndex] == SmmCpuRemove) { if (gSmmCpuPrivate->Operation[CpuIndex] == SmmCpuRemove) {
if (!FeaturePcdGet (PcdCpuHotPlugSupport)) { if (!FeaturePcdGet (PcdCpuHotPlugSupport)) {
DEBUG((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex)); DEBUG ((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex));
} }
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) { if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (Procedure == NULL) { if (Procedure == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -1262,6 +1284,7 @@ InternalSmmStartupThisAp (
*Token = (MM_COMPLETION)ProcToken->SpinLock; *Token = (MM_COMPLETION)ProcToken->SpinLock;
} }
} }
mSmmMpSyncData->CpuData[CpuIndex].Status = CpuStatus; mSmmMpSyncData->CpuData[CpuIndex].Status = CpuStatus;
if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) { if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) {
*mSmmMpSyncData->CpuData[CpuIndex].Status = EFI_NOT_READY; *mSmmMpSyncData->CpuData[CpuIndex].Status = EFI_NOT_READY;
@@ -1323,6 +1346,7 @@ InternalSmmStartupAllAPs (
if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) { if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (Procedure == NULL) { if (Procedure == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -1330,18 +1354,20 @@ InternalSmmStartupAllAPs (
CpuCount = 0; CpuCount = 0;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) { for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (IsPresentAp (Index)) { if (IsPresentAp (Index)) {
CpuCount ++; CpuCount++;
if (gSmmCpuPrivate->Operation[Index] == SmmCpuRemove) { if (gSmmCpuPrivate->Operation[Index] == SmmCpuRemove) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (!AcquireSpinLockOrFail(mSmmMpSyncData->CpuData[Index].Busy)) { if (!AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) {
return EFI_NOT_READY; return EFI_NOT_READY;
} }
ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy); ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
} }
} }
if (CpuCount == 0) { if (CpuCount == 0) {
return EFI_NOT_STARTED; return EFI_NOT_STARTED;
} }
@@ -1368,11 +1394,12 @@ InternalSmmStartupAllAPs (
for (Index = 0; Index < mMaxNumberOfCpus; Index++) { for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (IsPresentAp (Index)) { if (IsPresentAp (Index)) {
mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2) Procedure; mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2)Procedure;
mSmmMpSyncData->CpuData[Index].Parameter = ProcedureArguments; mSmmMpSyncData->CpuData[Index].Parameter = ProcedureArguments;
if (ProcToken != NULL) { if (ProcToken != NULL) {
mSmmMpSyncData->CpuData[Index].Token = ProcToken; mSmmMpSyncData->CpuData[Index].Token = ProcToken;
} }
if (CPUStatus != NULL) { if (CPUStatus != NULL) {
mSmmMpSyncData->CpuData[Index].Status = &CPUStatus[Index]; mSmmMpSyncData->CpuData[Index].Status = &CPUStatus[Index];
if (mSmmMpSyncData->CpuData[Index].Status != NULL) { if (mSmmMpSyncData->CpuData[Index].Status != NULL) {
@@ -1527,7 +1554,7 @@ CpuSmmDebugEntry (
SMRAM_SAVE_STATE_MAP *CpuSaveState; SMRAM_SAVE_STATE_MAP *CpuSaveState;
if (FeaturePcdGet (PcdCpuSmmDebug)) { if (FeaturePcdGet (PcdCpuSmmDebug)) {
ASSERT(CpuIndex < mMaxNumberOfCpus); ASSERT (CpuIndex < mMaxNumberOfCpus);
CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex]; CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
AsmWriteDr6 (CpuSaveState->x86._DR6); AsmWriteDr6 (CpuSaveState->x86._DR6);
@@ -1557,7 +1584,7 @@ CpuSmmDebugExit (
SMRAM_SAVE_STATE_MAP *CpuSaveState; SMRAM_SAVE_STATE_MAP *CpuSaveState;
if (FeaturePcdGet (PcdCpuSmmDebug)) { if (FeaturePcdGet (PcdCpuSmmDebug)) {
ASSERT(CpuIndex < mMaxNumberOfCpus); ASSERT (CpuIndex < mMaxNumberOfCpus);
CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex]; CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) { if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 (); CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();
@@ -1588,7 +1615,7 @@ SmiRendezvous (
UINTN Index; UINTN Index;
UINTN Cr2; UINTN Cr2;
ASSERT(CpuIndex < mMaxNumberOfCpus); ASSERT (CpuIndex < mMaxNumberOfCpus);
// //
// Save Cr2 because Page Fault exception in SMM may override its value, // Save Cr2 because Page Fault exception in SMM may override its value,
@@ -1612,7 +1639,7 @@ SmiRendezvous (
// //
// Determine if this is a valid SMI // Determine if this is a valid SMI
// //
ValidSmi = PlatformValidSmi(); ValidSmi = PlatformValidSmi ();
// //
// Determine if BSP has been already in progress. Note this must be checked after // Determine if BSP has been already in progress. Note this must be checked after
@@ -1644,9 +1671,9 @@ SmiRendezvous (
while (*mSmmMpSyncData->AllCpusInSync) { while (*mSmmMpSyncData->AllCpusInSync) {
CpuPause (); CpuPause ();
} }
goto Exit; goto Exit;
} else { } else {
// //
// The BUSY lock is initialized to Released state. // The BUSY lock is initialized to Released state.
// This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call. // This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call.
@@ -1693,7 +1720,7 @@ SmiRendezvous (
// Platform hook fails to determine, use default BSP election method // Platform hook fails to determine, use default BSP election method
// //
InterlockedCompareExchange32 ( InterlockedCompareExchange32 (
(UINT32*)&mSmmMpSyncData->BspIndex, (UINT32 *)&mSmmMpSyncData->BspIndex,
(UINT32)-1, (UINT32)-1,
(UINT32)CpuIndex (UINT32)CpuIndex
); );
@@ -1705,7 +1732,6 @@ SmiRendezvous (
// "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP // "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP
// //
if (mSmmMpSyncData->BspIndex == CpuIndex) { if (mSmmMpSyncData->BspIndex == CpuIndex) {
// //
// Clear last request for SwitchBsp. // Clear last request for SwitchBsp.
// //
@@ -1788,8 +1814,8 @@ InitializeSmmCpuSemaphores (
GlobalSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_GLOBAL) / sizeof (VOID *)) * SemaphoreSize; GlobalSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_GLOBAL) / sizeof (VOID *)) * SemaphoreSize;
CpuSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_CPU) / sizeof (VOID *)) * ProcessorCount * SemaphoreSize; CpuSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_CPU) / sizeof (VOID *)) * ProcessorCount * SemaphoreSize;
TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize; TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize;
DEBUG((DEBUG_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize)); DEBUG ((DEBUG_INFO, "One Semaphore Size = 0x%x\n", SemaphoreSize));
DEBUG((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize)); DEBUG ((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));
Pages = EFI_SIZE_TO_PAGES (TotalSize); Pages = EFI_SIZE_TO_PAGES (TotalSize);
SemaphoreBlock = AllocatePages (Pages); SemaphoreBlock = AllocatePages (Pages);
ASSERT (SemaphoreBlock != NULL); ASSERT (SemaphoreBlock != NULL);
@@ -1847,18 +1873,21 @@ InitializeMpSyncData (
// //
mSmmMpSyncData->BspIndex = (UINT32)-1; mSmmMpSyncData->BspIndex = (UINT32)-1;
} }
mSmmMpSyncData->EffectiveSyncMode = mCpuSmmSyncMode; mSmmMpSyncData->EffectiveSyncMode = mCpuSmmSyncMode;
mSmmMpSyncData->Counter = mSmmCpuSemaphores.SemaphoreGlobal.Counter; mSmmMpSyncData->Counter = mSmmCpuSemaphores.SemaphoreGlobal.Counter;
mSmmMpSyncData->InsideSmm = mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm; mSmmMpSyncData->InsideSmm = mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm;
mSmmMpSyncData->AllCpusInSync = mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync; mSmmMpSyncData->AllCpusInSync = mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync;
ASSERT (mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL && ASSERT (
mSmmMpSyncData->AllCpusInSync != NULL); mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL &&
mSmmMpSyncData->AllCpusInSync != NULL
);
*mSmmMpSyncData->Counter = 0; *mSmmMpSyncData->Counter = 0;
*mSmmMpSyncData->InsideSmm = FALSE; *mSmmMpSyncData->InsideSmm = FALSE;
*mSmmMpSyncData->AllCpusInSync = FALSE; *mSmmMpSyncData->AllCpusInSync = FALSE;
for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex ++) { for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex++) {
mSmmMpSyncData->CpuData[CpuIndex].Busy = mSmmMpSyncData->CpuData[CpuIndex].Busy =
(SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * CpuIndex); (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * CpuIndex);
mSmmMpSyncData->CpuData[CpuIndex].Run = mSmmMpSyncData->CpuData[CpuIndex].Run =
@@ -1911,7 +1940,7 @@ InitializeMpServiceData (
// //
mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) + mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) +
(sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA*) AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize)); mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA *)AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize));
ASSERT (mSmmMpSyncData != NULL); ASSERT (mSmmMpSyncData != NULL);
mCpuSmmSyncMode = (SMM_CPU_SYNC_MODE)PcdGet8 (PcdCpuSmmSyncMode); mCpuSmmSyncMode = (SMM_CPU_SYNC_MODE)PcdGet8 (PcdCpuSmmSyncMode);
InitializeMpSyncData (); InitializeMpSyncData ();
@@ -1926,6 +1955,7 @@ InitializeMpServiceData (
} else { } else {
VirPhyAddressSize.Bits.PhysicalAddressBits = 36; VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
} }
gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1; gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
// //
// Clear the low 12 bits // Clear the low 12 bits
@@ -1946,7 +1976,7 @@ InitializeMpServiceData (
InstallSmiHandler ( InstallSmiHandler (
Index, Index,
(UINT32)mCpuHotPlugData.SmBase[Index], (UINT32)mCpuHotPlugData.SmBase[Index],
(VOID*)((UINTN)Stacks + (StackSize + ShadowStackSize) * Index), (VOID *)((UINTN)Stacks + (StackSize + ShadowStackSize) * Index),
StackSize, StackSize,
(UINTN)(GdtTssTables + GdtTableStepSize * Index), (UINTN)(GdtTssTables + GdtTableStepSize * Index),
gcSmiGdtr.Limit + 1, gcSmiGdtr.Limit + 1,
@@ -2013,9 +2043,10 @@ RegisterStartupProcedure (
IN OUT VOID *ProcedureArguments OPTIONAL IN OUT VOID *ProcedureArguments OPTIONAL
) )
{ {
if (Procedure == NULL && ProcedureArguments != NULL) { if ((Procedure == NULL) && (ProcedureArguments != NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (mSmmMpSyncData == NULL) { if (mSmmMpSyncData == NULL) {
return EFI_NOT_READY; return EFI_NOT_READY;
} }

94
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
View File

@@ -21,7 +21,9 @@ SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {
NULL, // Pointer to Operation array NULL, // Pointer to Operation array
NULL, // Pointer to CpuSaveStateSize array NULL, // Pointer to CpuSaveStateSize array
NULL, // Pointer to CpuSaveState array NULL, // Pointer to CpuSaveState array
{ {0} }, // SmmReservedSmramRegion {
{ 0 }
}, // SmmReservedSmramRegion
{ {
SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp
0, // SmmCoreEntryContext.CurrentlyExecutingCpu 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
@@ -35,7 +37,7 @@ SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {
RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry RegisterSmmEntry // SmmConfiguration.RegisterSmmEntry
}, },
NULL, // pointer to Ap Wrapper Func array NULL, // pointer to Ap Wrapper Func array
{NULL, NULL}, // List_Entry for Tokens. { NULL, NULL }, // List_Entry for Tokens.
}; };
CPU_HOT_PLUG_DATA mCpuHotPlugData = { CPU_HOT_PLUG_DATA mCpuHotPlugData = {
@@ -147,11 +149,11 @@ InitializeSmmIdt (
// There are 32 (not 255) entries in it since only processor // There are 32 (not 255) entries in it since only processor
// generated exceptions will be handled. // generated exceptions will be handled.
// //
gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1; gcSmiIdtr.Limit = (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;
// //
// Allocate page aligned IDT, because it might be set as read only. // Allocate page aligned IDT, because it might be set as read only.
// //
gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1)); gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES (gcSmiIdtr.Limit + 1));
ASSERT (gcSmiIdtr.Base != 0); ASSERT (gcSmiIdtr.Base != 0);
ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1); ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);
@@ -173,7 +175,7 @@ InitializeSmmIdt (
// //
// Restore DXE IDT table and CPU interrupt // Restore DXE IDT table and CPU interrupt
// //
AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr); AsmWriteIdtr ((IA32_DESCRIPTOR *)&DxeIdtr);
SetInterruptState (InterruptState); SetInterruptState (InterruptState);
} }
@@ -196,8 +198,8 @@ DumpModuleInfoByIp (
// //
Pe32Data = PeCoffSearchImageBase (CallerIpAddress); Pe32Data = PeCoffSearchImageBase (CallerIpAddress);
if (Pe32Data != 0) { if (Pe32Data != 0) {
DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress)); DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *)CallerIpAddress));
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data); PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);
if (PdbPointer != NULL) { if (PdbPointer != NULL) {
DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer)); DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));
} }
@@ -236,6 +238,7 @@ SmmReadSaveState (
if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) { if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
// //
// The SpeculationBarrier() call here is to ensure the above check for the // The SpeculationBarrier() call here is to ensure the above check for the
// CpuIndex has been completed before the execution of subsequent codes. // CpuIndex has been completed before the execution of subsequent codes.
@@ -252,6 +255,7 @@ SmmReadSaveState (
if (Width != sizeof (UINT64)) { if (Width != sizeof (UINT64)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
// //
// If the processor is in SMM at the time the SMI occurred, // If the processor is in SMM at the time the SMI occurred,
// the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer. // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
@@ -273,6 +277,7 @@ SmmReadSaveState (
if (Status == EFI_UNSUPPORTED) { if (Status == EFI_UNSUPPORTED) {
Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer); Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
} }
return Status; return Status;
} }
@@ -324,10 +329,10 @@ SmmWriteSaveState (
if (Status == EFI_UNSUPPORTED) { if (Status == EFI_UNSUPPORTED) {
Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer); Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
} }
return Status; return Status;
} }
/** /**
C function for SMI handler. To change all processor's SMMBase Register. C function for SMI handler. To change all processor's SMMBase Register.
@@ -384,6 +389,7 @@ SmmInitHandler (
return; return;
} }
} }
ASSERT (FALSE); ASSERT (FALSE);
} }
@@ -427,7 +433,7 @@ SmmRelocateBases (
gcSmiInitGdtr.Base = gcSmiGdtr.Base; gcSmiInitGdtr.Base = gcSmiGdtr.Base;
gcSmiInitGdtr.Limit = gcSmiGdtr.Limit; gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;
U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET); U8Ptr = (UINT8 *)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
// //
@@ -459,7 +465,8 @@ SmmRelocateBases (
// //
// Wait for this AP to finish its 1st SMI // Wait for this AP to finish its 1st SMI
// //
while (!mRebased[Index]); while (!mRebased[Index]) {
}
} else { } else {
// //
// BSP will be Relocated later // BSP will be Relocated later
@@ -477,7 +484,8 @@ SmmRelocateBases (
// //
// Wait for the BSP to finish its 1st SMI // Wait for the BSP to finish its 1st SMI
// //
while (!mRebased[BspIndex]); while (!mRebased[BspIndex]) {
}
// //
// Restore contents at address 0x38000 // Restore contents at address 0x38000
@@ -599,9 +607,9 @@ PiCpuSmmEntry (
// //
DEBUG_CODE_BEGIN (); DEBUG_CODE_BEGIN ();
if (FeaturePcdGet (PcdCpuHotPlugSupport)) { if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection)); ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
} }
DEBUG_CODE_END (); DEBUG_CODE_END ();
// //
@@ -625,6 +633,7 @@ PiCpuSmmEntry (
} else { } else {
mMaxNumberOfCpus = mNumberOfCpus; mMaxNumberOfCpus = mNumberOfCpus;
} }
gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus; gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;
// //
@@ -703,7 +712,7 @@ PiCpuSmmEntry (
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
FamilyId = (RegEax >> 8) & 0xf; FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf; ModelId = (RegEax >> 4) & 0xf;
if (FamilyId == 0x06 || FamilyId == 0x0f) { if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0); ModelId = ModelId | ((RegEax >> 12) & 0xf0);
} }
@@ -712,6 +721,7 @@ PiCpuSmmEntry (
if (RegEax >= CPUID_EXTENDED_CPU_SIG) { if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx); AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
} }
// //
// Determine the mode of the CPU at the time an SMI occurs // Determine the mode of the CPU at the time an SMI occurs
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
@@ -721,8 +731,9 @@ PiCpuSmmEntry (
if ((RegEdx & BIT29) != 0) { if ((RegEdx & BIT29) != 0) {
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
} }
if (FamilyId == 0x06) { if (FamilyId == 0x06) {
if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) { if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) {
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
} }
} }
@@ -739,17 +750,18 @@ PiCpuSmmEntry (
mCetSupported = FALSE; mCetSupported = FALSE;
PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1); PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);
} }
if (mCetSupported) { if (mCetSupported) {
AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL); AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL);
DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx)); DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx));
AsmCpuidEx (CPUID_EXTENDED_STATE, 11, &RegEax, NULL, &RegEcx, NULL); AsmCpuidEx (CPUID_EXTENDED_STATE, 11, &RegEax, NULL, &RegEcx, NULL);
DEBUG ((DEBUG_INFO, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx)); DEBUG ((DEBUG_INFO, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));
AsmCpuidEx(CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL); AsmCpuidEx (CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL);
DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx)); DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));
} }
} else { } else {
mCetSupported = FALSE; mCetSupported = FALSE;
PatchInstructionX86(mPatchCetSupported, mCetSupported, 1); PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);
} }
} else { } else {
mCetSupported = FALSE; mCetSupported = FALSE;
@@ -762,9 +774,9 @@ PiCpuSmmEntry (
// This size is rounded up to nearest power of 2. // This size is rounded up to nearest power of 2.
// //
TileCodeSize = GetSmiHandlerSize (); TileCodeSize = GetSmiHandlerSize ();
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB); TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1; TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
@@ -796,8 +808,9 @@ PiCpuSmmEntry (
} else { } else {
Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB); Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
} }
ASSERT (Buffer != NULL); ASSERT (Buffer != NULL);
DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages))); DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages)));
// //
// Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA. // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
@@ -833,7 +846,7 @@ PiCpuSmmEntry (
// //
for (Index = 0; Index < mMaxNumberOfCpus; Index++) { for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET; mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP); gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP);
gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET); gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
gSmmCpuPrivate->Operation[Index] = SmmCpuNone; gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
@@ -842,7 +855,9 @@ PiCpuSmmEntry (
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId; mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;
DEBUG ((DEBUG_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n", DEBUG ((
DEBUG_INFO,
"CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
Index, Index,
(UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId, (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,
mCpuHotPlugData.SmBase[Index], mCpuHotPlugData.SmBase[Index],
@@ -916,7 +931,7 @@ PiCpuSmmEntry (
} }
} }
Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize))); Stacks = (UINT8 *)AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize)));
ASSERT (Stacks != NULL); ASSERT (Stacks != NULL);
mSmmStackArrayBase = (UINTN)Stacks; mSmmStackArrayBase = (UINTN)Stacks;
mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1; mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1;
@@ -933,7 +948,7 @@ PiCpuSmmEntry (
// //
PatchInstructionX86 ( PatchInstructionX86 (
gPatchSmmInitStack, gPatchSmmInitStack,
(UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)), (UINTN)(Stacks + mSmmStackSize - sizeof (UINTN)),
sizeof (UINTN) sizeof (UINTN)
); );
@@ -977,8 +992,8 @@ PiCpuSmmEntry (
if (FeaturePcdGet (PcdCpuSmmStackGuard)) { if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
SetNotPresentPage ( SetNotPresentPage (
Cr3, Cr3,
(EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE(1) + (mSmmStackSize + mSmmShadowStackSize) * Index, (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE (1) + (mSmmStackSize + mSmmShadowStackSize) * Index,
EFI_PAGES_TO_SIZE(1) EFI_PAGES_TO_SIZE (1)
); );
} }
} }
@@ -997,7 +1012,8 @@ PiCpuSmmEntry (
// //
Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces ( Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (
&gSmmCpuPrivate->SmmCpuHandle, &gSmmCpuPrivate->SmmCpuHandle,
&gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration, &gEfiSmmConfigurationProtocolGuid,
&gSmmCpuPrivate->SmmConfiguration,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -1150,12 +1166,13 @@ FindSmramInfo (
do { do {
Found = FALSE; Found = FALSE;
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) { for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase && if ((mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase) &&
*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) { (*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)))
{
*SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart; *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
*SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize); *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE; Found = TRUE;
} else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) { } else if (((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart) && (mSmmCpuSmramRanges[Index].PhysicalSize > 0)) {
*SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize); *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE; Found = TRUE;
} }
@@ -1272,6 +1289,7 @@ ConfigSmmCodeAccessCheck (
// //
continue; continue;
} }
// //
// Acquire Config SMM Code Access Check spin lock. The AP will release the // Acquire Config SMM Code Access Check spin lock. The AP will release the
// spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor(). // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
@@ -1325,6 +1343,7 @@ AllocatePageTableMemory (
if (Buffer != NULL) { if (Buffer != NULL) {
return Buffer; return Buffer;
} }
return AllocatePages (Pages); return AllocatePages (Pages);
} }
@@ -1351,7 +1370,8 @@ AllocateCodePages (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return NULL; return NULL;
} }
return (VOID *) (UINTN) Memory;
return (VOID *)(UINTN)Memory;
} }
/** /**
@@ -1385,6 +1405,7 @@ AllocateAlignedCodePages (
if (Pages == 0) { if (Pages == 0) {
return NULL; return NULL;
} }
if (Alignment > EFI_PAGE_SIZE) { if (Alignment > EFI_PAGE_SIZE) {
// //
// Calculate the total number of pages since alignment is larger than page size. // Calculate the total number of pages since alignment is larger than page size.
@@ -1400,8 +1421,9 @@ AllocateAlignedCodePages (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return NULL; return NULL;
} }
AlignedMemory = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;
UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory); AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) { if (UnalignedPages > 0) {
// //
// Free first unaligned page(s). // Free first unaligned page(s).
@@ -1409,6 +1431,7 @@ AllocateAlignedCodePages (
Status = gSmst->SmmFreePages (Memory, UnalignedPages); Status = gSmst->SmmFreePages (Memory, UnalignedPages);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages); Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);
UnalignedPages = RealPages - Pages - UnalignedPages; UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) { if (UnalignedPages > 0) {
@@ -1426,9 +1449,11 @@ AllocateAlignedCodePages (
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return NULL; return NULL;
} }
AlignedMemory = (UINTN) Memory;
AlignedMemory = (UINTN)Memory;
} }
return (VOID *) AlignedMemory;
return (VOID *)AlignedMemory;
} }
/** /**
@@ -1447,6 +1472,7 @@ PerformRemainingTasks (
if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
SmmProfileStart (); SmmProfileStart ();
} }
// //
// Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable. // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
// //

24
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
View File

@@ -74,32 +74,32 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
typedef union { typedef union {
struct { struct {
// enable shadow stacks // enable shadow stacks
UINT32 SH_STK_ENP:1; UINT32 SH_STK_ENP : 1;
// enable the WRSS{D,Q}W instructions. // enable the WRSS{D,Q}W instructions.
UINT32 WR_SHSTK_EN:1; UINT32 WR_SHSTK_EN : 1;
// enable tracking of indirect call/jmp targets to be ENDBRANCH instruction. // enable tracking of indirect call/jmp targets to be ENDBRANCH instruction.
UINT32 ENDBR_EN:1; UINT32 ENDBR_EN : 1;
// enable legacy compatibility treatment for indirect call/jmp tracking. // enable legacy compatibility treatment for indirect call/jmp tracking.
UINT32 LEG_IW_EN:1; UINT32 LEG_IW_EN : 1;
// enable use of no-track prefix on indirect call/jmp. // enable use of no-track prefix on indirect call/jmp.
UINT32 NO_TRACK_EN:1; UINT32 NO_TRACK_EN : 1;
// disable suppression of CET indirect branch tracking on legacy compatibility. // disable suppression of CET indirect branch tracking on legacy compatibility.
UINT32 SUPPRESS_DIS:1; UINT32 SUPPRESS_DIS : 1;
UINT32 RSVD:4; UINT32 RSVD : 4;
// indirect branch tracking is suppressed. // indirect branch tracking is suppressed.
// This bit can be written to 1 only if TRACKER is written as IDLE. // This bit can be written to 1 only if TRACKER is written as IDLE.
UINT32 SUPPRESS:1; UINT32 SUPPRESS : 1;
// Value of the endbranch state machine // Value of the endbranch state machine
// Values: IDLE (0), WAIT_FOR_ENDBRANCH(1). // Values: IDLE (0), WAIT_FOR_ENDBRANCH(1).
UINT32 TRACKER:1; UINT32 TRACKER : 1;
// linear address of a bitmap in memory indicating valid // linear address of a bitmap in memory indicating valid
// pages as target of CALL/JMP_indirect that do not land on ENDBRANCH when CET is enabled // pages as target of CALL/JMP_indirect that do not land on ENDBRANCH when CET is enabled
// and not suppressed. Valid when ENDBR_EN is 1. Must be machine canonical when written on // and not suppressed. Valid when ENDBR_EN is 1. Must be machine canonical when written on
// parts that support 64 bit mode. On parts that do not support 64 bit mode, the bits 63:32 are // parts that support 64 bit mode. On parts that do not support 64 bit mode, the bits 63:32 are
// reserved and must be 0. This value is extended by 12 bits at the low end to form the base address // reserved and must be 0. This value is extended by 12 bits at the low end to form the base address
// (this automatically aligns the address on a 4-Kbyte boundary). // (this automatically aligns the address on a 4-Kbyte boundary).
UINT32 EB_LEG_BITMAP_BASE_low:12; UINT32 EB_LEG_BITMAP_BASE_low : 12;
UINT32 EB_LEG_BITMAP_BASE_high:32; UINT32 EB_LEG_BITMAP_BASE_high : 32;
} Bits; } Bits;
UINT64 Uint64; UINT64 Uint64;
} MSR_IA32_CET; } MSR_IA32_CET;
@@ -500,7 +500,6 @@ Gen4GPageTable (
IN BOOLEAN Is32BitPageTable IN BOOLEAN Is32BitPageTable
); );
/** /**
Initialize global data for MP synchronization. Initialize global data for MP synchronization.
@@ -1080,7 +1079,6 @@ AllocateAlignedCodePages (
IN UINTN Alignment IN UINTN Alignment
); );
// //
// S3 related global variable and function prototype. // S3 related global variable and function prototype.
// //

173
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
View File

@@ -27,9 +27,9 @@ UINTN mGcdMemNumberOfDesc = 0;
EFI_MEMORY_ATTRIBUTES_TABLE *mUefiMemoryAttributesTable = NULL; EFI_MEMORY_ATTRIBUTES_TABLE *mUefiMemoryAttributesTable = NULL;
PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
{Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64}, { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64 },
{Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64}, { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64 },
{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 },
}; };
UINTN mInternalCr3; UINTN mInternalCr3;
@@ -62,11 +62,13 @@ PageAttributeToLength (
) )
{ {
UINTN Index; UINTN Index;
for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) { if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].Length; return (UINTN)mPageAttributeTable[Index].Length;
} }
} }
return 0; return 0;
} }
@@ -83,11 +85,13 @@ PageAttributeToMask (
) )
{ {
UINTN Index; UINTN Index;
for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {
for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) { if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].AddressMask; return (UINTN)mPageAttributeTable[Index].AddressMask;
} }
} }
return 0; return 0;
} }
@@ -126,7 +130,7 @@ GetPageTableEntry (
Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;
Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;
if (sizeof(UINTN) == sizeof(UINT64)) { if (sizeof (UINTN) == sizeof (UINT64)) {
if (Enable5LevelPaging) { if (Enable5LevelPaging) {
L5PageTable = (UINT64 *)PageTableBase; L5PageTable = (UINT64 *)PageTableBase;
if (L5PageTable[Index5] == 0) { if (L5PageTable[Index5] == 0) {
@@ -138,6 +142,7 @@ GetPageTableEntry (
} else { } else {
L4PageTable = (UINT64 *)PageTableBase; L4PageTable = (UINT64 *)PageTableBase;
} }
if (L4PageTable[Index4] == 0) { if (L4PageTable[Index4] == 0) {
*PageAttribute = PageNone; *PageAttribute = PageNone;
return NULL; return NULL;
@@ -147,10 +152,12 @@ GetPageTableEntry (
} else { } else {
L3PageTable = (UINT64 *)PageTableBase; L3PageTable = (UINT64 *)PageTableBase;
} }
if (L3PageTable[Index3] == 0) { if (L3PageTable[Index3] == 0) {
*PageAttribute = PageNone; *PageAttribute = PageNone;
return NULL; return NULL;
} }
if ((L3PageTable[Index3] & IA32_PG_PS) != 0) { if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
// 1G // 1G
*PageAttribute = Page1G; *PageAttribute = Page1G;
@@ -162,6 +169,7 @@ GetPageTableEntry (
*PageAttribute = PageNone; *PageAttribute = PageNone;
return NULL; return NULL;
} }
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) { if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M // 2M
*PageAttribute = Page2M; *PageAttribute = Page2M;
@@ -174,6 +182,7 @@ GetPageTableEntry (
*PageAttribute = PageNone; *PageAttribute = PageNone;
return NULL; return NULL;
} }
*PageAttribute = Page4K; *PageAttribute = Page4K;
return &L1PageTable[Index1]; return &L1PageTable[Index1];
} }
@@ -191,16 +200,20 @@ GetAttributesFromPageEntry (
) )
{ {
UINT64 Attributes; UINT64 Attributes;
Attributes = 0; Attributes = 0;
if ((*PageEntry & IA32_PG_P) == 0) { if ((*PageEntry & IA32_PG_P) == 0) {
Attributes |= EFI_MEMORY_RP; Attributes |= EFI_MEMORY_RP;
} }
if ((*PageEntry & IA32_PG_RW) == 0) { if ((*PageEntry & IA32_PG_RW) == 0) {
Attributes |= EFI_MEMORY_RO; Attributes |= EFI_MEMORY_RO;
} }
if ((*PageEntry & IA32_PG_NX) != 0) { if ((*PageEntry & IA32_PG_NX) != 0) {
Attributes |= EFI_MEMORY_XP; Attributes |= EFI_MEMORY_XP;
} }
return Attributes; return Attributes;
} }
@@ -232,6 +245,7 @@ ConvertPageEntryAttribute (
NewPageEntry |= IA32_PG_P; NewPageEntry |= IA32_PG_P;
} }
} }
if ((Attributes & EFI_MEMORY_RO) != 0) { if ((Attributes & EFI_MEMORY_RO) != 0) {
if (IsSet) { if (IsSet) {
NewPageEntry &= ~(UINT64)IA32_PG_RW; NewPageEntry &= ~(UINT64)IA32_PG_RW;
@@ -250,6 +264,7 @@ ConvertPageEntryAttribute (
NewPageEntry |= IA32_PG_RW; NewPageEntry |= IA32_PG_RW;
} }
} }
if ((Attributes & EFI_MEMORY_XP) != 0) { if ((Attributes & EFI_MEMORY_XP) != 0) {
if (mXdSupported) { if (mXdSupported) {
if (IsSet) { if (IsSet) {
@@ -259,6 +274,7 @@ ConvertPageEntryAttribute (
} }
} }
} }
*PageEntry = NewPageEntry; *PageEntry = NewPageEntry;
if (CurrentPageEntry != NewPageEntry) { if (CurrentPageEntry != NewPageEntry) {
*IsModified = TRUE; *IsModified = TRUE;
@@ -337,10 +353,12 @@ SplitPage (
if (NewPageEntry == NULL) { if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64; BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64;
for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS); NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
} }
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; (*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
return RETURN_SUCCESS; return RETURN_SUCCESS;
} else { } else {
@@ -352,16 +370,18 @@ SplitPage (
// No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table. // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.
// //
ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K); ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);
if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) { if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) {
NewPageEntry = AllocatePageTableMemory (1); NewPageEntry = AllocatePageTableMemory (1);
DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry)); DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));
if (NewPageEntry == NULL) { if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64; BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64;
for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS); NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
} }
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; (*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
return RETURN_SUCCESS; return RETURN_SUCCESS;
} else { } else {
@@ -431,18 +451,21 @@ ConvertMemoryPageAttributes (
if (BaseAddress > MaximumSupportMemAddress) { if (BaseAddress > MaximumSupportMemAddress) {
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
if (Length > MaximumSupportMemAddress) { if (Length > MaximumSupportMemAddress) {
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
if ((Length != 0) && (BaseAddress > MaximumSupportMemAddress - (Length - 1))) { if ((Length != 0) && (BaseAddress > MaximumSupportMemAddress - (Length - 1))) {
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
// DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes)); // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));
if (IsSplitted != NULL) { if (IsSplitted != NULL) {
*IsSplitted = FALSE; *IsSplitted = FALSE;
} }
if (IsModified != NULL) { if (IsModified != NULL) {
*IsModified = FALSE; *IsModified = FALSE;
} }
@@ -455,6 +478,7 @@ ConvertMemoryPageAttributes (
if (PageEntry == NULL) { if (PageEntry == NULL) {
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
PageEntryLength = PageAttributeToLength (PageAttribute); PageEntryLength = PageAttributeToLength (PageAttribute);
SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute); SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);
if (SplitAttribute == PageNone) { if (SplitAttribute == PageNone) {
@@ -464,6 +488,7 @@ ConvertMemoryPageAttributes (
*IsModified = TRUE; *IsModified = TRUE;
} }
} }
// //
// Convert success, move to next // Convert success, move to next
// //
@@ -474,12 +499,15 @@ ConvertMemoryPageAttributes (
if (RETURN_ERROR (Status)) { if (RETURN_ERROR (Status)) {
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
if (IsSplitted != NULL) { if (IsSplitted != NULL) {
*IsSplitted = TRUE; *IsSplitted = TRUE;
} }
if (IsModified != NULL) { if (IsModified != NULL) {
*IsModified = TRUE; *IsModified = TRUE;
} }
// //
// Just split current page // Just split current page
// Convert success in next around // Convert success in next around
@@ -561,12 +589,12 @@ SmmSetMemoryAttributesEx (
BOOLEAN IsModified; BOOLEAN IsModified;
Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, TRUE, IsSplitted, &IsModified); Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, TRUE, IsSplitted, &IsModified);
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
if (IsModified) { if (IsModified) {
// //
// Flush TLB as last step // Flush TLB as last step
// //
FlushTlbForAll(); FlushTlbForAll ();
} }
} }
@@ -609,12 +637,12 @@ SmmClearMemoryAttributesEx (
BOOLEAN IsModified; BOOLEAN IsModified;
Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, FALSE, IsSplitted, &IsModified); Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, FALSE, IsSplitted, &IsModified);
if (!EFI_ERROR(Status)) { if (!EFI_ERROR (Status)) {
if (IsModified) { if (IsModified) {
// //
// Flush TLB as last step // Flush TLB as last step
// //
FlushTlbForAll(); FlushTlbForAll ();
} }
} }
@@ -789,9 +817,9 @@ PatchSmmSaveStateMap (
UINTN TileSize; UINTN TileSize;
TileCodeSize = GetSmiHandlerSize (); TileCodeSize = GetSmiHandlerSize ();
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB); TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);
TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1; TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize); TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
@@ -872,7 +900,7 @@ PatchGdtIdtMap (
DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - GDT:\n")); DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - GDT:\n"));
BaseAddress = mGdtBuffer; BaseAddress = mGdtBuffer;
Size = ALIGN_VALUE(mGdtBufferSize, SIZE_4KB); Size = ALIGN_VALUE (mGdtBufferSize, SIZE_4KB);
// //
// The range should have been set to RO // The range should have been set to RO
// if it is allocated with EfiRuntimeServicesCode. // if it is allocated with EfiRuntimeServicesCode.
@@ -889,7 +917,7 @@ PatchGdtIdtMap (
DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - IDT:\n")); DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - IDT:\n"));
BaseAddress = gcSmiIdtr.Base; BaseAddress = gcSmiIdtr.Base;
Size = ALIGN_VALUE(gcSmiIdtr.Limit + 1, SIZE_4KB); Size = ALIGN_VALUE (gcSmiIdtr.Limit + 1, SIZE_4KB);
// //
// The range should have been set to RO // The range should have been set to RO
// if it is allocated with EfiRuntimeServicesCode. // if it is allocated with EfiRuntimeServicesCode.
@@ -919,7 +947,7 @@ SetMemMapAttributes (
SmmGetSystemConfigurationTable (&gEdkiiPiSmmMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable); SmmGetSystemConfigurationTable (&gEdkiiPiSmmMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable);
if (MemoryAttributesTable == NULL) { if (MemoryAttributesTable == NULL) {
DEBUG ((DEBUG_INFO, "MemoryAttributesTable - NULL\n")); DEBUG ((DEBUG_INFO, "MemoryAttributesTable - NULL\n"));
return ; return;
} }
DEBUG ((DEBUG_INFO, "MemoryAttributesTable:\n")); DEBUG ((DEBUG_INFO, "MemoryAttributesTable:\n"));
@@ -938,7 +966,7 @@ SetMemMapAttributes (
DEBUG ((DEBUG_INFO, " VirtualStart - 0x%016lx\n", MemoryMap->VirtualStart)); DEBUG ((DEBUG_INFO, " VirtualStart - 0x%016lx\n", MemoryMap->VirtualStart));
DEBUG ((DEBUG_INFO, " NumberOfPages - 0x%016lx\n", MemoryMap->NumberOfPages)); DEBUG ((DEBUG_INFO, " NumberOfPages - 0x%016lx\n", MemoryMap->NumberOfPages));
DEBUG ((DEBUG_INFO, " Attribute - 0x%016lx\n", MemoryMap->Attribute)); DEBUG ((DEBUG_INFO, " Attribute - 0x%016lx\n", MemoryMap->Attribute));
MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize); MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);
} }
MemoryMap = MemoryMapStart; MemoryMap = MemoryMapStart;
@@ -948,32 +976,33 @@ SetMemMapAttributes (
case EfiRuntimeServicesCode: case EfiRuntimeServicesCode:
SmmSetMemoryAttributes ( SmmSetMemoryAttributes (
MemoryMap->PhysicalStart, MemoryMap->PhysicalStart,
EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
EFI_MEMORY_RO EFI_MEMORY_RO
); );
break; break;
case EfiRuntimeServicesData: case EfiRuntimeServicesData:
SmmSetMemoryAttributes ( SmmSetMemoryAttributes (
MemoryMap->PhysicalStart, MemoryMap->PhysicalStart,
EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
EFI_MEMORY_XP EFI_MEMORY_XP
); );
break; break;
default: default:
SmmSetMemoryAttributes ( SmmSetMemoryAttributes (
MemoryMap->PhysicalStart, MemoryMap->PhysicalStart,
EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
EFI_MEMORY_XP EFI_MEMORY_XP
); );
break; break;
} }
MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize);
MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);
} }
PatchSmmSaveStateMap (); PatchSmmSaveStateMap ();
PatchGdtIdtMap (); PatchGdtIdtMap ();
return ; return;
} }
/** /**
@@ -999,13 +1028,13 @@ SortMemoryMap (
MemoryMapEntry = MemoryMap; MemoryMapEntry = MemoryMap;
NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + MemoryMapSize); MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + MemoryMapSize);
while (MemoryMapEntry < MemoryMapEnd) { while (MemoryMapEntry < MemoryMapEnd) {
while (NextMemoryMapEntry < MemoryMapEnd) { while (NextMemoryMapEntry < MemoryMapEnd) {
if (MemoryMapEntry->PhysicalStart > NextMemoryMapEntry->PhysicalStart) { if (MemoryMapEntry->PhysicalStart > NextMemoryMapEntry->PhysicalStart) {
CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR)); CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));
CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR)); CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));
CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof(EFI_MEMORY_DESCRIPTOR)); CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof (EFI_MEMORY_DESCRIPTOR));
} }
NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NextMemoryMapEntry, DescriptorSize); NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NextMemoryMapEntry, DescriptorSize);
@@ -1077,16 +1106,17 @@ MergeMemoryMapForNotPresentEntry (
MemoryMapEntry = MemoryMap; MemoryMapEntry = MemoryMap;
NewMemoryMapEntry = MemoryMap; NewMemoryMapEntry = MemoryMap;
MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + *MemoryMapSize); MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + *MemoryMapSize);
while ((UINTN)MemoryMapEntry < (UINTN)MemoryMapEnd) { while ((UINTN)MemoryMapEntry < (UINTN)MemoryMapEnd) {
CopyMem (NewMemoryMapEntry, MemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR)); CopyMem (NewMemoryMapEntry, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));
NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize); NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);
do { do {
MemoryBlockLength = (UINT64) (EFI_PAGES_TO_SIZE((UINTN)MemoryMapEntry->NumberOfPages)); MemoryBlockLength = (UINT64)(EFI_PAGES_TO_SIZE ((UINTN)MemoryMapEntry->NumberOfPages));
if (((UINTN)NextMemoryMapEntry < (UINTN)MemoryMapEnd) && if (((UINTN)NextMemoryMapEntry < (UINTN)MemoryMapEnd) &&
IsUefiPageNotPresent(MemoryMapEntry) && IsUefiPageNotPresent(NextMemoryMapEntry) && IsUefiPageNotPresent (MemoryMapEntry) && IsUefiPageNotPresent (NextMemoryMapEntry) &&
((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart)) { ((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart))
{
MemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages; MemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages;
if (NewMemoryMapEntry != MemoryMapEntry) { if (NewMemoryMapEntry != MemoryMapEntry) {
NewMemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages; NewMemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages;
@@ -1106,7 +1136,7 @@ MergeMemoryMapForNotPresentEntry (
*MemoryMapSize = (UINTN)NewMemoryMapEntry - (UINTN)MemoryMap; *MemoryMapSize = (UINTN)NewMemoryMapEntry - (UINTN)MemoryMap;
return ; return;
} }
/** /**
@@ -1124,15 +1154,16 @@ GetGcdMemoryMap (
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemSpaceMap); Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemSpaceMap);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return ; return;
} }
mGcdMemNumberOfDesc = 0; mGcdMemNumberOfDesc = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) { for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved && if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&
(MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) == ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
(EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED) (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))
) { )
{
mGcdMemNumberOfDesc++; mGcdMemNumberOfDesc++;
} }
} }
@@ -1142,19 +1173,20 @@ GetGcdMemoryMap (
if (mGcdMemSpace == NULL) { if (mGcdMemSpace == NULL) {
mGcdMemNumberOfDesc = 0; mGcdMemNumberOfDesc = 0;
gBS->FreePool (MemSpaceMap); gBS->FreePool (MemSpaceMap);
return ; return;
} }
mGcdMemNumberOfDesc = 0; mGcdMemNumberOfDesc = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) { for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved && if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&
(MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) == ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
(EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED) (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))
) { )
{
CopyMem ( CopyMem (
&mGcdMemSpace[mGcdMemNumberOfDesc], &mGcdMemSpace[mGcdMemNumberOfDesc],
&MemSpaceMap[Index], &MemSpaceMap[Index],
sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR) sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR)
); );
mGcdMemNumberOfDesc++; mGcdMemNumberOfDesc++;
} }
@@ -1177,7 +1209,7 @@ GetUefiMemoryAttributesTable (
Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable); Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable);
if (!EFI_ERROR (Status) && (MemoryAttributesTable != NULL)) { if (!EFI_ERROR (Status) && (MemoryAttributesTable != NULL)) {
MemoryAttributesTableSize = sizeof(EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries; MemoryAttributesTableSize = sizeof (EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries;
mUefiMemoryAttributesTable = AllocateCopyPool (MemoryAttributesTableSize, MemoryAttributesTable); mUefiMemoryAttributesTable = AllocateCopyPool (MemoryAttributesTableSize, MemoryAttributesTable);
ASSERT (mUefiMemoryAttributesTable != NULL); ASSERT (mUefiMemoryAttributesTable != NULL);
} }
@@ -1214,7 +1246,7 @@ GetUefiMemoryMap (
Status = gBS->AllocatePool (EfiBootServicesData, UefiMemoryMapSize, (VOID **)&MemoryMap); Status = gBS->AllocatePool (EfiBootServicesData, UefiMemoryMapSize, (VOID **)&MemoryMap);
ASSERT (MemoryMap != NULL); ASSERT (MemoryMap != NULL);
if (MemoryMap == NULL) { if (MemoryMap == NULL) {
return ; return;
} }
Status = gBS->GetMemoryMap ( Status = gBS->GetMemoryMap (
@@ -1231,7 +1263,7 @@ GetUefiMemoryMap (
} while (Status == EFI_BUFFER_TOO_SMALL); } while (Status == EFI_BUFFER_TOO_SMALL);
if (MemoryMap == NULL) { if (MemoryMap == NULL) {
return ; return;
} }
SortMemoryMap (MemoryMap, UefiMemoryMapSize, mUefiDescriptorSize); SortMemoryMap (MemoryMap, UefiMemoryMapSize, mUefiDescriptorSize);
@@ -1278,23 +1310,25 @@ SetUefiMemMapAttributes (
MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize; MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize;
MemoryMap = mUefiMemoryMap; MemoryMap = mUefiMemoryMap;
for (Index = 0; Index < MemoryMapEntryCount; Index++) { for (Index = 0; Index < MemoryMapEntryCount; Index++) {
if (IsUefiPageNotPresent(MemoryMap)) { if (IsUefiPageNotPresent (MemoryMap)) {
Status = SmmSetMemoryAttributes ( Status = SmmSetMemoryAttributes (
MemoryMap->PhysicalStart, MemoryMap->PhysicalStart,
EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
EFI_MEMORY_RP EFI_MEMORY_RP
); );
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"UefiMemory protection: 0x%lx - 0x%lx %r\n", "UefiMemory protection: 0x%lx - 0x%lx %r\n",
MemoryMap->PhysicalStart, MemoryMap->PhysicalStart,
MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),
Status Status
)); ));
} }
MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSize);
MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize);
} }
} }
// //
// Do not free mUefiMemoryMap, it will be checked in IsSmmCommBufferForbiddenAddress(). // Do not free mUefiMemoryMap, it will be checked in IsSmmCommBufferForbiddenAddress().
// //
@@ -1318,6 +1352,7 @@ SetUefiMemMapAttributes (
)); ));
} }
} }
// //
// Do not free mGcdMemSpace, it will be checked in IsSmmCommBufferForbiddenAddress(). // Do not free mGcdMemSpace, it will be checked in IsSmmCommBufferForbiddenAddress().
// //
@@ -1328,25 +1363,27 @@ SetUefiMemMapAttributes (
if (mUefiMemoryAttributesTable != NULL) { if (mUefiMemoryAttributesTable != NULL) {
Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1); Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1);
for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) { for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) {
if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) { if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {
if ((Entry->Attribute & EFI_MEMORY_RO) != 0) { if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {
Status = SmmSetMemoryAttributes ( Status = SmmSetMemoryAttributes (
Entry->PhysicalStart, Entry->PhysicalStart,
EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages), EFI_PAGES_TO_SIZE ((UINTN)Entry->NumberOfPages),
EFI_MEMORY_RP EFI_MEMORY_RP
); );
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"UefiMemoryAttribute protection: 0x%lx - 0x%lx %r\n", "UefiMemoryAttribute protection: 0x%lx - 0x%lx %r\n",
Entry->PhysicalStart, Entry->PhysicalStart,
Entry->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages), Entry->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE ((UINTN)Entry->NumberOfPages),
Status Status
)); ));
} }
} }
Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize); Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize);
} }
} }
// //
// Do not free mUefiMemoryAttributesTable, it will be checked in IsSmmCommBufferForbiddenAddress(). // Do not free mUefiMemoryAttributesTable, it will be checked in IsSmmCommBufferForbiddenAddress().
// //
@@ -1376,18 +1413,21 @@ IsSmmCommBufferForbiddenAddress (
for (Index = 0; Index < MemoryMapEntryCount; Index++) { for (Index = 0; Index < MemoryMapEntryCount; Index++) {
if (IsUefiPageNotPresent (MemoryMap)) { if (IsUefiPageNotPresent (MemoryMap)) {
if ((Address >= MemoryMap->PhysicalStart) && if ((Address >= MemoryMap->PhysicalStart) &&
(Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages)) ) { (Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages)))
{
return TRUE; return TRUE;
} }
} }
MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSize);
MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize);
} }
} }
if (mGcdMemSpace != NULL) { if (mGcdMemSpace != NULL) {
for (Index = 0; Index < mGcdMemNumberOfDesc; Index++) { for (Index = 0; Index < mGcdMemNumberOfDesc; Index++) {
if ((Address >= mGcdMemSpace[Index].BaseAddress) && if ((Address >= mGcdMemSpace[Index].BaseAddress) &&
(Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length) ) { (Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length))
{
return TRUE; return TRUE;
} }
} }
@@ -1396,17 +1436,20 @@ IsSmmCommBufferForbiddenAddress (
if (mUefiMemoryAttributesTable != NULL) { if (mUefiMemoryAttributesTable != NULL) {
Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1); Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1);
for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) { for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) {
if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) { if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {
if ((Entry->Attribute & EFI_MEMORY_RO) != 0) { if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {
if ((Address >= Entry->PhysicalStart) && if ((Address >= Entry->PhysicalStart) &&
(Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT))) { (Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT)))
{
return TRUE; return TRUE;
} }
Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize); Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize);
} }
} }
} }
} }
return FALSE; return FALSE;
} }
@@ -1516,7 +1559,7 @@ EdkiiSmmGetMemoryAttributes (
PAGE_ATTRIBUTE PageAttr; PAGE_ATTRIBUTE PageAttr;
INT64 Size; INT64 Size;
if (Length < SIZE_4KB || Attributes == NULL) { if ((Length < SIZE_4KB) || (Attributes == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -1524,9 +1567,8 @@ EdkiiSmmGetMemoryAttributes (
MemAttr = (UINT64)-1; MemAttr = (UINT64)-1;
do { do {
PageEntry = GetPageTableEntry (BaseAddress, &PageAttr); PageEntry = GetPageTableEntry (BaseAddress, &PageAttr);
if (PageEntry == NULL || PageAttr == PageNone) { if ((PageEntry == NULL) || (PageAttr == PageNone)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@@ -1535,7 +1577,7 @@ EdkiiSmmGetMemoryAttributes (
// share the same attribute. Return EFI_NO_MAPPING if not. // share the same attribute. Return EFI_NO_MAPPING if not.
// //
*Attributes = GetAttributesFromPageEntry (PageEntry); *Attributes = GetAttributesFromPageEntry (PageEntry);
if (MemAttr != (UINT64)-1 && *Attributes != MemAttr) { if ((MemAttr != (UINT64)-1) && (*Attributes != MemAttr)) {
return EFI_NO_MAPPING; return EFI_NO_MAPPING;
} }
@@ -1563,7 +1605,6 @@ EdkiiSmmGetMemoryAttributes (
} }
MemAttr = *Attributes; MemAttr = *Attributes;
} while (Size > 0); } while (Size > 0);
return EFI_SUCCESS; return EFI_SUCCESS;

3
UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c
View File

@@ -210,7 +210,7 @@ SmmMpBroadcastProcedure (
IN OUT EFI_STATUS *CPUStatus IN OUT EFI_STATUS *CPUStatus
) )
{ {
return InternalSmmStartupAllAPs( return InternalSmmStartupAllAPs (
Procedure, Procedure,
TimeoutInMicroseconds, TimeoutInMicroseconds,
ProcedureArguments, ProcedureArguments,
@@ -341,4 +341,3 @@ SmmMpWaitForProcedure (
return Status; return Status;
} }

2
UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h
View File

@@ -31,7 +31,6 @@ SmmMpGetNumberOfProcessors (
OUT UINTN *NumberOfProcessors OUT UINTN *NumberOfProcessors
); );
/** /**
This service allows the caller to invoke a procedure one of the application processors (AP). This This service allows the caller to invoke a procedure one of the application processors (AP). This
function uses an optional token parameter to support blocking and non-blocking modes. If the token function uses an optional token parameter to support blocking and non-blocking modes. If the token
@@ -182,7 +181,6 @@ SmmMpBroadcastProcedure (
IN OUT EFI_STATUS *CPUStatus IN OUT EFI_STATUS *CPUStatus
); );
/** /**
This service allows the caller to set a startup procedure that will be executed when an AP powers This service allows the caller to set a startup procedure that will be executed when an AP powers
up from a state where core configuration and context is lost. The procedure is execution has the up from a state where core configuration and context is lost. The procedure is execution has the

158
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
View File

@@ -78,13 +78,17 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
// SMRAM range (to be fixed in runtime). // SMRAM range (to be fixed in runtime).
// It is always present and instruction fetches are allowed. // It is always present and instruction fetches are allowed.
// //
{{0x00000000, 0x00000000},TRUE,FALSE}, {
{ 0x00000000, 0x00000000 }, TRUE, FALSE
},
// //
// SMM profile data range( to be fixed in runtime). // SMM profile data range( to be fixed in runtime).
// It is always present and instruction fetches are not allowed. // It is always present and instruction fetches are not allowed.
// //
{{0x00000000, 0x00000000},TRUE,TRUE}, {
{ 0x00000000, 0x00000000 }, TRUE, TRUE
},
// //
// SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime). // SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).
@@ -156,6 +160,7 @@ GetCpuIndex (
return Index; return Index;
} }
} }
ASSERT (FALSE); ASSERT (FALSE);
return 0; return 0;
} }
@@ -186,8 +191,9 @@ GetSourceFromDestinationOnBts (
// Underflow // Underflow
// //
CurrentBTSRecord = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[CpuIndex]->BTSAbsoluteMaximum - 1); CurrentBTSRecord = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[CpuIndex]->BTSAbsoluteMaximum - 1);
CurrentBTSRecord --; CurrentBTSRecord--;
} }
if (CurrentBTSRecord->LastBranchTo == DestinationIP) { if (CurrentBTSRecord->LastBranchTo == DestinationIP) {
// //
// Good! find 1st one, then find 2nd one. // Good! find 1st one, then find 2nd one.
@@ -204,6 +210,7 @@ GetSourceFromDestinationOnBts (
return CurrentBTSRecord->LastBranchFrom; return CurrentBTSRecord->LastBranchFrom;
} }
} }
CurrentBTSRecord--; CurrentBTSRecord--;
} }
@@ -230,9 +237,11 @@ DebugExceptionHandler (
if (!mSmmProfileStart && if (!mSmmProfileStart &&
!HEAP_GUARD_NONSTOP_MODE && !HEAP_GUARD_NONSTOP_MODE &&
!NULL_DETECTION_NONSTOP_MODE) { !NULL_DETECTION_NONSTOP_MODE)
{
return; return;
} }
CpuIndex = GetCpuIndex (); CpuIndex = GetCpuIndex ();
// //
@@ -276,12 +285,15 @@ IsInSmmRanges (
if ((Address >= mCpuHotPlugData.SmrrBase) && (Address < mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) { if ((Address >= mCpuHotPlugData.SmrrBase) && (Address < mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
return TRUE; return TRUE;
} }
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) { for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
if (Address >= mSmmCpuSmramRanges[Index].CpuStart && if ((Address >= mSmmCpuSmramRanges[Index].CpuStart) &&
Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) { (Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize))
{
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }
@@ -310,14 +322,15 @@ IsAddressValid (
return mProtectionMemRange[Index].Present; return mProtectionMemRange[Index].Present;
} }
} }
*Nx = TRUE; *Nx = TRUE;
return FALSE; return FALSE;
} else { } else {
*Nx = TRUE; *Nx = TRUE;
if (IsInSmmRanges (Address)) { if (IsInSmmRanges (Address)) {
*Nx = FALSE; *Nx = FALSE;
} }
return TRUE; return TRUE;
} }
} }
@@ -355,6 +368,7 @@ IsAddressSplit (
} }
} }
} }
// //
// Return default // Return default
// //
@@ -404,7 +418,7 @@ InitProtectedMemRange (
if (NumberOfAddedDescriptors != 0) { if (NumberOfAddedDescriptors != 0) {
TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate); TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate);
mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool (TotalSize); mProtectionMemRange = (MEMORY_PROTECTION_RANGE *)AllocateZeroPool (TotalSize);
ASSERT (mProtectionMemRange != NULL); ASSERT (mProtectionMemRange != NULL);
mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE); mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE);
@@ -417,7 +431,7 @@ InitProtectedMemRange (
// Create split ranges which come from protected ranges. // Create split ranges which come from protected ranges.
// //
TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE); TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE);
mSplitMemRange = (MEMORY_RANGE *) AllocateZeroPool (TotalSize); mSplitMemRange = (MEMORY_RANGE *)AllocateZeroPool (TotalSize);
ASSERT (mSplitMemRange != NULL); ASSERT (mSplitMemRange != NULL);
// //
@@ -425,13 +439,15 @@ InitProtectedMemRange (
// //
NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE); NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE);
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) { for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
if (mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base && if ((mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base) &&
mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) { (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top))
{
// //
// If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz // If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz
// //
break; break;
} }
mProtectionMemRange[NumberOfProtectRange].Range.Base = mSmmCpuSmramRanges[Index].CpuStart; mProtectionMemRange[NumberOfProtectRange].Range.Base = mSmmCpuSmramRanges[Index].CpuStart;
mProtectionMemRange[NumberOfProtectRange].Range.Top = mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize; mProtectionMemRange[NumberOfProtectRange].Range.Top = mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize;
mProtectionMemRange[NumberOfProtectRange].Present = TRUE; mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
@@ -446,6 +462,7 @@ InitProtectedMemRange (
if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) { if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) {
continue; continue;
} }
mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress; mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress;
mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length; mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length;
mProtectionMemRange[NumberOfProtectRange].Present = TRUE; mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
@@ -479,7 +496,8 @@ InitProtectedMemRange (
Top2MBAlignedAddress = ProtectEndAddress & ~(SIZE_2MB - 1); Top2MBAlignedAddress = ProtectEndAddress & ~(SIZE_2MB - 1);
Base2MBAlignedAddress = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1); Base2MBAlignedAddress = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
if ((Top2MBAlignedAddress > Base2MBAlignedAddress) && if ((Top2MBAlignedAddress > Base2MBAlignedAddress) &&
((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB)) { ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB))
{
// //
// There is an range which could be mapped by 2MB-page. // There is an range which could be mapped by 2MB-page.
// //
@@ -493,6 +511,7 @@ InitProtectedMemRange (
mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1); mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
NumberOfSpliteRange++; NumberOfSpliteRange++;
} }
if (Low4KBPageSize != 0) { if (Low4KBPageSize != 0) {
// //
// Add not 2MB-aligned range to be mapped by 4KB-page. // Add not 2MB-aligned range to be mapped by 4KB-page.
@@ -519,6 +538,7 @@ InitProtectedMemRange (
DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base)); DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base));
DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top)); DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top));
} }
for (Index = 0; Index < mSplitMemRangeCount; Index++) { for (Index = 0; Index < mSplitMemRangeCount; Index++) {
DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base)); DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base));
DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top)); DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top));
@@ -556,38 +576,39 @@ InitPaging (
BOOLEAN Enable5LevelPaging; BOOLEAN Enable5LevelPaging;
Cr4.UintN = AsmReadCr4 (); Cr4.UintN = AsmReadCr4 ();
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
if (sizeof (UINTN) == sizeof (UINT64)) { if (sizeof (UINTN) == sizeof (UINT64)) {
if (!Enable5LevelPaging) { if (!Enable5LevelPaging) {
Pml5Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P; Pml5Entry = (UINTN)mSmmProfileCr3 | IA32_PG_P;
Pml5 = &Pml5Entry; Pml5 = &Pml5Entry;
} else { } else {
Pml5 = (UINT64*) (UINTN) mSmmProfileCr3; Pml5 = (UINT64 *)(UINTN)mSmmProfileCr3;
} }
SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1; SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;
// //
// Calculate the table entries of PML4E and PDPTE. // Calculate the table entries of PML4E and PDPTE.
// //
NumberOfPml5Entries = 1; NumberOfPml5Entries = 1;
if (SizeOfMemorySpace > 48) { if (SizeOfMemorySpace > 48) {
NumberOfPml5Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 48); NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);
SizeOfMemorySpace = 48; SizeOfMemorySpace = 48;
} }
NumberOfPml4Entries = 1; NumberOfPml4Entries = 1;
if (SizeOfMemorySpace > 39) { if (SizeOfMemorySpace > 39) {
NumberOfPml4Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 39); NumberOfPml4Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 39);
SizeOfMemorySpace = 39; SizeOfMemorySpace = 39;
} }
NumberOfPdptEntries = 1; NumberOfPdptEntries = 1;
ASSERT (SizeOfMemorySpace > 30); ASSERT (SizeOfMemorySpace > 30);
NumberOfPdptEntries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 30); NumberOfPdptEntries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 30);
} else { } else {
Pml4Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P; Pml4Entry = (UINTN)mSmmProfileCr3 | IA32_PG_P;
Pml4 = &Pml4Entry; Pml4 = &Pml4Entry;
Pml5Entry = (UINTN) Pml4 | IA32_PG_P; Pml5Entry = (UINTN)Pml4 | IA32_PG_P;
Pml5 = &Pml5Entry; Pml5 = &Pml5Entry;
NumberOfPml5Entries = 1; NumberOfPml5Entries = 1;
NumberOfPml4Entries = 1; NumberOfPml4Entries = 1;
@@ -604,7 +625,8 @@ InitPaging (
// //
continue; continue;
} }
Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) { for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
if ((Pml4[Pml4Index] & IA32_PG_P) == 0) { if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
// //
@@ -612,6 +634,7 @@ InitPaging (
// //
continue; continue;
} }
Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) { for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
if ((*Pdpt & IA32_PG_P) == 0) { if ((*Pdpt & IA32_PG_P) == 0) {
@@ -620,16 +643,19 @@ InitPaging (
// //
continue; continue;
} }
if ((*Pdpt & IA32_PG_PS) != 0) { if ((*Pdpt & IA32_PG_PS) != 0) {
// //
// This is 1G entry, skip it // This is 1G entry, skip it
// //
continue; continue;
} }
Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
if (Pd == 0) { if (Pd == 0) {
continue; continue;
} }
for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) { for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {
if ((*Pd & IA32_PG_P) == 0) { if ((*Pd & IA32_PG_P) == 0) {
// //
@@ -637,7 +663,8 @@ InitPaging (
// //
continue; continue;
} }
Address = (UINTN) LShiftU64 (
Address = (UINTN)LShiftU64 (
LShiftU64 ( LShiftU64 (
LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex, LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
9 9
@@ -658,9 +685,10 @@ InitPaging (
ASSERT (Pt != NULL); ASSERT (Pt != NULL);
// Split it // Split it
for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++) { for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++) {
Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS); Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
} // end for PT } // end for PT
*Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS; *Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
} // end if IsAddressSplit } // end if IsAddressSplit
} // end for PD } // end for PD
@@ -679,7 +707,8 @@ InitPaging (
// //
continue; continue;
} }
Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) { for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
if ((Pml4[Pml4Index] & IA32_PG_P) == 0) { if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
// //
@@ -687,6 +716,7 @@ InitPaging (
// //
continue; continue;
} }
Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) { for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
if ((*Pdpt & IA32_PG_P) == 0) { if ((*Pdpt & IA32_PG_P) == 0) {
@@ -695,6 +725,7 @@ InitPaging (
// //
continue; continue;
} }
if ((*Pdpt & IA32_PG_PS) != 0) { if ((*Pdpt & IA32_PG_PS) != 0) {
// //
// This is 1G entry, set NX bit and skip it // This is 1G entry, set NX bit and skip it
@@ -702,12 +733,15 @@ InitPaging (
if (mXdSupported) { if (mXdSupported) {
*Pdpt = *Pdpt | IA32_PG_NX; *Pdpt = *Pdpt | IA32_PG_NX;
} }
continue; continue;
} }
Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK); Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
if (Pd == 0) { if (Pd == 0) {
continue; continue;
} }
for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) { for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {
if ((*Pd & IA32_PG_P) == 0) { if ((*Pd & IA32_PG_P) == 0) {
// //
@@ -715,7 +749,8 @@ InitPaging (
// //
continue; continue;
} }
Address = (UINTN) LShiftU64 (
Address = (UINTN)LShiftU64 (
LShiftU64 ( LShiftU64 (
LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex, LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
9 9
@@ -732,6 +767,7 @@ InitPaging (
// //
*Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); *Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
} }
if (Nx && mXdSupported) { if (Nx && mXdSupported) {
*Pd = *Pd | IA32_PG_NX; *Pd = *Pd | IA32_PG_NX;
} }
@@ -741,13 +777,16 @@ InitPaging (
if (Pt == 0) { if (Pt == 0) {
continue; continue;
} }
for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {
for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++, Pt++) {
if (!IsAddressValid (Address, &Nx)) { if (!IsAddressValid (Address, &Nx)) {
*Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS); *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
} }
if (Nx && mXdSupported) { if (Nx && mXdSupported) {
*Pt = *Pt | IA32_PG_NX; *Pt = *Pt | IA32_PG_NX;
} }
Address += SIZE_4KB; Address += SIZE_4KB;
} // end for PT } // end for PT
} // end if PS } // end if PS
@@ -766,7 +805,7 @@ InitPaging (
// //
mXdEnabled = TRUE; mXdEnabled = TRUE;
return ; return;
} }
/** /**
@@ -780,7 +819,7 @@ GetSmiCommandPort (
{ {
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt; EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;
Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) EfiLocateFirstAcpiTable ( Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *)EfiLocateFirstAcpiTable (
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE
); );
ASSERT (Fadt != NULL); ASSERT (Fadt != NULL);
@@ -830,7 +869,7 @@ InitSmmProfileCallBack (
SMM_PROFILE_NAME, SMM_PROFILE_NAME,
&gEfiCallerIdGuid, &gEfiCallerIdGuid,
EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
sizeof(mSmmProfileBase), sizeof (mSmmProfileBase),
&mSmmProfileBase &mSmmProfileBase
); );
@@ -866,10 +905,12 @@ InitSmmProfileInternal (
mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mMaxNumberOfCpus); mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mMaxNumberOfCpus);
ASSERT (mPFEntryCount != NULL); ASSERT (mPFEntryCount != NULL);
mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool ( mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus); sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus
);
ASSERT (mLastPFEntryValue != NULL); ASSERT (mLastPFEntryValue != NULL);
mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool ( mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus); sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus
);
ASSERT (mLastPFEntryPointer != NULL); ASSERT (mLastPFEntryPointer != NULL);
// //
@@ -900,8 +941,8 @@ InitSmmProfileInternal (
// Initialize SMM profile data header. // Initialize SMM profile data header.
// //
mSmmProfileBase->HeaderSize = sizeof (SMM_PROFILE_HEADER); mSmmProfileBase->HeaderSize = sizeof (SMM_PROFILE_HEADER);
mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof(SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY)); mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof (SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY));
mSmmProfileBase->MaxDataSize = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof(SMM_PROFILE_ENTRY)); mSmmProfileBase->MaxDataSize = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof (SMM_PROFILE_ENTRY));
mSmmProfileBase->CurDataEntries = 0; mSmmProfileBase->CurDataEntries = 0;
mSmmProfileBase->CurDataSize = 0; mSmmProfileBase->CurDataSize = 0;
mSmmProfileBase->TsegStart = mCpuHotPlugData.SmrrBase; mSmmProfileBase->TsegStart = mCpuHotPlugData.SmrrBase;
@@ -919,20 +960,20 @@ InitSmmProfileInternal (
mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize); mMsrDsAreaBase = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize);
MsrDsAreaSizePerCpu = mMsrDsAreaSize / mMaxNumberOfCpus; MsrDsAreaSizePerCpu = mMsrDsAreaSize / mMaxNumberOfCpus;
mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof(MSR_DS_AREA_STRUCT)) / sizeof(BRANCH_TRACE_RECORD); mBTSRecordNumber = (MsrDsAreaSizePerCpu - sizeof (PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof (MSR_DS_AREA_STRUCT)) / sizeof (BRANCH_TRACE_RECORD);
for (Index = 0; Index < mMaxNumberOfCpus; Index++) { for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
mMsrDsArea[Index] = (MSR_DS_AREA_STRUCT *)((UINTN)mMsrDsAreaBase + MsrDsAreaSizePerCpu * Index); mMsrDsArea[Index] = (MSR_DS_AREA_STRUCT *)((UINTN)mMsrDsAreaBase + MsrDsAreaSizePerCpu * Index);
mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof(MSR_DS_AREA_STRUCT)); mMsrBTSRecord[Index] = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof (MSR_DS_AREA_STRUCT));
mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER); mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof (PEBS_RECORD) * PEBS_RECORD_NUMBER);
mMsrDsArea[Index]->BTSBufferBase = (UINTN)mMsrBTSRecord[Index]; mMsrDsArea[Index]->BTSBufferBase = (UINTN)mMsrBTSRecord[Index];
mMsrDsArea[Index]->BTSIndex = mMsrDsArea[Index]->BTSBufferBase; mMsrDsArea[Index]->BTSIndex = mMsrDsArea[Index]->BTSBufferBase;
mMsrDsArea[Index]->BTSAbsoluteMaximum = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof(BRANCH_TRACE_RECORD) + 1; mMsrDsArea[Index]->BTSAbsoluteMaximum = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof (BRANCH_TRACE_RECORD) + 1;
mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1; mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1;
mMsrDsArea[Index]->PEBSBufferBase = (UINTN)mMsrPEBSRecord[Index]; mMsrDsArea[Index]->PEBSBufferBase = (UINTN)mMsrPEBSRecord[Index];
mMsrDsArea[Index]->PEBSIndex = mMsrDsArea[Index]->PEBSBufferBase; mMsrDsArea[Index]->PEBSIndex = mMsrDsArea[Index]->PEBSBufferBase;
mMsrDsArea[Index]->PEBSAbsoluteMaximum = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof(PEBS_RECORD) + 1; mMsrDsArea[Index]->PEBSAbsoluteMaximum = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof (PEBS_RECORD) + 1;
mMsrDsArea[Index]->PEBSInterruptThreshold = mMsrDsArea[Index]->PEBSAbsoluteMaximum + 1; mMsrDsArea[Index]->PEBSInterruptThreshold = mMsrDsArea[Index]->PEBSAbsoluteMaximum + 1;
} }
} }
@@ -967,7 +1008,7 @@ InitSmmProfileInternal (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return ; return;
} }
/** /**
@@ -1062,6 +1103,7 @@ ActivateSingleStepDB (
if ((Dr6 & DR6_SINGLE_STEP) != 0) { if ((Dr6 & DR6_SINGLE_STEP) != 0) {
return; return;
} }
Dr6 |= DR6_SINGLE_STEP; Dr6 |= DR6_SINGLE_STEP;
AsmWriteDr6 (Dr6); AsmWriteDr6 (Dr6);
} }
@@ -1079,8 +1121,9 @@ ActivateLBR (
DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL); DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);
if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) { if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {
return ; return;
} }
DebugCtl |= MSR_DEBUG_CTL_LBR; DebugCtl |= MSR_DEBUG_CTL_LBR;
AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl); AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);
} }
@@ -1100,7 +1143,7 @@ ActivateBTS (
DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL); DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);
if ((DebugCtl & MSR_DEBUG_CTL_BTS) != 0) { if ((DebugCtl & MSR_DEBUG_CTL_BTS) != 0) {
return ; return;
} }
AsmWriteMsr64 (MSR_DS_AREA, (UINT64)(UINTN)mMsrDsArea[CpuIndex]); AsmWriteMsr64 (MSR_DS_AREA, (UINT64)(UINTN)mMsrDsArea[CpuIndex]);
@@ -1173,7 +1216,8 @@ InitSmmProfile (
// //
if (!FeaturePcdGet (PcdCpuSmmProfileEnable) && if (!FeaturePcdGet (PcdCpuSmmProfileEnable) &&
!HEAP_GUARD_NONSTOP_MODE && !HEAP_GUARD_NONSTOP_MODE &&
!NULL_DETECTION_NONSTOP_MODE) { !NULL_DETECTION_NONSTOP_MODE)
{
return; return;
} }
@@ -1218,7 +1262,7 @@ RestorePageTableBelow4G (
BOOLEAN Enable5LevelPaging; BOOLEAN Enable5LevelPaging;
Cr4.UintN = AsmReadCr4 (); Cr4.UintN = AsmReadCr4 ();
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
// //
// PML5 // PML5
@@ -1226,16 +1270,16 @@ RestorePageTableBelow4G (
if (Enable5LevelPaging) { if (Enable5LevelPaging) {
PTIndex = (UINTN)BitFieldRead64 (PFAddress, 48, 56); PTIndex = (UINTN)BitFieldRead64 (PFAddress, 48, 56);
ASSERT (PageTable[PTIndex] != 0); ASSERT (PageTable[PTIndex] != 0);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
} }
// //
// PML4 // PML4
// //
if (sizeof(UINT64) == sizeof(UINTN)) { if (sizeof (UINT64) == sizeof (UINTN)) {
PTIndex = (UINTN)BitFieldRead64 (PFAddress, 39, 47); PTIndex = (UINTN)BitFieldRead64 (PFAddress, 39, 47);
ASSERT (PageTable[PTIndex] != 0); ASSERT (PageTable[PTIndex] != 0);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
} }
// //
@@ -1243,7 +1287,7 @@ RestorePageTableBelow4G (
// //
PTIndex = (UINTN)BitFieldRead64 (PFAddress, 30, 38); PTIndex = (UINTN)BitFieldRead64 (PFAddress, 30, 38);
ASSERT (PageTable[PTIndex] != 0); ASSERT (PageTable[PTIndex] != 0);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
// //
// PD // PD
@@ -1281,7 +1325,7 @@ RestorePageTableBelow4G (
// Small page // Small page
// //
ASSERT (PageTable[PTIndex] != 0); ASSERT (PageTable[PTIndex] != 0);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK); PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);
// //
// 4K PTE // 4K PTE
@@ -1411,13 +1455,14 @@ SmmProfilePFHandler (
} else { } else {
RestorePageTableAbove4G (PageTable, RestoreAddress, CpuIndex, ErrorCode, &IsValidPFAddress); RestorePageTableAbove4G (PageTable, RestoreAddress, CpuIndex, ErrorCode, &IsValidPFAddress);
} }
RestoreAddress += EFI_PAGE_SIZE; RestoreAddress += EFI_PAGE_SIZE;
RestorePageNumber--; RestorePageNumber--;
} }
if (!IsValidPFAddress) { if (!IsValidPFAddress) {
InstructionAddress = Rip; InstructionAddress = Rip;
if ((ErrorCode & IA32_PF_EC_ID) != 0 && (mBtsSupported)) { if (((ErrorCode & IA32_PF_EC_ID) != 0) && (mBtsSupported)) {
// //
// If it is instruction fetch failure, get the correct IP from BTS. // If it is instruction fetch failure, get the correct IP from BTS.
// //
@@ -1436,10 +1481,11 @@ SmmProfilePFHandler (
// //
SmiCommand = 0xFFFFFFFFFFFFFFFFULL; SmiCommand = 0xFFFFFFFFFFFFFFFFULL;
for (Index = 0; Index < gSmst->NumberOfCpus; Index++) { for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
Status = SmmReadSaveState(&mSmmCpu, sizeof(IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo); Status = SmmReadSaveState (&mSmmCpu, sizeof (IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
continue; continue;
} }
if (IoInfo.IoPort == mSmiCommandPort) { if (IoInfo.IoPort == mSmiCommandPort) {
// //
// A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port. // A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.
@@ -1454,24 +1500,27 @@ SmmProfilePFHandler (
// //
// Check if there is already a same entry in profile data. // Check if there is already a same entry in profile data.
// //
for (Index = 0; Index < (UINTN) mSmmProfileBase->CurDataEntries; Index++) { for (Index = 0; Index < (UINTN)mSmmProfileBase->CurDataEntries; Index++) {
if ((SmmProfileEntry[Index].ErrorCode == (UINT64)ErrorCode) && if ((SmmProfileEntry[Index].ErrorCode == (UINT64)ErrorCode) &&
(SmmProfileEntry[Index].Address == PFAddress) && (SmmProfileEntry[Index].Address == PFAddress) &&
(SmmProfileEntry[Index].CpuNum == (UINT64)CpuIndex) && (SmmProfileEntry[Index].CpuNum == (UINT64)CpuIndex) &&
(SmmProfileEntry[Index].Instruction == InstructionAddress) && (SmmProfileEntry[Index].Instruction == InstructionAddress) &&
(SmmProfileEntry[Index].SmiCmd == SmiCommand)) { (SmmProfileEntry[Index].SmiCmd == SmiCommand))
{
// //
// Same record exist, need not save again. // Same record exist, need not save again.
// //
break; break;
} }
} }
if (Index == mSmmProfileBase->CurDataEntries) { if (Index == mSmmProfileBase->CurDataEntries) {
CurrentEntryNumber = (UINTN) mSmmProfileBase->CurDataEntries; CurrentEntryNumber = (UINTN)mSmmProfileBase->CurDataEntries;
MaxEntryNumber = (UINTN) mSmmProfileBase->MaxDataEntries; MaxEntryNumber = (UINTN)mSmmProfileBase->MaxDataEntries;
if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer)) { if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer)) {
CurrentEntryNumber = CurrentEntryNumber % MaxEntryNumber; CurrentEntryNumber = CurrentEntryNumber % MaxEntryNumber;
} }
if (CurrentEntryNumber < MaxEntryNumber) { if (CurrentEntryNumber < MaxEntryNumber) {
// //
// Log the new entry // Log the new entry
@@ -1491,6 +1540,7 @@ SmmProfilePFHandler (
} }
} }
} }
// //
// Flush TLB // Flush TLB
// //

1
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
View File

@@ -80,7 +80,6 @@ PageFaultIdtHandlerSmmProfile (
VOID VOID
); );
/** /**
Check if feature is supported by a processor. Check if feature is supported by a processor.

127
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
View File

@@ -116,7 +116,7 @@ CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO), SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP), SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4), SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
{ (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 } { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0}
}; };
/// ///
@@ -124,58 +124,58 @@ CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
/// supported EFI_SMM_SAVE_STATE_REGISTER value /// supported EFI_SMM_SAVE_STATE_REGISTER value
/// ///
CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = { CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
{0, 0, 0, 0, 0, FALSE}, // Reserved { 0, 0, 0, 0, 0, FALSE }, // Reserved
// //
// Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol. // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
// //
{4, 4, SMM_CPU_OFFSET (x86.SMMRevId) , SMM_CPU_OFFSET (x64.SMMRevId) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1 { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), 0, FALSE }, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
{4, 4, SMM_CPU_OFFSET (x86.IOMisc) , SMM_CPU_OFFSET (x64.IOMisc) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2 { 4, 4, SMM_CPU_OFFSET (x86.IOMisc), SMM_CPU_OFFSET (x64.IOMisc), 0, FALSE }, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2
{4, 8, SMM_CPU_OFFSET (x86.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE}, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3 { 4, 8, SMM_CPU_OFFSET (x86.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE }, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3
// //
// CPU Save State registers defined in PI SMM CPU Protocol. // CPU Save State registers defined in PI SMM CPU Protocol.
// //
{0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4 { 0, 8, 0, SMM_CPU_OFFSET (x64.GdtBaseLoDword), SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
{0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5 { 0, 8, 0, SMM_CPU_OFFSET (x64.IdtBaseLoDword), SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
{0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6 { 0, 8, 0, SMM_CPU_OFFSET (x64.LdtBaseLoDword), SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7 { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8 { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9 { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10 { 0, 0, 0, 0, 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
{4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20 { 4, 4, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
{4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21 { 4, 4, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
{4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22 { 4, 4, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
{4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23 { 4, 4, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
{4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24 { 4, 4, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
{4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25 { 4, 4, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
{0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26 { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTR), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
{4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27 { 4, 4, SMM_CPU_OFFSET (x86._TR), SMM_CPU_OFFSET (x64._TR), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
{4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28 { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), SMM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
{4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29 { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), SMM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
{0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30 { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
{0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31 { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
{0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32 { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
{0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33 { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
{0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34 { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
{0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35 { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
{0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36 { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
{0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37 { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
{4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38 { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
{4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39 { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
{4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40 { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
{4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41 { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
{4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42 { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
{4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43 { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
{4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44 { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
{4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45 { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
{4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46 { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
{4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51 { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
{4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52 { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), SMM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
{4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53 { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), SMM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
{0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54 { 0, 4, 0, SMM_CPU_OFFSET (x64._CR4), 0, FALSE }, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
}; };
/// ///
@@ -237,11 +237,13 @@ GetRegisterIndex (
UINTN Offset; UINTN Offset;
for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) { for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) { if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) {
return Register - mSmmCpuRegisterRanges[Index].Start + Offset; return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
} }
Offset += mSmmCpuRegisterRanges[Index].Length; Offset += mSmmCpuRegisterRanges[Index].Length;
} }
return 0; return 0;
} }
@@ -297,8 +299,8 @@ ReadSaveStateRegisterByIndex (
// //
// Write return buffer // Write return buffer
// //
ASSERT(CpuSaveState != NULL); ASSERT (CpuSaveState != NULL);
CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width); CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
} else { } else {
// //
// If 64-bit mode width is zero, then the specified register can not be accessed // If 64-bit mode width is zero, then the specified register can not be accessed
@@ -317,14 +319,15 @@ ReadSaveStateRegisterByIndex (
// //
// Write at most 4 of the lower bytes of the return buffer // Write at most 4 of the lower bytes of the return buffer
// //
CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width)); CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));
if (Width > 4) { if (Width > 4) {
// //
// Write at most 4 of the upper bytes of the return buffer // Write at most 4 of the upper bytes of the return buffer
// //
CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4); CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -382,7 +385,7 @@ ReadSaveStateRegister (
// //
// Get SMM Revision ID // Get SMM Revision ID
// //
ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof(SmmRevId), &SmmRevId); ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);
// //
// See if the CPU supports the IOMisc register in the save state // See if the CPU supports the IOMisc register in the save state
@@ -394,7 +397,7 @@ ReadSaveStateRegister (
// //
// Get the IOMisc register value // Get the IOMisc register value
// //
ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof(IoMisc.Uint32), &IoMisc.Uint32); ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32);
// //
// Check for the SMI_FLAG in IOMisc // Check for the SMI_FLAG in IOMisc
@@ -407,14 +410,15 @@ ReadSaveStateRegister (
// Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS. // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS.
// //
if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) && if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) &&
(mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) { (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT))
{
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
// //
// Compute index for the I/O Length and I/O Type lookup tables // Compute index for the I/O Length and I/O Type lookup tables
// //
if (mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0 || mSmmCpuIoType[IoMisc.Bits.Type] == 0) { if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) {
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
@@ -429,7 +433,7 @@ ReadSaveStateRegister (
// Zero the IoInfo structure that will be returned in Buffer // Zero the IoInfo structure that will be returned in Buffer
// //
IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer; IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;
ZeroMem (IoInfo, sizeof(EFI_SMM_SAVE_STATE_IO_INFO)); ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO));
// //
// Use lookup tables to help fill in all the fields of the IoInfo structure // Use lookup tables to help fill in all the fields of the IoInfo structure
@@ -525,11 +529,12 @@ WriteSaveStateRegister (
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
// //
// Write SMM State register // Write SMM State register
// //
ASSERT (CpuSaveState != NULL); ASSERT (CpuSaveState != NULL);
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width); CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
} else { } else {
// //
// If 64-bit mode width is zero, then the specified register can not be accessed // If 64-bit mode width is zero, then the specified register can not be accessed
@@ -548,14 +553,15 @@ WriteSaveStateRegister (
// //
// Write at most 4 of the lower bytes of SMM State register // Write at most 4 of the lower bytes of SMM State register
// //
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width)); CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
if (Width > 4) { if (Width > 4) {
// //
// Write at most 4 of the upper bytes of SMM State register // Write at most 4 of the upper bytes of SMM State register
// //
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4); CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -615,6 +621,7 @@ HookReturnFromSmm (
} else { } else {
CpuState->x64._RIP = (UINT32)NewInstructionPointer; CpuState->x64._RIP = (UINT32)NewInstructionPointer;
} }
// //
// Clear the auto HALT restart flag so the RSM instruction returns // Clear the auto HALT restart flag so the RSM instruction returns
// program control to the instruction following the HLT instruction. // program control to the instruction following the HLT instruction.
@@ -623,6 +630,7 @@ HookReturnFromSmm (
CpuState->x64.AutoHALTRestart &= ~BIT0; CpuState->x64.AutoHALTRestart &= ~BIT0;
} }
} }
return OriginalInstructionPointer; return OriginalInstructionPointer;
} }
@@ -644,6 +652,7 @@ GetSmiHandlerSize (
if (Size != 0) { if (Size != 0) {
return Size; return Size;
} }
return gcSmiHandlerSize; return gcSmiHandlerSize;
} }
@@ -729,14 +738,14 @@ InstallSmiHandler (
// //
// Set the value at the top of the CPU stack to the CPU Index // Set the value at the top of the CPU stack to the CPU Index
// //
*(UINTN*)(UINTN)CpuSmiStack = CpuIndex; *(UINTN *)(UINTN)CpuSmiStack = CpuIndex;
// //
// Copy template to CPU specific SMI handler location // Copy template to CPU specific SMI handler location
// //
CopyMem ( CopyMem (
(VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET), (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET),
(VOID*)gcSmiHandlerTemplate, (VOID *)gcSmiHandlerTemplate,
gcSmiHandlerSize gcSmiHandlerSize
); );
} }

5
UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c
View File

@@ -33,7 +33,7 @@ InitializeSmmTimer (
TimerFrequency = GetPerformanceCounterProperties (&Start, &End); TimerFrequency = GetPerformanceCounterProperties (&Start, &End);
mTimeoutTicker = DivU64x32 ( mTimeoutTicker = DivU64x32 (
MultU64x64(TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)), MultU64x64 (TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)),
1000 * 1000 1000 * 1000
); );
if (End < Start) { if (End < Start) {
@@ -58,7 +58,6 @@ StartSyncTimer (
return GetPerformanceCounter (); return GetPerformanceCounter ();
} }
/** /**
Check if the SMM AP Sync timer is timeout. Check if the SMM AP Sync timer is timeout.
@@ -106,5 +105,5 @@ IsSyncTimerTimeout (
} }
} }
return (BOOLEAN) (Delta >= mTimeoutTicker); return (BOOLEAN)(Delta >= mTimeoutTicker);
} }

207
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
View File

@@ -61,6 +61,7 @@ Is1GPageSupport (
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }
@@ -88,14 +89,20 @@ Is5LevelPagingNeeded (
} else { } else {
VirPhyAddressSize.Bits.PhysicalAddressBits = 36; VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
NULL, NULL, &ExtFeatureEcx.Uint32, NULL NULL,
NULL,
&ExtFeatureEcx.Uint32,
NULL
); );
DEBUG (( DEBUG ((
DEBUG_INFO, "PhysicalAddressBits = %d, 5LPageTable = %d.\n", DEBUG_INFO,
VirPhyAddressSize.Bits.PhysicalAddressBits, ExtFeatureEcx.Bits.FiveLevelPage "PhysicalAddressBits = %d, 5LPageTable = %d.\n",
VirPhyAddressSize.Bits.PhysicalAddressBits,
ExtFeatureEcx.Bits.FiveLevelPage
)); ));
if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) { if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) {
@@ -126,6 +133,7 @@ GetPageTable (
Cr4.UintN = AsmReadCr4 (); Cr4.UintN = AsmReadCr4 ();
*FiveLevels = (BOOLEAN)(Cr4.Bits.LA57 == 1); *FiveLevels = (BOOLEAN)(Cr4.Bits.LA57 == 1);
} }
return; return;
} }
@@ -195,16 +203,17 @@ CalculateMaximumSupportAddress (
// //
Hob = GetFirstHob (EFI_HOB_TYPE_CPU); Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
if (Hob != NULL) { if (Hob != NULL) {
PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace; PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else { } else {
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) { if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax; PhysicalAddressBits = (UINT8)RegEax;
} else { } else {
PhysicalAddressBits = 36; PhysicalAddressBits = 36;
} }
} }
return PhysicalAddressBits; return PhysicalAddressBits;
} }
@@ -240,30 +249,30 @@ SetStaticPageTable (
// when 5-Level Paging is disabled. // when 5-Level Paging is disabled.
// //
ASSERT (PhysicalAddressBits <= 52); ASSERT (PhysicalAddressBits <= 52);
if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) { if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) {
PhysicalAddressBits = 48; PhysicalAddressBits = 48;
} }
NumberOfPml5EntriesNeeded = 1; NumberOfPml5EntriesNeeded = 1;
if (PhysicalAddressBits > 48) { if (PhysicalAddressBits > 48) {
NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 48); NumberOfPml5EntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 48);
PhysicalAddressBits = 48; PhysicalAddressBits = 48;
} }
NumberOfPml4EntriesNeeded = 1; NumberOfPml4EntriesNeeded = 1;
if (PhysicalAddressBits > 39) { if (PhysicalAddressBits > 39) {
NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 39); NumberOfPml4EntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 39);
PhysicalAddressBits = 39; PhysicalAddressBits = 39;
} }
NumberOfPdpEntriesNeeded = 1; NumberOfPdpEntriesNeeded = 1;
ASSERT (PhysicalAddressBits > 30); ASSERT (PhysicalAddressBits > 30);
NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 30); NumberOfPdpEntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 30);
// //
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it. // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
// //
PageMap = (VOID *) PageTable; PageMap = (VOID *)PageTable;
PageMapLevel4Entry = PageMap; PageMapLevel4Entry = PageMap;
PageMapLevel5Entry = NULL; PageMapLevel5Entry = NULL;
@@ -273,22 +282,24 @@ SetStaticPageTable (
// //
PageMapLevel5Entry = PageMap; PageMapLevel5Entry = PageMap;
} }
PageAddress = 0; PageAddress = 0;
for ( IndexOfPml5Entries = 0 for ( IndexOfPml5Entries = 0
; IndexOfPml5Entries < NumberOfPml5EntriesNeeded ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded
; IndexOfPml5Entries++, PageMapLevel5Entry++) { ; IndexOfPml5Entries++, PageMapLevel5Entry++)
{
// //
// Each PML5 entry points to a page of PML4 entires. // Each PML5 entry points to a page of PML4 entires.
// So lets allocate space for them and fill them in in the IndexOfPml4Entries loop. // So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.
// When 5-Level Paging is disabled, below allocation happens only once. // When 5-Level Paging is disabled, below allocation happens only once.
// //
if (m5LevelPagingNeeded) { if (m5LevelPagingNeeded) {
PageMapLevel4Entry = (UINT64 *) ((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask); PageMapLevel4Entry = (UINT64 *)((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask);
if (PageMapLevel4Entry == NULL) { if (PageMapLevel4Entry == NULL) {
PageMapLevel4Entry = AllocatePageTableMemory (1); PageMapLevel4Entry = AllocatePageTableMemory (1);
ASSERT(PageMapLevel4Entry != NULL); ASSERT (PageMapLevel4Entry != NULL);
ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE(1)); ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE (1));
*PageMapLevel5Entry = (UINT64)(UINTN)PageMapLevel4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; *PageMapLevel5Entry = (UINT64)(UINTN)PageMapLevel4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
} }
@@ -298,11 +309,11 @@ SetStaticPageTable (
// //
// Each PML4 entry points to a page of Page Directory Pointer entries. // Each PML4 entry points to a page of Page Directory Pointer entries.
// //
PageDirectoryPointerEntry = (UINT64 *) ((*PageMapLevel4Entry) & ~mAddressEncMask & gPhyMask); PageDirectoryPointerEntry = (UINT64 *)((*PageMapLevel4Entry) & ~mAddressEncMask & gPhyMask);
if (PageDirectoryPointerEntry == NULL) { if (PageDirectoryPointerEntry == NULL) {
PageDirectoryPointerEntry = AllocatePageTableMemory (1); PageDirectoryPointerEntry = AllocatePageTableMemory (1);
ASSERT(PageDirectoryPointerEntry != NULL); ASSERT (PageDirectoryPointerEntry != NULL);
ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE(1)); ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE (1));
*PageMapLevel4Entry = (UINT64)(UINTN)PageDirectoryPointerEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; *PageMapLevel4Entry = (UINT64)(UINTN)PageDirectoryPointerEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
} }
@@ -310,12 +321,13 @@ SetStaticPageTable (
if (m1GPageTableSupport) { if (m1GPageTableSupport) {
PageDirectory1GEntry = PageDirectoryPointerEntry; PageDirectory1GEntry = PageDirectoryPointerEntry;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) { for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
if (IndexOfPml4Entries == 0 && IndexOfPageDirectoryEntries < 4) { if ((IndexOfPml4Entries == 0) && (IndexOfPageDirectoryEntries < 4)) {
// //
// Skip the < 4G entries // Skip the < 4G entries
// //
continue; continue;
} }
// //
// Fill in the Page Directory entries // Fill in the Page Directory entries
// //
@@ -324,21 +336,22 @@ SetStaticPageTable (
} else { } else {
PageAddress = BASE_4GB; PageAddress = BASE_4GB;
for (IndexOfPdpEntries = 0; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++, PageDirectoryPointerEntry++) { for (IndexOfPdpEntries = 0; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
if (IndexOfPml4Entries == 0 && IndexOfPdpEntries < 4) { if ((IndexOfPml4Entries == 0) && (IndexOfPdpEntries < 4)) {
// //
// Skip the < 4G entries // Skip the < 4G entries
// //
continue; continue;
} }
// //
// Each Directory Pointer entries points to a page of Page Directory entires. // Each Directory Pointer entries points to a page of Page Directory entires.
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop. // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
// //
PageDirectoryEntry = (UINT64 *) ((*PageDirectoryPointerEntry) & ~mAddressEncMask & gPhyMask); PageDirectoryEntry = (UINT64 *)((*PageDirectoryPointerEntry) & ~mAddressEncMask & gPhyMask);
if (PageDirectoryEntry == NULL) { if (PageDirectoryEntry == NULL) {
PageDirectoryEntry = AllocatePageTableMemory (1); PageDirectoryEntry = AllocatePageTableMemory (1);
ASSERT(PageDirectoryEntry != NULL); ASSERT (PageDirectoryEntry != NULL);
ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE(1)); ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE (1));
// //
// Fill in a Page Directory Pointer Entries // Fill in a Page Directory Pointer Entries
@@ -401,7 +414,7 @@ SmmInitPageTable (
// //
// Set IA32_PG_PMNT bit to mask this entry // Set IA32_PG_PMNT bit to mask this entry
// //
PTEntry = (UINT64*)(UINTN)Pages; PTEntry = (UINT64 *)(UINTN)Pages;
for (Index = 0; Index < 4; Index++) { for (Index = 0; Index < 4; Index++) {
PTEntry[Index] |= IA32_PG_PMNT; PTEntry[Index] |= IA32_PG_PMNT;
} }
@@ -409,7 +422,7 @@ SmmInitPageTable (
// //
// Fill Page-Table-Level4 (PML4) entry // Fill Page-Table-Level4 (PML4) entry
// //
Pml4Entry = (UINT64*)AllocatePageTableMemory (1); Pml4Entry = (UINT64 *)AllocatePageTableMemory (1);
ASSERT (Pml4Entry != NULL); ASSERT (Pml4Entry != NULL);
*Pml4Entry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS; *Pml4Entry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry)); ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry));
@@ -424,9 +437,9 @@ SmmInitPageTable (
// //
// Fill PML5 entry // Fill PML5 entry
// //
Pml5Entry = (UINT64*)AllocatePageTableMemory (1); Pml5Entry = (UINT64 *)AllocatePageTableMemory (1);
ASSERT (Pml5Entry != NULL); ASSERT (Pml5Entry != NULL);
*Pml5Entry = (UINTN) Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS; *Pml5Entry = (UINTN)Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry)); ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry));
// //
// Set sub-entries number // Set sub-entries number
@@ -445,7 +458,7 @@ SmmInitPageTable (
// //
// Add pages to page pool // Add pages to page pool
// //
FreePage = (LIST_ENTRY*)AllocatePageTableMemory (PAGE_TABLE_PAGES); FreePage = (LIST_ENTRY *)AllocatePageTableMemory (PAGE_TABLE_PAGES);
ASSERT (FreePage != NULL); ASSERT (FreePage != NULL);
for (Index = 0; Index < PAGE_TABLE_PAGES; Index++) { for (Index = 0; Index < PAGE_TABLE_PAGES; Index++) {
InsertTailList (&mPagePool, FreePage); InsertTailList (&mPagePool, FreePage);
@@ -455,13 +468,14 @@ SmmInitPageTable (
if (FeaturePcdGet (PcdCpuSmmProfileEnable) || if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||
HEAP_GUARD_NONSTOP_MODE || HEAP_GUARD_NONSTOP_MODE ||
NULL_DETECTION_NONSTOP_MODE) { NULL_DETECTION_NONSTOP_MODE)
{
// //
// Set own Page Fault entry instead of the default one, because SMM Profile // Set own Page Fault entry instead of the default one, because SMM Profile
// feature depends on IRET instruction to do Single Step // feature depends on IRET instruction to do Single Step
// //
PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile; PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base; IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;
IdtEntry += EXCEPT_IA32_PAGE_FAULT; IdtEntry += EXCEPT_IA32_PAGE_FAULT;
IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress; IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
IdtEntry->Bits.Reserved_0 = 0; IdtEntry->Bits.Reserved_0 = 0;
@@ -570,6 +584,7 @@ GetAndUpdateAccNum (
SetAccNum (Entry, Acc - 1); SetAccNum (Entry, Acc - 1);
} }
} }
return Acc; return Acc;
} }
@@ -631,15 +646,15 @@ ReclaimPages (
PFAddressPdtIndex = BitFieldRead64 (PFAddress, 21, 21 + 8); PFAddressPdtIndex = BitFieldRead64 (PFAddress, 21, 21 + 8);
Cr4.UintN = AsmReadCr4 (); Cr4.UintN = AsmReadCr4 ();
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);
Pml5 = (UINT64*)(UINTN)(AsmReadCr3 () & gPhyMask); Pml5 = (UINT64 *)(UINTN)(AsmReadCr3 () & gPhyMask);
if (!Enable5LevelPaging) { if (!Enable5LevelPaging) {
// //
// Create one fake PML5 entry for 4-Level Paging // Create one fake PML5 entry for 4-Level Paging
// so that the page table parsing logic only handles 5-Level page structure. // so that the page table parsing logic only handles 5-Level page structure.
// //
Pml5Entry = (UINTN) Pml5 | IA32_PG_P; Pml5Entry = (UINTN)Pml5 | IA32_PG_P;
Pml5 = &Pml5Entry; Pml5 = &Pml5Entry;
} }
@@ -647,24 +662,26 @@ ReclaimPages (
// First, find the leaf entry has the smallest access record value // First, find the leaf entry has the smallest access record value
// //
for (Pml5Index = 0; Pml5Index < (Enable5LevelPaging ? (EFI_PAGE_SIZE / sizeof (*Pml4)) : 1); Pml5Index++) { for (Pml5Index = 0; Pml5Index < (Enable5LevelPaging ? (EFI_PAGE_SIZE / sizeof (*Pml4)) : 1); Pml5Index++) {
if ((Pml5[Pml5Index] & IA32_PG_P) == 0 || (Pml5[Pml5Index] & IA32_PG_PMNT) != 0) { if (((Pml5[Pml5Index] & IA32_PG_P) == 0) || ((Pml5[Pml5Index] & IA32_PG_PMNT) != 0)) {
// //
// If the PML5 entry is not present or is masked, skip it // If the PML5 entry is not present or is masked, skip it
// //
continue; continue;
} }
Pml4 = (UINT64*)(UINTN)(Pml5[Pml5Index] & gPhyMask);
Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & gPhyMask);
for (Pml4Index = 0; Pml4Index < EFI_PAGE_SIZE / sizeof (*Pml4); Pml4Index++) { for (Pml4Index = 0; Pml4Index < EFI_PAGE_SIZE / sizeof (*Pml4); Pml4Index++) {
if ((Pml4[Pml4Index] & IA32_PG_P) == 0 || (Pml4[Pml4Index] & IA32_PG_PMNT) != 0) { if (((Pml4[Pml4Index] & IA32_PG_P) == 0) || ((Pml4[Pml4Index] & IA32_PG_PMNT) != 0)) {
// //
// If the PML4 entry is not present or is masked, skip it // If the PML4 entry is not present or is masked, skip it
// //
continue; continue;
} }
Pdpt = (UINT64*)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask);
Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask);
PML4EIgnore = FALSE; PML4EIgnore = FALSE;
for (PdptIndex = 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); PdptIndex++) { for (PdptIndex = 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); PdptIndex++) {
if ((Pdpt[PdptIndex] & IA32_PG_P) == 0 || (Pdpt[PdptIndex] & IA32_PG_PMNT) != 0) { if (((Pdpt[PdptIndex] & IA32_PG_P) == 0) || ((Pdpt[PdptIndex] & IA32_PG_PMNT) != 0)) {
// //
// If the PDPT entry is not present or is masked, skip it // If the PDPT entry is not present or is masked, skip it
// //
@@ -674,18 +691,20 @@ ReclaimPages (
// //
PML4EIgnore = TRUE; PML4EIgnore = TRUE;
} }
continue; continue;
} }
if ((Pdpt[PdptIndex] & IA32_PG_PS) == 0) { if ((Pdpt[PdptIndex] & IA32_PG_PS) == 0) {
// //
// It's not 1-GByte pages entry, it should be a PDPT entry, // It's not 1-GByte pages entry, it should be a PDPT entry,
// we will not check PML4 entry more // we will not check PML4 entry more
// //
PML4EIgnore = TRUE; PML4EIgnore = TRUE;
Pdt = (UINT64*)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask); Pdt = (UINT64 *)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask);
PDPTEIgnore = FALSE; PDPTEIgnore = FALSE;
for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof(*Pdt); PdtIndex++) { for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof (*Pdt); PdtIndex++) {
if ((Pdt[PdtIndex] & IA32_PG_P) == 0 || (Pdt[PdtIndex] & IA32_PG_PMNT) != 0) { if (((Pdt[PdtIndex] & IA32_PG_P) == 0) || ((Pdt[PdtIndex] & IA32_PG_PMNT) != 0)) {
// //
// If the PD entry is not present or is masked, skip it // If the PD entry is not present or is masked, skip it
// //
@@ -695,16 +714,19 @@ ReclaimPages (
// //
PDPTEIgnore = TRUE; PDPTEIgnore = TRUE;
} }
continue; continue;
} }
if ((Pdt[PdtIndex] & IA32_PG_PS) == 0) { if ((Pdt[PdtIndex] & IA32_PG_PS) == 0) {
// //
// It's not 2 MByte page table entry, it should be PD entry // It's not 2 MByte page table entry, it should be PD entry
// we will find the entry has the smallest access record value // we will find the entry has the smallest access record value
// //
PDPTEIgnore = TRUE; PDPTEIgnore = TRUE;
if (PdtIndex != PFAddressPdtIndex || PdptIndex != PFAddressPdptIndex || if ((PdtIndex != PFAddressPdtIndex) || (PdptIndex != PFAddressPdptIndex) ||
Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) { (Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index))
{
Acc = GetAndUpdateAccNum (Pdt + PdtIndex); Acc = GetAndUpdateAccNum (Pdt + PdtIndex);
if (Acc < MinAcc) { if (Acc < MinAcc) {
// //
@@ -721,13 +743,15 @@ ReclaimPages (
} }
} }
} }
if (!PDPTEIgnore) { if (!PDPTEIgnore) {
// //
// If this PDPT entry has no PDT entries pointer to 4 KByte pages, // If this PDPT entry has no PDT entries pointer to 4 KByte pages,
// it should only has the entries point to 2 MByte Pages // it should only has the entries point to 2 MByte Pages
// //
if (PdptIndex != PFAddressPdptIndex || Pml4Index != PFAddressPml4Index || if ((PdptIndex != PFAddressPdptIndex) || (Pml4Index != PFAddressPml4Index) ||
Pml5Index != PFAddressPml5Index) { (Pml5Index != PFAddressPml5Index))
{
Acc = GetAndUpdateAccNum (Pdpt + PdptIndex); Acc = GetAndUpdateAccNum (Pdpt + PdptIndex);
if (Acc < MinAcc) { if (Acc < MinAcc) {
// //
@@ -745,12 +769,13 @@ ReclaimPages (
} }
} }
} }
if (!PML4EIgnore) { if (!PML4EIgnore) {
// //
// If PML4 entry has no the PDPT entry pointer to 2 MByte pages, // If PML4 entry has no the PDPT entry pointer to 2 MByte pages,
// it should only has the entries point to 1 GByte Pages // it should only has the entries point to 1 GByte Pages
// //
if (Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) { if ((Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index)) {
Acc = GetAndUpdateAccNum (Pml4 + Pml4Index); Acc = GetAndUpdateAccNum (Pml4 + Pml4Index);
if (Acc < MinAcc) { if (Acc < MinAcc) {
// //
@@ -768,6 +793,7 @@ ReclaimPages (
} }
} }
} }
// //
// Make sure one PML4/PDPT/PD entry is selected // Make sure one PML4/PDPT/PD entry is selected
// //
@@ -776,7 +802,7 @@ ReclaimPages (
// //
// Secondly, insert the page pointed by this entry into page pool and clear this entry // Secondly, insert the page pointed by this entry into page pool and clear this entry
// //
InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress & ~mAddressEncMask & gPhyMask)); InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(*ReleasePageAddress & ~mAddressEncMask & gPhyMask));
*ReleasePageAddress = 0; *ReleasePageAddress = 0;
// //
@@ -788,16 +814,17 @@ ReclaimPages (
// //
// If 4 KByte Page Table is released, check the PDPT entry // If 4 KByte Page Table is released, check the PDPT entry
// //
Pml4 = (UINT64 *) (UINTN) (Pml5[MinPml5] & gPhyMask); Pml4 = (UINT64 *)(UINTN)(Pml5[MinPml5] & gPhyMask);
Pdpt = (UINT64*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask); Pdpt = (UINT64 *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask);
SubEntriesNum = GetSubEntriesNum(Pdpt + MinPdpt); SubEntriesNum = GetSubEntriesNum (Pdpt + MinPdpt);
if (SubEntriesNum == 0 && if ((SubEntriesNum == 0) &&
(MinPdpt != PFAddressPdptIndex || MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) { ((MinPdpt != PFAddressPdptIndex) || (MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index)))
{
// //
// Release the empty Page Directory table if there was no more 4 KByte Page Table entry // Release the empty Page Directory table if there was no more 4 KByte Page Table entry
// clear the Page directory entry // clear the Page directory entry
// //
InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt] & ~mAddressEncMask & gPhyMask)); InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(Pdpt[MinPdpt] & ~mAddressEncMask & gPhyMask));
Pdpt[MinPdpt] = 0; Pdpt[MinPdpt] = 0;
// //
// Go on checking the PML4 table // Go on checking the PML4 table
@@ -805,33 +832,37 @@ ReclaimPages (
MinPdt = (UINTN)-1; MinPdt = (UINTN)-1;
continue; continue;
} }
// //
// Update the sub-entries filed in PDPT entry and exit // Update the sub-entries filed in PDPT entry and exit
// //
SetSubEntriesNum (Pdpt + MinPdpt, (SubEntriesNum - 1) & 0x1FF); SetSubEntriesNum (Pdpt + MinPdpt, (SubEntriesNum - 1) & 0x1FF);
break; break;
} }
if (MinPdpt != (UINTN)-1) { if (MinPdpt != (UINTN)-1) {
// //
// One 2MB Page Table is released or Page Directory table is released, check the PML4 entry // One 2MB Page Table is released or Page Directory table is released, check the PML4 entry
// //
SubEntriesNum = GetSubEntriesNum (Pml4 + MinPml4); SubEntriesNum = GetSubEntriesNum (Pml4 + MinPml4);
if (SubEntriesNum == 0 && (MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) { if ((SubEntriesNum == 0) && ((MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index))) {
// //
// Release the empty PML4 table if there was no more 1G KByte Page Table entry // Release the empty PML4 table if there was no more 1G KByte Page Table entry
// clear the Page directory entry // clear the Page directory entry
// //
InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask)); InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask));
Pml4[MinPml4] = 0; Pml4[MinPml4] = 0;
MinPdpt = (UINTN)-1; MinPdpt = (UINTN)-1;
continue; continue;
} }
// //
// Update the sub-entries filed in PML4 entry and exit // Update the sub-entries filed in PML4 entry and exit
// //
SetSubEntriesNum (Pml4 + MinPml4, (SubEntriesNum - 1) & 0x1FF); SetSubEntriesNum (Pml4 + MinPml4, (SubEntriesNum - 1) & 0x1FF);
break; break;
} }
// //
// PLM4 table has been released before, exit it // PLM4 table has been released before, exit it
// //
@@ -867,7 +898,7 @@ AllocPage (
// //
// Clean this page and return // Clean this page and return
// //
ZeroMem ((VOID*)(UINTN)RetVal, EFI_PAGE_SIZE); ZeroMem ((VOID *)(UINTN)RetVal, EFI_PAGE_SIZE);
return RetVal; return RetVal;
} }
@@ -903,11 +934,11 @@ SmiDefaultPFHandler (
PageAttribute = 0; PageAttribute = 0;
EndBit = 0; EndBit = 0;
PageTableTop = (UINT64*)(AsmReadCr3 () & gPhyMask); PageTableTop = (UINT64 *)(AsmReadCr3 () & gPhyMask);
PFAddress = AsmReadCr2 (); PFAddress = AsmReadCr2 ();
Cr4.UintN = AsmReadCr4 (); Cr4.UintN = AsmReadCr4 ();
Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 != 0); Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 != 0);
Status = GetPlatformPageTableAttribute (PFAddress, &PageSize, &NumOfPages, &PageAttribute); Status = GetPlatformPageTableAttribute (PFAddress, &PageSize, &NumOfPages, &PageAttribute);
// //
@@ -918,9 +949,11 @@ SmiDefaultPFHandler (
NumOfPages = 1; NumOfPages = 1;
PageAttribute = 0; PageAttribute = 0;
} }
if (PageSize >= MaxSmmPageSizeType) { if (PageSize >= MaxSmmPageSizeType) {
PageSize = SmmPageSize2M; PageSize = SmmPageSize2M;
} }
if (NumOfPages > 512) { if (NumOfPages > 512) {
NumOfPages = 512; NumOfPages = 512;
} }
@@ -944,6 +977,7 @@ SmiDefaultPFHandler (
DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!")); DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!"));
ASSERT (FALSE); ASSERT (FALSE);
} }
// //
// BIT30 to BIT38 is Page Directory Pointer Table index // BIT30 to BIT38 is Page Directory Pointer Table index
// //
@@ -977,13 +1011,14 @@ SmiDefaultPFHandler (
// //
UpperEntry = PageTable + PTIndex; UpperEntry = PageTable + PTIndex;
} }
// //
// BIT9 to BIT11 of entry is used to save access record, // BIT9 to BIT11 of entry is used to save access record,
// initialize value is 7 // initialize value is 7
// //
PageTable[PTIndex] |= (UINT64)IA32_PG_A; PageTable[PTIndex] |= (UINT64)IA32_PG_A;
SetAccNum (PageTable + PTIndex, 7); SetAccNum (PageTable + PTIndex, 7);
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & gPhyMask); PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & gPhyMask);
} }
PTIndex = BitFieldRead64 (PFAddress, StartBit, StartBit + 8); PTIndex = BitFieldRead64 (PFAddress, StartBit, StartBit + 8);
@@ -996,6 +1031,7 @@ SmiDefaultPFHandler (
DEBUG ((DEBUG_ERROR, "New page table overlapped with old page table!\n")); DEBUG ((DEBUG_ERROR, "New page table overlapped with old page table!\n"));
ASSERT (FALSE); ASSERT (FALSE);
} }
// //
// Fill the new entry // Fill the new entry
// //
@@ -1004,6 +1040,7 @@ SmiDefaultPFHandler (
if (UpperEntry != NULL) { if (UpperEntry != NULL) {
SetSubEntriesNum (UpperEntry, (GetSubEntriesNum (UpperEntry) + 1) & 0x1FF); SetSubEntriesNum (UpperEntry, (GetSubEntriesNum (UpperEntry) + 1) & 0x1FF);
} }
// //
// Get the next page address if we need to create more page tables // Get the next page address if we need to create more page tables
// //
@@ -1049,19 +1086,22 @@ SmiPFHandler (
// or SMM page protection violation. // or SMM page protection violation.
// //
if ((PFAddress >= mCpuHotPlugData.SmrrBase) && if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) { (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))
{
DumpCpuContext (InterruptType, SystemContext); DumpCpuContext (InterruptType, SystemContext);
CpuIndex = GetCpuIndex (); CpuIndex = GetCpuIndex ();
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize)); GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));
ShadowStackGuardPageAddress = (mSmmStackArrayBase + mSmmStackSize + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize)); ShadowStackGuardPageAddress = (mSmmStackArrayBase + mSmmStackSize + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) && if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(PFAddress >= GuardPageAddress) && (PFAddress >= GuardPageAddress) &&
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) { (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))
{
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n")); DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else if ((FeaturePcdGet (PcdCpuSmmStackGuard)) && } else if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(mSmmShadowStackSize > 0) && (mSmmShadowStackSize > 0) &&
(PFAddress >= ShadowStackGuardPageAddress) && (PFAddress >= ShadowStackGuardPageAddress) &&
(PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE))) { (PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE)))
{
DEBUG ((DEBUG_ERROR, "SMM shadow stack overflow!\n")); DEBUG ((DEBUG_ERROR, "SMM shadow stack overflow!\n"));
} else { } else {
if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) { if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {
@@ -1081,6 +1121,7 @@ SmiPFHandler (
goto Exit; goto Exit;
} }
} }
CpuDeadLoop (); CpuDeadLoop ();
goto Exit; goto Exit;
} }
@@ -1089,7 +1130,8 @@ SmiPFHandler (
// If a page fault occurs in non-SMRAM range. // If a page fault occurs in non-SMRAM range.
// //
if ((PFAddress < mCpuHotPlugData.SmrrBase) || if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) { (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))
{
if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) { if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {
DumpCpuContext (InterruptType, SystemContext); DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%lx) out of SMM range after SMM is locked!\n", PFAddress)); DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%lx) out of SMM range after SMM is locked!\n", PFAddress));
@@ -1103,8 +1145,9 @@ SmiPFHandler (
// //
// If NULL pointer was just accessed // If NULL pointer was just accessed
// //
if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 && if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&
(PFAddress < EFI_PAGE_SIZE)) { (PFAddress < EFI_PAGE_SIZE))
{
DumpCpuContext (InterruptType, SystemContext); DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n")); DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));
DEBUG_CODE ( DEBUG_CODE (
@@ -1177,18 +1220,21 @@ SetPageTableAttributes (
// //
if (!mCpuSmmRestrictedMemoryAccess || if (!mCpuSmmRestrictedMemoryAccess ||
((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) || ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) ||
FeaturePcdGet (PcdCpuSmmProfileEnable)) { FeaturePcdGet (PcdCpuSmmProfileEnable))
{
// //
// Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time. // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.
// //
ASSERT (!(mCpuSmmRestrictedMemoryAccess && ASSERT (
(PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)); !(mCpuSmmRestrictedMemoryAccess &&
(PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)
);
// //
// Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time. // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.
// //
ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable))); ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable)));
return ; return;
} }
DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n")); DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));
@@ -1197,14 +1243,15 @@ SetPageTableAttributes (
// Disable write protection, because we need mark page table to be write protected. // Disable write protection, because we need mark page table to be write protected.
// We need *write* page table memory, to mark itself to be *read only*. // We need *write* page table memory, to mark itself to be *read only*.
// //
CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE; CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;
if (CetEnabled) { if (CetEnabled) {
// //
// CET must be disabled if WP is disabled. // CET must be disabled if WP is disabled.
// //
DisableCet(); DisableCet ();
} }
AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
do { do {
DEBUG ((DEBUG_INFO, "Start...\n")); DEBUG ((DEBUG_INFO, "Start...\n"));
@@ -1219,7 +1266,7 @@ SetPageTableAttributes (
PageTableSplitted = (PageTableSplitted || IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted);
} }
for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof(UINT64) : 1); Index5++) { for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof (UINT64) : 1); Index5++) {
if (Enable5LevelPaging) { if (Enable5LevelPaging) {
L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L4PageTable == NULL) { if (L4PageTable == NULL) {
@@ -1228,10 +1275,11 @@ SetPageTableAttributes (
} else { } else {
L4PageTable = (UINT64 *)PageTableBase; L4PageTable = (UINT64 *)PageTableBase;
} }
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted);
for (Index4 = 0; Index4 < SIZE_4KB/sizeof(UINT64); Index4++) { for (Index4 = 0; Index4 < SIZE_4KB/sizeof (UINT64); Index4++) {
L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L3PageTable == NULL) { if (L3PageTable == NULL) {
continue; continue;
@@ -1240,11 +1288,12 @@ SetPageTableAttributes (
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted);
for (Index3 = 0; Index3 < SIZE_4KB/sizeof(UINT64); Index3++) { for (Index3 = 0; Index3 < SIZE_4KB/sizeof (UINT64); Index3++) {
if ((L3PageTable[Index3] & IA32_PG_PS) != 0) { if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
// 1G // 1G
continue; continue;
} }
L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L2PageTable == NULL) { if (L2PageTable == NULL) {
continue; continue;
@@ -1253,15 +1302,17 @@ SetPageTableAttributes (
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted);
for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) { for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) { if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M // 2M
continue; continue;
} }
L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L1PageTable == NULL) { if (L1PageTable == NULL) {
continue; continue;
} }
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted); PageTableSplitted = (PageTableSplitted || IsSplitted);
} }
@@ -1273,15 +1324,15 @@ SetPageTableAttributes (
// //
// Enable write protection, after page table updated. // Enable write protection, after page table updated.
// //
AsmWriteCr0 (AsmReadCr0() | CR0_WP); AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
if (CetEnabled) { if (CetEnabled) {
// //
// re-enable CET. // re-enable CET.
// //
EnableCet(); EnableCet ();
} }
return ; return;
} }
/** /**

24
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
View File

@@ -72,13 +72,13 @@ InitGdt (
// //
GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned
mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;
GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize)); GdtTssTables = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));
ASSERT (GdtTssTables != NULL); ASSERT (GdtTssTables != NULL);
mGdtBuffer = (UINTN)GdtTssTables; mGdtBuffer = (UINTN)GdtTssTables;
GdtTableStepSize = GdtTssTableSize; GdtTableStepSize = GdtTssTableSize;
for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) { for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {
CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE); CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);
// //
// Fixup TSS descriptors // Fixup TSS descriptors
@@ -118,15 +118,17 @@ GetProtectedModeCS (
AsmReadGdtr (&GdtrDesc); AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) { for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) { if (GdtEntry->Bits.L == 0) {
if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) { if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {
break; break;
} }
} }
GdtEntry++; GdtEntry++;
} }
ASSERT (Index != GdtEntryCount); ASSERT (Index != GdtEntryCount);
return Index * 8; return Index * 8;
} }
@@ -188,14 +190,15 @@ InitShadowStack (
// //
SmmShadowStackSize += EFI_PAGES_TO_SIZE (1); SmmShadowStackSize += EFI_PAGES_TO_SIZE (1);
} }
mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));
mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));
PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4); PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp)); DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack)); DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));
DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize)); DEBUG ((DEBUG_INFO, " SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));
if (mSmmInterruptSspTables == 0) { if (mSmmInterruptSspTables == 0) {
mSmmInterruptSspTables = (UINTN)AllocateZeroPool(sizeof(UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus); mSmmInterruptSspTables = (UINTN)AllocateZeroPool (sizeof (UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);
ASSERT (mSmmInterruptSspTables != 0); ASSERT (mSmmInterruptSspTables != 0);
DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterruptSspTables)); DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterruptSspTables));
} }
@@ -209,11 +212,11 @@ InitShadowStack (
// Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime. // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime.
// According to SDM (ver. 075 June 2021), shadow stack should be 32 bytes aligned. // According to SDM (ver. 075 June 2021), shadow stack should be 32 bytes aligned.
// //
InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - (sizeof(UINT64) * 4)) & ~0x1f); InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - (sizeof (UINT64) * 4)) & ~0x1f);
*(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2; *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof (UINT64) * 4) | 0x2;
mCetInterruptSsp = InterruptSsp - sizeof(UINT64); mCetInterruptSsp = InterruptSsp - sizeof (UINT64);
mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex); mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof (UINT64) * 8 * CpuIndex);
InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable; InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable;
InterruptSspTable[1] = mCetInterruptSsp; InterruptSspTable[1] = mCetInterruptSsp;
PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4); PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);
@@ -222,4 +225,3 @@ InitShadowStack (
DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSspTable)); DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSspTable));
} }
} }

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