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UefiCpuPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiCpuPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:17 -08:00
committed by mergify[bot]
parent 91415a36ae
commit 053e878bfb
143 changed files with 14130 additions and 13035 deletions
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527
UefiCpuPkg/Application/Cpuid/Cpuid.c
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@@ -27,134 +27,134 @@
/// Structure for cache description lookup table /// Structure for cache description lookup table
/// ///
typedef struct { typedef struct {
UINT8 CacheDescriptor; UINT8 CacheDescriptor;
CHAR8 *Type; CHAR8 *Type;
CHAR8 *Description; CHAR8 *Description;
} CPUID_CACHE_INFO_DESCRIPTION; } CPUID_CACHE_INFO_DESCRIPTION;
/// ///
/// Cache description lookup table /// Cache description lookup table
/// ///
CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = { CPUID_CACHE_INFO_DESCRIPTION mCpuidCacheInfoDescription[] = {
{ 0x00 , "General" , "Null descriptor, this byte contains no information" }, { 0x00, "General", "Null descriptor, this byte contains no information" },
{ 0x01 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" }, { 0x01, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },
{ 0x02 , "TLB" , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" }, { 0x02, "TLB", "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },
{ 0x03 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" }, { 0x03, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },
{ 0x04 , "TLB" , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" }, { 0x04, "TLB", "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },
{ 0x05 , "TLB" , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" }, { 0x05, "TLB", "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },
{ 0x06 , "Cache" , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" }, { 0x06, "Cache", "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },
{ 0x08 , "Cache" , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" }, { 0x08, "Cache", "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },
{ 0x09 , "Cache" , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" }, { 0x09, "Cache", "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },
{ 0x0A , "Cache" , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" }, { 0x0A, "Cache", "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },
{ 0x0B , "TLB" , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" }, { 0x0B, "TLB", "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },
{ 0x0C , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" }, { 0x0C, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },
{ 0x0D , "Cache" , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" }, { 0x0D, "Cache", "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },
{ 0x0E , "Cache" , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" }, { 0x0E, "Cache", "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },
{ 0x1D , "Cache" , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" }, { 0x1D, "Cache", "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },
{ 0x21 , "Cache" , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" }, { 0x21, "Cache", "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },
{ 0x22 , "Cache" , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" }, { 0x22, "Cache", "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x23 , "Cache" , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x23, "Cache", "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x24 , "Cache" , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" }, { 0x24, "Cache", "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },
{ 0x25 , "Cache" , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x25, "Cache", "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x29 , "Cache" , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x29, "Cache", "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x2C , "Cache" , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" }, { 0x2C, "Cache", "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },
{ 0x30 , "Cache" , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" }, { 0x30, "Cache", "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },
{ 0x40 , "Cache" , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" }, { 0x40, "Cache", "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },
{ 0x41 , "Cache" , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" }, { 0x41, "Cache", "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },
{ 0x42 , "Cache" , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" }, { 0x42, "Cache", "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },
{ 0x43 , "Cache" , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" }, { 0x43, "Cache", "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },
{ 0x44 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" }, { 0x44, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },
{ 0x45 , "Cache" , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" }, { 0x45, "Cache", "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },
{ 0x46 , "Cache" , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" }, { 0x46, "Cache", "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },
{ 0x47 , "Cache" , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" }, { 0x47, "Cache", "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },
{ 0x48 , "Cache" , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" }, { 0x48, "Cache", "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },
{ 0x49 , "Cache" , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" }, { 0x49, "Cache", "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
{ 0x4A , "Cache" , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" }, { 0x4A, "Cache", "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },
{ 0x4B , "Cache" , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" }, { 0x4B, "Cache", "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },
{ 0x4C , "Cache" , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" }, { 0x4C, "Cache", "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },
{ 0x4D , "Cache" , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" }, { 0x4D, "Cache", "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },
{ 0x4E , "Cache" , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" }, { 0x4E, "Cache", "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },
{ 0x4F , "TLB" , "Instruction TLB: 4 KByte pages, 32 entries" }, { 0x4F, "TLB", "Instruction TLB: 4 KByte pages, 32 entries" },
{ 0x50 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" }, { 0x50, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },
{ 0x51 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" }, { 0x51, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },
{ 0x52 , "TLB" , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" }, { 0x52, "TLB", "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },
{ 0x55 , "TLB" , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" }, { 0x55, "TLB", "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },
{ 0x56 , "TLB" , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" }, { 0x56, "TLB", "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },
{ 0x57 , "TLB" , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" }, { 0x57, "TLB", "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },
{ 0x59 , "TLB" , "Data TLB0: 4 KByte pages, fully associative, 16 entries" }, { 0x59, "TLB", "Data TLB0: 4 KByte pages, fully associative, 16 entries" },
{ 0x5A , "TLB" , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" }, { 0x5A, "TLB", "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },
{ 0x5B , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" }, { 0x5B, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },
{ 0x5C , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,128 entries" }, { 0x5C, "TLB", "Data TLB: 4 KByte and 4 MByte pages,128 entries" },
{ 0x5D , "TLB" , "Data TLB: 4 KByte and 4 MByte pages,256 entries" }, { 0x5D, "TLB", "Data TLB: 4 KByte and 4 MByte pages,256 entries" },
{ 0x60 , "Cache" , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" }, { 0x60, "Cache", "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },
{ 0x61 , "TLB" , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" }, { 0x61, "TLB", "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },
{ 0x63 , "TLB" , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" }, { 0x63, "TLB", "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },
{ 0x64 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" }, { 0x64, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },
{ 0x66 , "Cache" , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" }, { 0x66, "Cache", "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },
{ 0x67 , "Cache" , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" }, { 0x67, "Cache", "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },
{ 0x68 , "Cache" , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" }, { 0x68, "Cache", "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },
{ 0x6A , "Cache" , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" }, { 0x6A, "Cache", "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },
{ 0x6B , "Cache" , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" }, { 0x6B, "Cache", "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },
{ 0x6C , "Cache" , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" }, { 0x6C, "Cache", "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },
{ 0x6D , "Cache" , "DTLB: 1 GByte pages, fully associative, 16 entries" }, { 0x6D, "Cache", "DTLB: 1 GByte pages, fully associative, 16 entries" },
{ 0x70 , "Cache" , "Trace cache: 12 K-uop, 8-way set associative" }, { 0x70, "Cache", "Trace cache: 12 K-uop, 8-way set associative" },
{ 0x71 , "Cache" , "Trace cache: 16 K-uop, 8-way set associative" }, { 0x71, "Cache", "Trace cache: 16 K-uop, 8-way set associative" },
{ 0x72 , "Cache" , "Trace cache: 32 K-uop, 8-way set associative" }, { 0x72, "Cache", "Trace cache: 32 K-uop, 8-way set associative" },
{ 0x76 , "TLB" , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" }, { 0x76, "TLB", "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },
{ 0x78 , "Cache" , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" }, { 0x78, "Cache", "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },
{ 0x79 , "Cache" , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x79, "Cache", "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x7A , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x7A, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x7B , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x7B, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x7C , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" }, { 0x7C, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },
{ 0x7D , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" }, { 0x7D, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },
{ 0x7F , "Cache" , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" }, { 0x7F, "Cache", "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },
{ 0x80 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" }, { 0x80, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },
{ 0x82 , "Cache" , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" }, { 0x82, "Cache", "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },
{ 0x83 , "Cache" , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" }, { 0x83, "Cache", "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },
{ 0x84 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" }, { 0x84, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },
{ 0x85 , "Cache" , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" }, { 0x85, "Cache", "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },
{ 0x86 , "Cache" , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, { 0x86, "Cache", "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
{ 0x87 , "Cache" , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" }, { 0x87, "Cache", "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
{ 0xA0 , "DTLB" , "DTLB: 4k pages, fully associative, 32 entries" }, { 0xA0, "DTLB", "DTLB: 4k pages, fully associative, 32 entries" },
{ 0xB0 , "TLB" , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" }, { 0xB0, "TLB", "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },
{ 0xB1 , "TLB" , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" }, { 0xB1, "TLB", "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },
{ 0xB2 , "TLB" , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" }, { 0xB2, "TLB", "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },
{ 0xB3 , "TLB" , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" }, { 0xB3, "TLB", "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },
{ 0xB4 , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" }, { 0xB4, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },
{ 0xB5 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" }, { 0xB5, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },
{ 0xB6 , "TLB" , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" }, { 0xB6, "TLB", "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },
{ 0xBA , "TLB" , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" }, { 0xBA, "TLB", "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },
{ 0xC0 , "TLB" , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" }, { 0xC0, "TLB", "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },
{ 0xC1 , "STLB" , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" }, { 0xC1, "STLB", "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },
{ 0xC2 , "DTLB" , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" }, { 0xC2, "DTLB", "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },
{ 0xC3 , "STLB" , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." }, { 0xC3, "STLB", "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },
{ 0xC4 , "DTLB" , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" }, { 0xC4, "DTLB", "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },
{ 0xCA , "STLB" , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" }, { 0xCA, "STLB", "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },
{ 0xD0 , "Cache" , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" }, { 0xD0, "Cache", "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },
{ 0xD1 , "Cache" , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" }, { 0xD1, "Cache", "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },
{ 0xD2 , "Cache" , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" }, { 0xD2, "Cache", "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },
{ 0xD6 , "Cache" , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" }, { 0xD6, "Cache", "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },
{ 0xD7 , "Cache" , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" }, { 0xD7, "Cache", "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },
{ 0xD8 , "Cache" , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" }, { 0xD8, "Cache", "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },
{ 0xDC , "Cache" , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" }, { 0xDC, "Cache", "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },
{ 0xDD , "Cache" , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" }, { 0xDD, "Cache", "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },
{ 0xDE , "Cache" , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" }, { 0xDE, "Cache", "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },
{ 0xE2 , "Cache" , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" }, { 0xE2, "Cache", "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },
{ 0xE3 , "Cache" , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" }, { 0xE3, "Cache", "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },
{ 0xE4 , "Cache" , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" }, { 0xE4, "Cache", "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },
{ 0xEA , "Cache" , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" }, { 0xEA, "Cache", "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },
{ 0xEB , "Cache" , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" }, { 0xEB, "Cache", "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },
{ 0xEC , "Cache" , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" }, { 0xEC, "Cache", "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },
{ 0xF0 , "Prefetch" , "64-Byte prefetching" }, { 0xF0, "Prefetch", "64-Byte prefetching" },
{ 0xF1 , "Prefetch" , "128-Byte prefetching" }, { 0xF1, "Prefetch", "128-Byte prefetching" },
{ 0xFE , "General" , "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." }, { 0xFE, "General", "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },
{ 0xFF , "General" , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" } { 0xFF, "General", "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }
}; };
/// ///
/// The maximum supported CPUID leaf index starting from leaf 0x00000000. /// The maximum supported CPUID leaf index starting from leaf 0x00000000.
/// ///
UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; UINT32 gMaximumBasicFunction = CPUID_SIGNATURE;
/// ///
/// The maximum supported CPUID leaf index starting from leaf 0x80000000. /// The maximum supported CPUID leaf index starting from leaf 0x80000000.
@@ -170,11 +170,11 @@ CpuidSignature (
VOID VOID
) )
{ {
UINT32 Eax; UINT32 Eax;
UINT32 Ebx; UINT32 Ebx;
UINT32 Ecx; UINT32 Ecx;
UINT32 Edx; UINT32 Edx;
CHAR8 Signature[13]; CHAR8 Signature[13];
AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx); AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
@@ -184,7 +184,7 @@ CpuidSignature (
*(UINT32 *)(Signature + 0) = Ebx; *(UINT32 *)(Signature + 0) = Ebx;
*(UINT32 *)(Signature + 4) = Edx; *(UINT32 *)(Signature + 4) = Edx;
*(UINT32 *)(Signature + 8) = Ecx; *(UINT32 *)(Signature + 8) = Ecx;
Signature [12] = 0; Signature[12] = 0;
Print (L" Signature = %a\n", Signature); Print (L" Signature = %a\n", Signature);
gMaximumBasicFunction = Eax; gMaximumBasicFunction = Eax;
@@ -221,7 +221,7 @@ CpuidVersionInfo (
} }
DisplayModel = Eax.Bits.Model; DisplayModel = Eax.Bits.Model;
if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) { if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {
DisplayModel |= (Eax.Bits.ExtendedModelId << 4); DisplayModel |= (Eax.Bits.ExtendedModelId << 4);
} }
@@ -314,12 +314,14 @@ LookupCacheDescription (
if (CacheDescriptor == 0x00) { if (CacheDescriptor == 0x00) {
return NULL; return NULL;
} }
NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]); NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);
for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) { for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {
if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) { if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {
return &mCpuidCacheInfoDescription[Descriptor]; return &mCpuidCacheInfoDescription[Descriptor];
} }
} }
return NULL; return NULL;
} }
@@ -354,13 +356,15 @@ CpuidCacheInfo (
for (Index = 1; Index < 4; Index++) { for (Index = 1; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]); CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);
if (CacheDescription != NULL) { if (CacheDescription != NULL) {
Print (L" %-8a %a\n", Print (
L" %-8a %a\n",
CacheDescription->Type, CacheDescription->Type,
CacheDescription->Description CacheDescription->Description
); );
} }
} }
} }
if (Ebx.Bits.NotValid == 0) { if (Ebx.Bits.NotValid == 0) {
// //
// Process Ebx.CacheDescriptor[0..3] // Process Ebx.CacheDescriptor[0..3]
@@ -368,13 +372,15 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) { for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]); CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);
if (CacheDescription != NULL) { if (CacheDescription != NULL) {
Print (L" %-8a %a\n", Print (
L" %-8a %a\n",
CacheDescription->Type, CacheDescription->Type,
CacheDescription->Description CacheDescription->Description
); );
} }
} }
} }
if (Ecx.Bits.NotValid == 0) { if (Ecx.Bits.NotValid == 0) {
// //
// Process Ecx.CacheDescriptor[0..3] // Process Ecx.CacheDescriptor[0..3]
@@ -382,13 +388,15 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) { for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]); CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);
if (CacheDescription != NULL) { if (CacheDescription != NULL) {
Print (L" %-8a %a\n", Print (
L" %-8a %a\n",
CacheDescription->Type, CacheDescription->Type,
CacheDescription->Description CacheDescription->Description
); );
} }
} }
} }
if (Edx.Bits.NotValid == 0) { if (Edx.Bits.NotValid == 0) {
// //
// Process Edx.CacheDescriptor[0..3] // Process Edx.CacheDescriptor[0..3]
@@ -396,7 +404,8 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) { for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]); CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);
if (CacheDescription != NULL) { if (CacheDescription != NULL) {
Print (L" %-8a %a\n", Print (
L" %-8a %a\n",
CacheDescription->Type, CacheDescription->Type,
CacheDescription->Description CacheDescription->Description
); );
@@ -457,8 +466,12 @@ CpuidCacheParams (
CacheLevel = 0; CacheLevel = 0;
do { do {
AsmCpuidEx ( AsmCpuidEx (
CPUID_CACHE_PARAMS, CacheLevel, CPUID_CACHE_PARAMS,
&Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32 CacheLevel,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx,
&Edx.Uint32
); );
if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) { if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {
Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel); Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);
@@ -472,11 +485,12 @@ CpuidCacheParams (
PRINT_BIT_FIELD (Ebx, LineSize); PRINT_BIT_FIELD (Ebx, LineSize);
PRINT_BIT_FIELD (Ebx, LinePartitions); PRINT_BIT_FIELD (Ebx, LinePartitions);
PRINT_BIT_FIELD (Ebx, Ways); PRINT_BIT_FIELD (Ebx, Ways);
PRINT_VALUE (Ecx, NumberOfSets); PRINT_VALUE (Ecx, NumberOfSets);
PRINT_BIT_FIELD (Edx, Invalidate); PRINT_BIT_FIELD (Edx, Invalidate);
PRINT_BIT_FIELD (Edx, CacheInclusiveness); PRINT_BIT_FIELD (Edx, CacheInclusiveness);
PRINT_BIT_FIELD (Edx, ComplexCacheIndexing); PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);
} }
CacheLevel++; CacheLevel++;
} while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL); } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
} }
@@ -585,15 +599,21 @@ CpuidStructuredExtendedFeatureFlags (
AsmCpuidEx ( AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
&Eax, NULL, NULL, NULL &Eax,
NULL,
NULL,
NULL
); );
for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) { for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
AsmCpuidEx ( AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
SubLeaf, SubLeaf,
NULL, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 NULL,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0 || Edx.Uint32 != 0) { if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) {
Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf); Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
PRINT_BIT_FIELD (Ebx, FSGSBASE); PRINT_BIT_FIELD (Ebx, FSGSBASE);
@@ -713,7 +733,7 @@ CpuidArchitecturalPerformanceMonitoring (
**/ **/
VOID VOID
CpuidExtendedTopology ( CpuidExtendedTopology (
UINT32 LeafFunction UINT32 LeafFunction
) )
{ {
CPUID_EXTENDED_TOPOLOGY_EAX Eax; CPUID_EXTENDED_TOPOLOGY_EAX Eax;
@@ -725,6 +745,7 @@ CpuidExtendedTopology (
if (LeafFunction > gMaximumBasicFunction) { if (LeafFunction > gMaximumBasicFunction) {
return; return;
} }
if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) { if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {
return; return;
} }
@@ -732,23 +753,29 @@ CpuidExtendedTopology (
LevelNumber = 0; LevelNumber = 0;
for (LevelNumber = 0; ; LevelNumber++) { for (LevelNumber = 0; ; LevelNumber++) {
AsmCpuidEx ( AsmCpuidEx (
LeafFunction, LevelNumber, LeafFunction,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx LevelNumber,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx
); );
if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break; break;
} }
Print ( Print (
L"%a (Leaf %08x, Sub-Leaf %08x)\n", L"%a (Leaf %08x, Sub-Leaf %08x)\n",
LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY", LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",
LeafFunction, LevelNumber LeafFunction,
LevelNumber
); );
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);
PRINT_BIT_FIELD (Eax, ApicIdShift); PRINT_BIT_FIELD (Eax, ApicIdShift);
PRINT_BIT_FIELD (Ebx, LogicalProcessors); PRINT_BIT_FIELD (Ebx, LogicalProcessors);
PRINT_BIT_FIELD (Ecx, LevelNumber); PRINT_BIT_FIELD (Ecx, LevelNumber);
PRINT_BIT_FIELD (Ecx, LevelType); PRINT_BIT_FIELD (Ecx, LevelType);
PRINT_VALUE (Edx, x2APIC_ID); PRINT_VALUE (Edx, x2APIC_ID);
} }
} }
@@ -767,8 +794,12 @@ CpuidExtendedStateSubLeaf (
UINT32 Edx; UINT32 Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, CPUID_EXTENDED_STATE,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx CPUID_EXTENDED_STATE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx
); );
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF); Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);
@@ -776,12 +807,12 @@ CpuidExtendedStateSubLeaf (
PRINT_BIT_FIELD (Eax, XSAVEC); PRINT_BIT_FIELD (Eax, XSAVEC);
PRINT_BIT_FIELD (Eax, XGETBV); PRINT_BIT_FIELD (Eax, XGETBV);
PRINT_BIT_FIELD (Eax, XSAVES); PRINT_BIT_FIELD (Eax, XSAVES);
PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS); PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);
PRINT_BIT_FIELD (Ecx, XCR0); PRINT_BIT_FIELD (Ecx, XCR0);
PRINT_BIT_FIELD (Ecx, HWPState); PRINT_BIT_FIELD (Ecx, HWPState);
PRINT_BIT_FIELD (Ecx, PT); PRINT_BIT_FIELD (Ecx, PT);
PRINT_BIT_FIELD (Ecx, XCR0_1); PRINT_BIT_FIELD (Ecx, XCR0_1);
PRINT_VALUE (Edx, IA32_XSS_Supported_32_63); PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);
} }
/** /**
@@ -801,14 +832,18 @@ CpuidExtendedStateSizeOffset (
for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) { for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
AsmCpuidEx ( AsmCpuidEx (
CPUID_EXTENDED_STATE, SubLeaf, CPUID_EXTENDED_STATE,
&Eax, &Ebx, &Ecx.Uint32, &Edx SubLeaf,
&Eax,
&Ebx,
&Ecx.Uint32,
&Edx
); );
if (Edx != 0) { if (Edx != 0) {
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf); Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);
PRINT_VALUE (Eax, FeatureSaveStateSize); PRINT_VALUE (Eax, FeatureSaveStateSize);
PRINT_VALUE (Ebx, FeatureSaveStateOffset); PRINT_VALUE (Ebx, FeatureSaveStateOffset);
PRINT_BIT_FIELD (Ecx, XSS); PRINT_BIT_FIELD (Ecx, XSS);
PRINT_BIT_FIELD (Ecx, Compacted); PRINT_BIT_FIELD (Ecx, Compacted);
} }
@@ -834,8 +869,12 @@ CpuidExtendedStateMainLeaf (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF, CPUID_EXTENDED_STATE,
&Eax.Uint32, &Ebx, &Ecx, &Edx CPUID_EXTENDED_STATE_MAIN_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx,
&Edx
); );
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF); Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);
@@ -847,9 +886,9 @@ CpuidExtendedStateMainLeaf (
PRINT_BIT_FIELD (Eax, IA32_XSS); PRINT_BIT_FIELD (Eax, IA32_XSS);
PRINT_BIT_FIELD (Eax, PKRU); PRINT_BIT_FIELD (Eax, PKRU);
PRINT_BIT_FIELD (Eax, IA32_XSS_2); PRINT_BIT_FIELD (Eax, IA32_XSS_2);
PRINT_VALUE (Ebx, EnabledSaveStateSize); PRINT_VALUE (Ebx, EnabledSaveStateSize);
PRINT_VALUE (Ecx, SupportedSaveStateSize); PRINT_VALUE (Ecx, SupportedSaveStateSize);
PRINT_VALUE (Edx, XCR0_Supported_32_63); PRINT_VALUE (Edx, XCR0_Supported_32_63);
CpuidExtendedStateSubLeaf (); CpuidExtendedStateSubLeaf ();
CpuidExtendedStateSizeOffset (); CpuidExtendedStateSizeOffset ();
@@ -864,20 +903,24 @@ CpuidIntelRdtMonitoringEnumerationSubLeaf (
VOID VOID
) )
{ {
UINT32 Ebx; UINT32 Ebx;
CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx; CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;
if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) { if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
return; return;
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF, CPUID_INTEL_RDT_MONITORING,
NULL, &Ebx, NULL, &Edx.Uint32 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
NULL,
&Ebx,
NULL,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF); Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);
PRINT_VALUE (Ebx, Maximum_RMID_Range); PRINT_VALUE (Ebx, Maximum_RMID_Range);
PRINT_BIT_FIELD (Edx, L3CacheRDT_M); PRINT_BIT_FIELD (Edx, L3CacheRDT_M);
} }
@@ -890,22 +933,26 @@ CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (
VOID VOID
) )
{ {
UINT32 Ebx; UINT32 Ebx;
UINT32 Ecx; UINT32 Ecx;
CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx; CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;
if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) { if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {
return; return;
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF, CPUID_INTEL_RDT_MONITORING,
NULL, &Ebx, &Ecx, &Edx.Uint32 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
NULL,
&Ebx,
&Ecx,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF); Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);
PRINT_VALUE (Ebx, OccupancyConversionFactor); PRINT_VALUE (Ebx, OccupancyConversionFactor);
PRINT_VALUE (Ecx, Maximum_RMID_Range); PRINT_VALUE (Ecx, Maximum_RMID_Range);
PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring); PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);
PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring); PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);
PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring); PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);
@@ -927,13 +974,17 @@ CpuidIntelRdtAllocationMemoryBandwidthSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx; CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF, CPUID_INTEL_RDT_ALLOCATION,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
PRINT_BIT_FIELD (Eax, MaximumMBAThrottling); PRINT_BIT_FIELD (Eax, MaximumMBAThrottling);
PRINT_VALUE (Ebx, AllocationUnitBitMap); PRINT_VALUE (Ebx, AllocationUnitBitMap);
PRINT_BIT_FIELD (Ecx, Liner); PRINT_BIT_FIELD (Ecx, Liner);
PRINT_BIT_FIELD (Edx, HighestCosNumber); PRINT_BIT_FIELD (Edx, HighestCosNumber);
} }
@@ -954,13 +1005,17 @@ CpuidIntelRdtAllocationL3CacheSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx; CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF, CPUID_INTEL_RDT_ALLOCATION,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
PRINT_BIT_FIELD (Eax, CapacityLength); PRINT_BIT_FIELD (Eax, CapacityLength);
PRINT_VALUE (Ebx, AllocationUnitBitMap); PRINT_VALUE (Ebx, AllocationUnitBitMap);
PRINT_BIT_FIELD (Ecx, CodeDataPrioritization); PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);
PRINT_BIT_FIELD (Edx, HighestCosNumber); PRINT_BIT_FIELD (Edx, HighestCosNumber);
} }
@@ -980,13 +1035,17 @@ CpuidIntelRdtAllocationL2CacheSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx; CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF, CPUID_INTEL_RDT_ALLOCATION,
&Eax.Uint32, &Ebx, NULL, &Edx.Uint32 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
NULL,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
PRINT_BIT_FIELD (Eax, CapacityLength); PRINT_BIT_FIELD (Eax, CapacityLength);
PRINT_VALUE (Ebx, AllocationUnitBitMap); PRINT_VALUE (Ebx, AllocationUnitBitMap);
PRINT_BIT_FIELD (Edx, HighestCosNumber); PRINT_BIT_FIELD (Edx, HighestCosNumber);
} }
@@ -1006,8 +1065,12 @@ CpuidIntelRdtAllocationMainLeaf (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF, CPUID_INTEL_RDT_ALLOCATION,
NULL, &Ebx.Uint32, NULL, NULL CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
NULL,
&Ebx.Uint32,
NULL,
NULL
); );
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF); Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);
@@ -1033,8 +1096,12 @@ CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx; CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF, CPUID_INTEL_SGX,
&Eax.Uint32, &Ebx, NULL, &Edx.Uint32 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
&Eax.Uint32,
&Ebx,
NULL,
&Edx.Uint32
); );
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF); Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
@@ -1055,14 +1122,18 @@ CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (
VOID VOID
) )
{ {
UINT32 Eax; UINT32 Eax;
UINT32 Ebx; UINT32 Ebx;
UINT32 Ecx; UINT32 Ecx;
UINT32 Edx; UINT32 Edx;
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF, CPUID_INTEL_SGX,
&Eax, &Ebx, &Ecx, &Edx CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
&Eax,
&Ebx,
&Ecx,
&Edx
); );
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF); Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);
@@ -1086,8 +1157,12 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf (
SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF; SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;
do { do {
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_SGX, SubLeaf, CPUID_INTEL_SGX,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 SubLeaf,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
if (Eax.Bits.SubLeafType == 0x1) { if (Eax.Bits.SubLeafType == 0x1) {
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf); Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);
@@ -1099,6 +1174,7 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf (
PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection); PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);
PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection); PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);
} }
SubLeaf++; SubLeaf++;
} while (Eax.Bits.SubLeafType == 0x1); } while (Eax.Bits.SubLeafType == 0x1);
} }
@@ -1121,7 +1197,10 @@ CpuidEnumerationOfIntelSgx (
AsmCpuidEx ( AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
NULL, &Ebx.Uint32, NULL, NULL NULL,
&Ebx.Uint32,
NULL,
NULL
); );
if (Ebx.Bits.SGX != 1) { if (Ebx.Bits.SGX != 1) {
// //
@@ -1153,8 +1232,12 @@ CpuidIntelProcessorTraceSubLeaf (
for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) { for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_PROCESSOR_TRACE, SubLeaf, CPUID_INTEL_PROCESSOR_TRACE,
&Eax.Uint32, &Ebx.Uint32, NULL, NULL SubLeaf,
&Eax.Uint32,
&Ebx.Uint32,
NULL,
NULL
); );
Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf); Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);
@@ -1183,12 +1266,16 @@ CpuidIntelProcessorTraceMainLeaf (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, CPUID_INTEL_PROCESSOR_TRACE,
&Eax, &Ebx.Uint32, &Ecx.Uint32, NULL CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
&Eax,
&Ebx.Uint32,
&Ecx.Uint32,
NULL
); );
Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF); Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);
PRINT_VALUE (Eax, MaximumSubLeaf); PRINT_VALUE (Eax, MaximumSubLeaf);
PRINT_BIT_FIELD (Ebx, Cr3Filter); PRINT_BIT_FIELD (Ebx, Cr3Filter);
PRINT_BIT_FIELD (Ebx, ConfigurablePsb); PRINT_BIT_FIELD (Ebx, ConfigurablePsb);
PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering); PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);
@@ -1270,11 +1357,15 @@ CpuidSocVendorBrandString (
// 4 32-bit brand string values per leaf and an extra value to // 4 32-bit brand string values per leaf and an extra value to
// null terminate the string. // null terminate the string.
// //
UINT32 BrandString[3 * 4 + 1]; UINT32 BrandString[3 * 4 + 1];
AsmCpuidEx ( AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1, CPUID_SOC_VENDOR,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 CPUID_SOC_VENDOR_BRAND_STRING1,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1284,8 +1375,12 @@ CpuidSocVendorBrandString (
BrandString[3] = Edx.Uint32; BrandString[3] = Edx.Uint32;
AsmCpuidEx ( AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2, CPUID_SOC_VENDOR,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 CPUID_SOC_VENDOR_BRAND_STRING2,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1295,8 +1390,12 @@ CpuidSocVendorBrandString (
BrandString[7] = Edx.Uint32; BrandString[7] = Edx.Uint32;
AsmCpuidEx ( AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3, CPUID_SOC_VENDOR,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32 CPUID_SOC_VENDOR_BRAND_STRING3,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
); );
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1329,8 +1428,12 @@ CpuidSocVendor (
} }
AsmCpuidEx ( AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF, CPUID_SOC_VENDOR,
&Eax, &Ebx.Uint32, &Ecx, &Edx CPUID_SOC_VENDOR_MAIN_LEAF,
&Eax,
&Ebx.Uint32,
&Ecx,
&Edx
); );
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF); Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);
@@ -1338,11 +1441,12 @@ CpuidSocVendor (
Print (L" Not Supported\n"); Print (L" Not Supported\n");
return; return;
} }
PRINT_VALUE (Eax, MaxSOCID_Index);
PRINT_VALUE (Eax, MaxSOCID_Index);
PRINT_BIT_FIELD (Ebx, SocVendorId); PRINT_BIT_FIELD (Ebx, SocVendorId);
PRINT_BIT_FIELD (Ebx, IsVendorScheme); PRINT_BIT_FIELD (Ebx, IsVendorScheme);
PRINT_VALUE (Ecx, ProjectID); PRINT_VALUE (Ecx, ProjectID);
PRINT_VALUE (Edx, SteppingID); PRINT_VALUE (Edx, SteppingID);
CpuidSocVendorBrandString (); CpuidSocVendorBrandString ();
} }
@@ -1367,12 +1471,15 @@ CpuidDeterministicAddressTranslationParameters (
AsmCpuidEx ( AsmCpuidEx (
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
&Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32 &Eax,
&Ebx.Uint32,
&Ecx,
&Edx.Uint32
); );
Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF); Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);
PRINT_VALUE (Eax, MaxID_Index); PRINT_VALUE (Eax, MaxID_Index);
PRINT_BIT_FIELD (Ebx, Page4K); PRINT_BIT_FIELD (Ebx, Page4K);
PRINT_BIT_FIELD (Ebx, Page2M); PRINT_BIT_FIELD (Ebx, Page2M);
PRINT_BIT_FIELD (Ebx, Page4M); PRINT_BIT_FIELD (Ebx, Page4M);
@@ -1380,7 +1487,7 @@ CpuidDeterministicAddressTranslationParameters (
PRINT_BIT_FIELD (Ebx, Partitioning); PRINT_BIT_FIELD (Ebx, Partitioning);
PRINT_BIT_FIELD (Ebx, Way); PRINT_BIT_FIELD (Ebx, Way);
PRINT_VALUE (Ecx, NumberOfSets); PRINT_VALUE (Ecx, NumberOfSets);
PRINT_BIT_FIELD (Edx, TranslationCacheType); PRINT_BIT_FIELD (Edx, TranslationCacheType);
PRINT_BIT_FIELD (Edx, TranslationCacheLevel); PRINT_BIT_FIELD (Edx, TranslationCacheLevel);
@@ -1402,7 +1509,7 @@ CpuidExtendedFunction (
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION); Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0); Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, 0, 0, 0);
PRINT_VALUE (Eax, MaximumExtendedFunction); PRINT_VALUE (Eax, MaximumExtendedFunction);
gMaximumExtendedFunction = Eax; gMaximumExtendedFunction = Eax;
} }
@@ -1456,7 +1563,7 @@ CpuidProcessorBrandString (
// 4 32-bit brand string values per leaf and an extra value to // 4 32-bit brand string values per leaf and an extra value to
// null terminate the string. // null terminate the string.
// //
UINT32 BrandString[3 * 4 + 1]; UINT32 BrandString[3 * 4 + 1];
if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) { if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {
AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32); AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
@@ -1583,11 +1690,11 @@ UefiMain (
CpuidVersionInfo (); CpuidVersionInfo ();
CpuidCacheInfo (); CpuidCacheInfo ();
CpuidSerialNumber (); CpuidSerialNumber ();
CpuidCacheParams(); CpuidCacheParams ();
CpuidMonitorMwait (); CpuidMonitorMwait ();
CpuidThermalPowerManagement (); CpuidThermalPowerManagement ();
CpuidStructuredExtendedFeatureFlags (); CpuidStructuredExtendedFeatureFlags ();
CpuidDirectCacheAccessInfo(); CpuidDirectCacheAccessInfo ();
CpuidArchitecturalPerformanceMonitoring (); CpuidArchitecturalPerformanceMonitoring ();
CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY); CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY);
CpuidExtendedStateMainLeaf (); CpuidExtendedStateMainLeaf ();

422
UefiCpuPkg/CpuDxe/CpuDxe.c
View File

@@ -13,15 +13,15 @@
// //
// Global Variables // Global Variables
// //
BOOLEAN InterruptState = FALSE; BOOLEAN InterruptState = FALSE;
EFI_HANDLE mCpuHandle = NULL; EFI_HANDLE mCpuHandle = NULL;
BOOLEAN mIsFlushingGCD; BOOLEAN mIsFlushingGCD;
BOOLEAN mIsAllocatingPageTable = FALSE; BOOLEAN mIsAllocatingPageTable = FALSE;
UINT64 mValidMtrrAddressMask; UINT64 mValidMtrrAddressMask;
UINT64 mValidMtrrBitsMask; UINT64 mValidMtrrBitsMask;
UINT64 mTimerPeriod = 0; UINT64 mTimerPeriod = 0;
FIXED_MTRR mFixedMtrrTable[] = { FIXED_MTRR mFixedMtrrTable[] = {
{ {
MSR_IA32_MTRR_FIX64K_00000, MSR_IA32_MTRR_FIX64K_00000,
0, 0,
@@ -79,7 +79,6 @@ FIXED_MTRR mFixedMtrrTable[] = {
}, },
}; };
EFI_CPU_ARCH_PROTOCOL gCpu = { EFI_CPU_ARCH_PROTOCOL gCpu = {
CpuFlushCpuDataCache, CpuFlushCpuDataCache,
CpuEnableInterrupt, CpuEnableInterrupt,
@@ -115,10 +114,10 @@ EFI_CPU_ARCH_PROTOCOL gCpu = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuFlushCpuDataCache ( CpuFlushCpuDataCache (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS Start, IN EFI_PHYSICAL_ADDRESS Start,
IN UINT64 Length, IN UINT64 Length,
IN EFI_CPU_FLUSH_TYPE FlushType IN EFI_CPU_FLUSH_TYPE FlushType
) )
{ {
if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) { if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
@@ -132,7 +131,6 @@ CpuFlushCpuDataCache (
} }
} }
/** /**
Enables CPU interrupts. Enables CPU interrupts.
@@ -145,7 +143,7 @@ CpuFlushCpuDataCache (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuEnableInterrupt ( CpuEnableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This IN EFI_CPU_ARCH_PROTOCOL *This
) )
{ {
EnableInterrupts (); EnableInterrupts ();
@@ -154,7 +152,6 @@ CpuEnableInterrupt (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Disables CPU interrupts. Disables CPU interrupts.
@@ -167,7 +164,7 @@ CpuEnableInterrupt (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuDisableInterrupt ( CpuDisableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This IN EFI_CPU_ARCH_PROTOCOL *This
) )
{ {
DisableInterrupts (); DisableInterrupts ();
@@ -176,7 +173,6 @@ CpuDisableInterrupt (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Return the state of interrupts. Return the state of interrupts.
@@ -190,8 +186,8 @@ CpuDisableInterrupt (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuGetInterruptState ( CpuGetInterruptState (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
OUT BOOLEAN *State OUT BOOLEAN *State
) )
{ {
if (State == NULL) { if (State == NULL) {
@@ -202,7 +198,6 @@ CpuGetInterruptState (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Generates an INIT to the CPU. Generates an INIT to the CPU.
@@ -218,14 +213,13 @@ CpuGetInterruptState (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuInit ( CpuInit (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_CPU_INIT_TYPE InitType IN EFI_CPU_INIT_TYPE InitType
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
/** /**
Registers a function to be called from the CPU interrupt handler. Registers a function to be called from the CPU interrupt handler.
@@ -249,15 +243,14 @@ CpuInit (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuRegisterInterruptHandler ( CpuRegisterInterruptHandler (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
) )
{ {
return RegisterCpuInterruptHandler (InterruptType, InterruptHandler); return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
} }
/** /**
Returns a timer value from one of the CPU's internal timers. There is no Returns a timer value from one of the CPU's internal timers. There is no
inherent time interval between ticks but is a function of the CPU frequency. inherent time interval between ticks but is a function of the CPU frequency.
@@ -284,14 +277,14 @@ CpuRegisterInterruptHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuGetTimerValue ( CpuGetTimerValue (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN UINT32 TimerIndex, IN UINT32 TimerIndex,
OUT UINT64 *TimerValue, OUT UINT64 *TimerValue,
OUT UINT64 *TimerPeriod OPTIONAL OUT UINT64 *TimerPeriod OPTIONAL
) )
{ {
UINT64 BeginValue; UINT64 BeginValue;
UINT64 EndValue; UINT64 EndValue;
if (TimerValue == NULL) { if (TimerValue == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
@@ -310,7 +303,7 @@ CpuGetTimerValue (
// //
BeginValue = AsmReadTsc (); BeginValue = AsmReadTsc ();
MicroSecondDelay (100); MicroSecondDelay (100);
EndValue = AsmReadTsc (); EndValue = AsmReadTsc ();
// //
// Calculate the actual frequency // Calculate the actual frequency
// //
@@ -323,6 +316,7 @@ CpuGetTimerValue (
NULL NULL
); );
} }
*TimerPeriod = mTimerPeriod; *TimerPeriod = mTimerPeriod;
} }
@@ -339,7 +333,7 @@ CpuGetTimerValue (
VOID VOID
EFIAPI EFIAPI
SetMtrrsFromBuffer ( SetMtrrsFromBuffer (
IN VOID *Buffer IN VOID *Buffer
) )
{ {
MtrrSetAllMtrrs (Buffer); MtrrSetAllMtrrs (Buffer);
@@ -373,10 +367,10 @@ SetMtrrsFromBuffer (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuSetMemoryAttributes ( CpuSetMemoryAttributes (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
) )
{ {
RETURN_STATUS Status; RETURN_STATUS Status;
@@ -395,7 +389,7 @@ CpuSetMemoryAttributes (
// to avoid unnecessary computing. // to avoid unnecessary computing.
// //
if (mIsFlushingGCD) { if (mIsFlushingGCD) {
DEBUG((DEBUG_VERBOSE, " Flushing GCD\n")); DEBUG ((DEBUG_VERBOSE, " Flushing GCD\n"));
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -410,11 +404,11 @@ CpuSetMemoryAttributes (
// by page table memory allocation. // by page table memory allocation.
// //
if (mIsAllocatingPageTable) { if (mIsAllocatingPageTable) {
DEBUG((DEBUG_VERBOSE, " Allocating page table memory\n")); DEBUG ((DEBUG_VERBOSE, " Allocating page table memory\n"));
return EFI_SUCCESS; return EFI_SUCCESS;
} }
CacheAttributes = Attributes & EFI_CACHE_ATTRIBUTE_MASK; CacheAttributes = Attributes & EFI_CACHE_ATTRIBUTE_MASK;
MemoryAttributes = Attributes & EFI_MEMORY_ATTRIBUTE_MASK; MemoryAttributes = Attributes & EFI_MEMORY_ATTRIBUTE_MASK;
if (Attributes != (CacheAttributes | MemoryAttributes)) { if (Attributes != (CacheAttributes | MemoryAttributes)) {
@@ -427,30 +421,31 @@ CpuSetMemoryAttributes (
} }
switch (CacheAttributes) { switch (CacheAttributes) {
case EFI_MEMORY_UC: case EFI_MEMORY_UC:
CacheType = CacheUncacheable; CacheType = CacheUncacheable;
break; break;
case EFI_MEMORY_WC: case EFI_MEMORY_WC:
CacheType = CacheWriteCombining; CacheType = CacheWriteCombining;
break; break;
case EFI_MEMORY_WT: case EFI_MEMORY_WT:
CacheType = CacheWriteThrough; CacheType = CacheWriteThrough;
break; break;
case EFI_MEMORY_WP: case EFI_MEMORY_WP:
CacheType = CacheWriteProtected; CacheType = CacheWriteProtected;
break; break;
case EFI_MEMORY_WB: case EFI_MEMORY_WB:
CacheType = CacheWriteBack; CacheType = CacheWriteBack;
break; break;
default: default:
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);
CurrentCacheType = MtrrGetMemoryAttribute (BaseAddress);
if (CurrentCacheType != CacheType) { if (CurrentCacheType != CacheType) {
// //
// call MTRR library function // call MTRR library function
@@ -484,7 +479,8 @@ CpuSetMemoryAttributes (
ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED); ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);
} }
} }
if (EFI_ERROR(Status)) {
if (EFI_ERROR (Status)) {
return Status; return Status;
} }
} }
@@ -507,15 +503,15 @@ InitializeMtrrMask (
VOID VOID
) )
{ {
UINT32 RegEax; UINT32 RegEax;
UINT8 PhysicalAddressBits; UINT8 PhysicalAddressBits;
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) { if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
PhysicalAddressBits = (UINT8) RegEax; PhysicalAddressBits = (UINT8)RegEax;
} else { } else {
PhysicalAddressBits = 36; PhysicalAddressBits = 36;
} }
@@ -536,22 +532,22 @@ InitializeMtrrMask (
**/ **/
UINT64 UINT64
GetMemorySpaceAttributeFromMtrrType ( GetMemorySpaceAttributeFromMtrrType (
IN UINT8 MtrrAttributes IN UINT8 MtrrAttributes
) )
{ {
switch (MtrrAttributes) { switch (MtrrAttributes) {
case MTRR_CACHE_UNCACHEABLE: case MTRR_CACHE_UNCACHEABLE:
return EFI_MEMORY_UC; return EFI_MEMORY_UC;
case MTRR_CACHE_WRITE_COMBINING: case MTRR_CACHE_WRITE_COMBINING:
return EFI_MEMORY_WC; return EFI_MEMORY_WC;
case MTRR_CACHE_WRITE_THROUGH: case MTRR_CACHE_WRITE_THROUGH:
return EFI_MEMORY_WT; return EFI_MEMORY_WT;
case MTRR_CACHE_WRITE_PROTECTED: case MTRR_CACHE_WRITE_PROTECTED:
return EFI_MEMORY_WP; return EFI_MEMORY_WP;
case MTRR_CACHE_WRITE_BACK: case MTRR_CACHE_WRITE_BACK:
return EFI_MEMORY_WB; return EFI_MEMORY_WB;
default: default:
return 0; return 0;
} }
} }
@@ -575,29 +571,33 @@ GetMemorySpaceAttributeFromMtrrType (
**/ **/
EFI_STATUS EFI_STATUS
SearchGcdMemorySpaces ( SearchGcdMemorySpaces (
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors, IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
OUT UINTN *StartIndex, OUT UINTN *StartIndex,
OUT UINTN *EndIndex OUT UINTN *EndIndex
) )
{ {
UINTN Index; UINTN Index;
*StartIndex = 0; *StartIndex = 0;
*EndIndex = 0; *EndIndex = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) { for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (BaseAddress >= MemorySpaceMap[Index].BaseAddress && if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&
BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { (BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))
{
*StartIndex = Index; *StartIndex = Index;
} }
if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { if ((BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress) &&
(BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))
{
*EndIndex = Index; *EndIndex = Index;
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
@@ -619,11 +619,11 @@ SearchGcdMemorySpaces (
**/ **/
EFI_STATUS EFI_STATUS
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
IN UINTN NumberOfDescriptors, IN UINTN NumberOfDescriptors,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@@ -655,6 +655,7 @@ SetGcdMemorySpaceAttributes (
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue; continue;
} }
// //
// Calculate the start and end address of the overlapping range // Calculate the start and end address of the overlapping range
// //
@@ -663,11 +664,13 @@ SetGcdMemorySpaceAttributes (
} else { } else {
RegionStart = MemorySpaceMap[Index].BaseAddress; RegionStart = MemorySpaceMap[Index].BaseAddress;
} }
if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) { if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
RegionLength = BaseAddress + Length - RegionStart; RegionLength = BaseAddress + Length - RegionStart;
} else { } else {
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart; RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
} }
// //
// Set memory attributes according to MTRR attribute and the original attribute of descriptor // Set memory attributes according to MTRR attribute and the original attribute of descriptor
// //
@@ -681,7 +684,6 @@ SetGcdMemorySpaceAttributes (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Refreshes the GCD Memory Space attributes according to MTRRs. Refreshes the GCD Memory Space attributes according to MTRRs.
@@ -693,22 +695,22 @@ RefreshMemoryAttributesFromMtrr (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
UINTN SubIndex; UINTN SubIndex;
UINT64 RegValue; UINT64 RegValue;
EFI_PHYSICAL_ADDRESS BaseAddress; EFI_PHYSICAL_ADDRESS BaseAddress;
UINT64 Length; UINT64 Length;
UINT64 Attributes; UINT64 Attributes;
UINT64 CurrentAttributes; UINT64 CurrentAttributes;
UINT8 MtrrType; UINT8 MtrrType;
UINTN NumberOfDescriptors; UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
UINT64 DefaultAttributes; UINT64 DefaultAttributes;
VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
MTRR_FIXED_SETTINGS MtrrFixedSettings; MTRR_FIXED_SETTINGS MtrrFixedSettings;
UINT32 FirmwareVariableMtrrCount; UINT32 FirmwareVariableMtrrCount;
UINT8 DefaultMemoryType; UINT8 DefaultMemoryType;
FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount (); FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR); ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
@@ -738,7 +740,7 @@ RefreshMemoryAttributesFromMtrr (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType (); DefaultMemoryType = (UINT8)MtrrGetDefaultMemoryType ();
DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType); DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);
// //
@@ -748,6 +750,7 @@ RefreshMemoryAttributesFromMtrr (
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) { if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue; continue;
} }
gDS->SetMemorySpaceAttributes ( gDS->SetMemorySpaceAttributes (
MemorySpaceMap[Index].BaseAddress, MemorySpaceMap[Index].BaseAddress,
MemorySpaceMap[Index].Length, MemorySpaceMap[Index].Length,
@@ -761,7 +764,8 @@ RefreshMemoryAttributesFromMtrr (
// //
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid && if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) { (VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK))
{
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
MemorySpaceMap, MemorySpaceMap,
NumberOfDescriptors, NumberOfDescriptors,
@@ -777,9 +781,10 @@ RefreshMemoryAttributesFromMtrr (
// //
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid && if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK && (VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) &&
VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) { (VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE))
Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type); {
Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8)VariableMtrr[Index].Type);
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
MemorySpaceMap, MemorySpaceMap,
NumberOfDescriptors, NumberOfDescriptors,
@@ -795,7 +800,8 @@ RefreshMemoryAttributesFromMtrr (
// //
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) { for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid && if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) { (VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE))
{
SetGcdMemorySpaceAttributes ( SetGcdMemorySpaceAttributes (
MemorySpaceMap, MemorySpaceMap,
NumberOfDescriptors, NumberOfDescriptors,
@@ -819,7 +825,7 @@ RefreshMemoryAttributesFromMtrr (
// Check for continuous fixed MTRR sections // Check for continuous fixed MTRR sections
// //
for (SubIndex = 0; SubIndex < 8; SubIndex++) { for (SubIndex = 0; SubIndex < 8; SubIndex++) {
MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8); MtrrType = (UINT8)RShiftU64 (RegValue, SubIndex * 8);
CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType); CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);
if (Length == 0) { if (Length == 0) {
// //
@@ -839,13 +845,15 @@ RefreshMemoryAttributesFromMtrr (
Attributes Attributes
); );
BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex; BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;
Length = 0; Length = 0;
Attributes = CurrentAttributes; Attributes = CurrentAttributes;
} }
} }
Length += mFixedMtrrTable[Index].Length; Length += mFixedMtrrTable[Index].Length;
} }
} }
// //
// Handle the last fixed MTRR region // Handle the last fixed MTRR region
// //
@@ -916,20 +924,20 @@ InitInterruptDescriptorTable (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_VECTOR_HANDOFF_INFO *VectorInfoList; EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
EFI_VECTOR_HANDOFF_INFO *VectorInfo; EFI_VECTOR_HANDOFF_INFO *VectorInfo;
VectorInfo = NULL; VectorInfo = NULL;
Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList); Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
if (Status == EFI_SUCCESS && VectorInfoList != NULL) { if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {
VectorInfo = VectorInfoList; VectorInfo = VectorInfoList;
} }
Status = InitializeCpuInterruptHandlers (VectorInfo); Status = InitializeCpuInterruptHandlers (VectorInfo);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
/** /**
Callback function for idle events. Callback function for idle events.
@@ -941,8 +949,8 @@ InitInterruptDescriptorTable (
VOID VOID
EFIAPI EFIAPI
IdleLoopEventCallback ( IdleLoopEventCallback (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
CpuSleep (); CpuSleep ();
@@ -989,24 +997,27 @@ IdleLoopEventCallback (
**/ **/
EFI_STATUS EFI_STATUS
IntersectMemoryDescriptor ( IntersectMemoryDescriptor (
IN UINT64 Base, IN UINT64 Base,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Capabilities, IN UINT64 Capabilities,
IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
) )
{ {
UINT64 IntersectionBase; UINT64 IntersectionBase;
UINT64 IntersectionEnd; UINT64 IntersectionEnd;
EFI_STATUS Status; EFI_STATUS Status;
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo && if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&
(Descriptor->Capabilities & Capabilities) == Capabilities) { ((Descriptor->Capabilities & Capabilities) == Capabilities))
{
return EFI_SUCCESS; return EFI_SUCCESS;
} }
IntersectionBase = MAX (Base, Descriptor->BaseAddress); IntersectionBase = MAX (Base, Descriptor->BaseAddress);
IntersectionEnd = MIN (Base + Length, IntersectionEnd = MIN (
Descriptor->BaseAddress + Descriptor->Length); Base + Length,
Descriptor->BaseAddress + Descriptor->Length
);
if (IntersectionBase >= IntersectionEnd) { if (IntersectionBase >= IntersectionEnd) {
// //
// The descriptor and the aperture don't overlap. // The descriptor and the aperture don't overlap.
@@ -1015,21 +1026,39 @@ IntersectMemoryDescriptor (
} }
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) { if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo, Status = gDS->AddMemorySpace (
IntersectionBase, IntersectionEnd - IntersectionBase, EfiGcdMemoryTypeMemoryMappedIo,
Capabilities); IntersectionBase,
IntersectionEnd - IntersectionBase,
Capabilities
);
DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, DEBUG ((
"%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__, EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
IntersectionBase, IntersectionEnd, Status)); "%a: %a: add [%Lx, %Lx): %r\n",
gEfiCallerBaseName,
__FUNCTION__,
IntersectionBase,
IntersectionEnd,
Status
));
return Status; return Status;
} }
DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts " DEBUG ((
"with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__, DEBUG_ERROR,
Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
(UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities, "with aperture [%Lx, %Lx) cap %Lx\n",
Base, Base + Length, Capabilities)); gEfiCallerBaseName,
__FUNCTION__,
Descriptor->BaseAddress,
Descriptor->BaseAddress + Descriptor->Length,
(UINT32)Descriptor->GcdMemoryType,
Descriptor->Capabilities,
Base,
Base + Length,
Capabilities
));
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -1046,49 +1075,60 @@ IntersectMemoryDescriptor (
**/ **/
EFI_STATUS EFI_STATUS
AddMemoryMappedIoSpace ( AddMemoryMappedIoSpace (
IN UINT64 Base, IN UINT64 Base,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Capabilities IN UINT64 Capabilities
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
UINTN NumberOfDescriptors; UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap); Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n", DEBUG ((
gEfiCallerBaseName, __FUNCTION__, Status)); DEBUG_ERROR,
"%a: %a: GetMemorySpaceMap(): %r\n",
gEfiCallerBaseName,
__FUNCTION__,
Status
));
return Status; return Status;
} }
for (Index = 0; Index < NumberOfDescriptors; Index++) { for (Index = 0; Index < NumberOfDescriptors; Index++) {
Status = IntersectMemoryDescriptor (Base, Length, Capabilities, Status = IntersectMemoryDescriptor (
&MemorySpaceMap[Index]); Base,
Length,
Capabilities,
&MemorySpaceMap[Index]
);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
goto FreeMemorySpaceMap; goto FreeMemorySpaceMap;
} }
} }
DEBUG_CODE_BEGIN (); DEBUG_CODE_BEGIN ();
// //
// Make sure there are adjacent descriptors covering [Base, Base + Length). // Make sure there are adjacent descriptors covering [Base, Base + Length).
// It is possible that they have not been merged; merging can be prevented // It is possible that they have not been merged; merging can be prevented
// by allocation and different capabilities. // by allocation and different capabilities.
// //
UINT64 CheckBase; UINT64 CheckBase;
EFI_STATUS CheckStatus; EFI_STATUS CheckStatus;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor; EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
for (CheckBase = Base;
CheckBase < Base + Length;
CheckBase = Descriptor.BaseAddress + Descriptor.Length)
{
CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
ASSERT_EFI_ERROR (CheckStatus);
ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
}
for (CheckBase = Base;
CheckBase < Base + Length;
CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
ASSERT_EFI_ERROR (CheckStatus);
ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
}
DEBUG_CODE_END (); DEBUG_CODE_END ();
FreeMemorySpaceMap: FreeMemorySpaceMap:
@@ -1105,14 +1145,14 @@ FreeMemorySpaceMap:
**/ **/
VOID VOID
AddLocalApicMemorySpace ( AddLocalApicMemorySpace (
IN EFI_HANDLE ImageHandle IN EFI_HANDLE ImageHandle
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS BaseAddress; EFI_PHYSICAL_ADDRESS BaseAddress;
BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress(); BaseAddress = (EFI_PHYSICAL_ADDRESS)GetLocalApicBaseAddress ();
Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC); Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// //
@@ -1130,8 +1170,13 @@ AddLocalApicMemorySpace (
NULL NULL
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n", DEBUG ((
gEfiCallerBaseName, __FUNCTION__, Status)); DEBUG_INFO,
"%a: %a: AllocateMemorySpace() Status - %r\n",
gEfiCallerBaseName,
__FUNCTION__,
Status
));
} }
} }
@@ -1149,14 +1194,14 @@ AddLocalApicMemorySpace (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpu ( InitializeCpu (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_EVENT IdleLoopEvent; EFI_EVENT IdleLoopEvent;
InitializePageTableLib(); InitializePageTableLib ();
InitializeFloatingPointUnits (); InitializeFloatingPointUnits ();
@@ -1180,7 +1225,8 @@ InitializeCpu (
// //
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&mCpuHandle, &mCpuHandle,
&gEfiCpuArchProtocolGuid, &gCpu, &gEfiCpuArchProtocolGuid,
&gCpu,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

59
UefiCpuPkg/CpuDxe/CpuDxe.h
View File

@@ -63,10 +63,10 @@
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuFlushCpuDataCache ( CpuFlushCpuDataCache (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS Start, IN EFI_PHYSICAL_ADDRESS Start,
IN UINT64 Length, IN UINT64 Length,
IN EFI_CPU_FLUSH_TYPE FlushType IN EFI_CPU_FLUSH_TYPE FlushType
); );
/** /**
@@ -81,7 +81,7 @@ CpuFlushCpuDataCache (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuEnableInterrupt ( CpuEnableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This IN EFI_CPU_ARCH_PROTOCOL *This
); );
/** /**
@@ -96,7 +96,7 @@ CpuEnableInterrupt (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuDisableInterrupt ( CpuDisableInterrupt (
IN EFI_CPU_ARCH_PROTOCOL *This IN EFI_CPU_ARCH_PROTOCOL *This
); );
/** /**
@@ -112,8 +112,8 @@ CpuDisableInterrupt (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuGetInterruptState ( CpuGetInterruptState (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
OUT BOOLEAN *State OUT BOOLEAN *State
); );
/** /**
@@ -131,8 +131,8 @@ CpuGetInterruptState (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuInit ( CpuInit (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_CPU_INIT_TYPE InitType IN EFI_CPU_INIT_TYPE InitType
); );
/** /**
@@ -158,9 +158,9 @@ CpuInit (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuRegisterInterruptHandler ( CpuRegisterInterruptHandler (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
); );
/** /**
@@ -189,10 +189,10 @@ CpuRegisterInterruptHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuGetTimerValue ( CpuGetTimerValue (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN UINT32 TimerIndex, IN UINT32 TimerIndex,
OUT UINT64 *TimerValue, OUT UINT64 *TimerValue,
OUT UINT64 *TimerPeriod OPTIONAL OUT UINT64 *TimerPeriod OPTIONAL
); );
/** /**
@@ -214,10 +214,10 @@ CpuGetTimerValue (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuSetMemoryAttributes ( CpuSetMemoryAttributes (
IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS BaseAddress, IN EFI_PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
); );
/** /**
@@ -238,7 +238,7 @@ InitGlobalDescriptorTable (
VOID VOID
EFIAPI EFIAPI
SetCodeSelector ( SetCodeSelector (
UINT16 Selector UINT16 Selector
); );
/** /**
@@ -250,7 +250,7 @@ SetCodeSelector (
VOID VOID
EFIAPI EFIAPI
SetDataSelectors ( SetDataSelectors (
UINT16 Selector UINT16 Selector
); );
/** /**
@@ -273,8 +273,8 @@ RefreshGcdMemoryAttributesFromPaging (
VOID VOID
EFIAPI EFIAPI
DebugExceptionHandler ( DebugExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
); );
/** /**
@@ -289,12 +289,11 @@ DebugExceptionHandler (
VOID VOID
EFIAPI EFIAPI
PageFaultExceptionHandler ( PageFaultExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
); );
extern BOOLEAN mIsAllocatingPageTable; extern BOOLEAN mIsAllocatingPageTable;
extern UINTN mNumberOfProcessors; extern UINTN mNumberOfProcessors;
#endif #endif

8
UefiCpuPkg/CpuDxe/CpuGdt.c
View File

@@ -13,7 +13,7 @@
// //
// Global descriptor table (GDT) Template // Global descriptor table (GDT) Template
// //
STATIC GDT_ENTRIES mGdtTemplate = { STATIC GDT_ENTRIES mGdtTemplate = {
// //
// NULL_SEL // NULL_SEL
// //
@@ -143,7 +143,7 @@ InitGlobalDescriptorTable (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
ASSERT ((Memory != 0) && (Memory < SIZE_4GB)); ASSERT ((Memory != 0) && (Memory < SIZE_4GB));
Gdt = (GDT_ENTRIES *) (UINTN) Memory; Gdt = (GDT_ENTRIES *)(UINTN)Memory;
// //
// Initialize all GDT entries // Initialize all GDT entries
@@ -153,8 +153,8 @@ InitGlobalDescriptorTable (
// //
// Write GDT register // Write GDT register
// //
Gdtr.Base = (UINT32) (UINTN) Gdt; Gdtr.Base = (UINT32)(UINTN)Gdt;
Gdtr.Limit = (UINT16) (sizeof (mGdtTemplate) - 1); Gdtr.Limit = (UINT16)(sizeof (mGdtTemplate) - 1);
AsmWriteGdtr (&Gdtr); AsmWriteGdtr (&Gdtr);
// //

61
UefiCpuPkg/CpuDxe/CpuGdt.h
View File

@@ -21,48 +21,47 @@
// //
typedef struct _GDT_ENTRY { typedef struct _GDT_ENTRY {
UINT16 Limit15_0; UINT16 Limit15_0;
UINT16 Base15_0; UINT16 Base15_0;
UINT8 Base23_16; UINT8 Base23_16;
UINT8 Type; UINT8 Type;
UINT8 Limit19_16_and_flags; UINT8 Limit19_16_and_flags;
UINT8 Base31_24; UINT8 Base31_24;
} GDT_ENTRY; } GDT_ENTRY;
typedef typedef
struct _GDT_ENTRIES { struct _GDT_ENTRIES {
GDT_ENTRY Null; GDT_ENTRY Null;
GDT_ENTRY Linear; GDT_ENTRY Linear;
GDT_ENTRY LinearCode; GDT_ENTRY LinearCode;
GDT_ENTRY SysData; GDT_ENTRY SysData;
GDT_ENTRY SysCode; GDT_ENTRY SysCode;
GDT_ENTRY SysCode16; GDT_ENTRY SysCode16;
GDT_ENTRY LinearData64; GDT_ENTRY LinearData64;
GDT_ENTRY LinearCode64; GDT_ENTRY LinearCode64;
GDT_ENTRY Spare5; GDT_ENTRY Spare5;
} GDT_ENTRIES; } GDT_ENTRIES;
#pragma pack () #pragma pack ()
#define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null) #define NULL_SEL OFFSET_OF (GDT_ENTRIES, Null)
#define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear) #define LINEAR_SEL OFFSET_OF (GDT_ENTRIES, Linear)
#define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode)
#define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData)
#define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode)
#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16) #define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16)
#define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) #define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64)
#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) #define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)
#define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5)
#if defined (MDE_CPU_IA32) #if defined (MDE_CPU_IA32)
#define CPU_CODE_SEL LINEAR_CODE_SEL #define CPU_CODE_SEL LINEAR_CODE_SEL
#define CPU_DATA_SEL LINEAR_SEL #define CPU_DATA_SEL LINEAR_SEL
#elif defined (MDE_CPU_X64) #elif defined (MDE_CPU_X64)
#define CPU_CODE_SEL LINEAR_CODE64_SEL #define CPU_CODE_SEL LINEAR_CODE64_SEL
#define CPU_DATA_SEL LINEAR_DATA64_SEL #define CPU_DATA_SEL LINEAR_DATA64_SEL
#else #else
#error CPU type not supported for CPU GDT initialization! #error CPU type not supported for CPU GDT initialization!
#endif #endif
#endif // _CPU_GDT_H_ #endif // _CPU_GDT_H_

95
UefiCpuPkg/CpuDxe/CpuMp.c
View File

@@ -9,8 +9,8 @@
#include "CpuDxe.h" #include "CpuDxe.h"
#include "CpuMp.h" #include "CpuMp.h"
EFI_HANDLE mMpServiceHandle = NULL; EFI_HANDLE mMpServiceHandle = NULL;
UINTN mNumberOfProcessors = 1; UINTN mNumberOfProcessors = 1;
EFI_MP_SERVICES_PROTOCOL mMpServicesTemplate = { EFI_MP_SERVICES_PROTOCOL mMpServicesTemplate = {
GetNumberOfProcessors, GetNumberOfProcessors,
@@ -509,7 +509,7 @@ WhoAmI (
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
) )
{ {
return MpInitLibWhoAmI (ProcessorNumber);; return MpInitLibWhoAmI (ProcessorNumber);
} }
/** /**
@@ -547,8 +547,8 @@ CollectBistDataFromHob (
// Sec Platform Information2 PPI includes BSP/APs' BIST information // Sec Platform Information2 PPI includes BSP/APs' BIST information
// //
SecPlatformInformation2 = GET_GUID_HOB_DATA (GuidHob); SecPlatformInformation2 = GET_GUID_HOB_DATA (GuidHob);
NumberOfData = SecPlatformInformation2->NumberOfCpus; NumberOfData = SecPlatformInformation2->NumberOfCpus;
CpuInstance = SecPlatformInformation2->CpuInstance; CpuInstance = SecPlatformInformation2->CpuInstance;
} else { } else {
// //
// Otherwise, get gEfiSecPlatformInformationPpiGuid Guided HOB // Otherwise, get gEfiSecPlatformInformationPpiGuid Guided HOB
@@ -556,14 +556,14 @@ CollectBistDataFromHob (
GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid); GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
if (GuidHob != NULL) { if (GuidHob != NULL) {
SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob); SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob);
NumberOfData = 1; NumberOfData = 1;
// //
// SEC Platform Information only includes BSP's BIST information // SEC Platform Information only includes BSP's BIST information
// does not have BSP's APIC ID // does not have BSP's APIC ID
// //
BspCpuInstance.CpuLocation = GetApicId (); BspCpuInstance.CpuLocation = GetApicId ();
BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32;
CpuInstance = &BspCpuInstance; CpuInstance = &BspCpuInstance;
} else { } else {
DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n")); DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n"));
// //
@@ -583,6 +583,7 @@ CollectBistDataFromHob (
BistData = CpuInstance[CpuInstanceNumber].InfoRecord.IA32HealthFlags; BistData = CpuInstance[CpuInstanceNumber].InfoRecord.IA32HealthFlags;
} }
} }
if (BistData.Uint32 != 0) { if (BistData.Uint32 != 0) {
// //
// Report Status Code that self test is failed // Report Status Code that self test is failed
@@ -607,7 +608,7 @@ CollectBistDataFromHob (
VOID VOID
EFIAPI EFIAPI
GetGdtr ( GetGdtr (
IN OUT VOID *Buffer IN OUT VOID *Buffer
) )
{ {
AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);
@@ -625,12 +626,12 @@ GetGdtr (
VOID VOID
EFIAPI EFIAPI
InitializeExceptionStackSwitchHandlers ( InitializeExceptionStackSwitchHandlers (
IN OUT VOID *Buffer IN OUT VOID *Buffer
) )
{ {
CPU_EXCEPTION_INIT_DATA *EssData; CPU_EXCEPTION_INIT_DATA *EssData;
IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Idtr;
EFI_STATUS Status; EFI_STATUS Status;
EssData = Buffer; EssData = Buffer;
// //
@@ -638,9 +639,9 @@ InitializeExceptionStackSwitchHandlers (
// the AP's IDT is the same as BSP's IDT either. // the AP's IDT is the same as BSP's IDT either.
// //
AsmReadIdtr (&Idtr); AsmReadIdtr (&Idtr);
EssData->Ia32.IdtTable = (VOID *)Idtr.Base; EssData->Ia32.IdtTable = (VOID *)Idtr.Base;
EssData->Ia32.IdtTableSize = Idtr.Limit + 1; EssData->Ia32.IdtTableSize = Idtr.Limit + 1;
Status = InitializeCpuExceptionHandlersEx (NULL, EssData); Status = InitializeCpuExceptionHandlersEx (NULL, EssData);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -656,19 +657,19 @@ InitializeMpExceptionStackSwitchHandlers (
VOID VOID
) )
{ {
UINTN Index; UINTN Index;
UINTN Bsp; UINTN Bsp;
UINTN ExceptionNumber; UINTN ExceptionNumber;
UINTN OldGdtSize; UINTN OldGdtSize;
UINTN NewGdtSize; UINTN NewGdtSize;
UINTN NewStackSize; UINTN NewStackSize;
IA32_DESCRIPTOR Gdtr; IA32_DESCRIPTOR Gdtr;
CPU_EXCEPTION_INIT_DATA EssData; CPU_EXCEPTION_INIT_DATA EssData;
UINT8 *GdtBuffer; UINT8 *GdtBuffer;
UINT8 *StackTop; UINT8 *StackTop;
ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList); ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);
NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber; NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;
StackTop = AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors); StackTop = AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors);
ASSERT (StackTop != NULL); ASSERT (StackTop != NULL);
@@ -678,17 +679,17 @@ InitializeMpExceptionStackSwitchHandlers (
// The default exception handlers must have been initialized. Let's just skip // The default exception handlers must have been initialized. Let's just skip
// it in this method. // it in this method.
// //
EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV; EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV;
EssData.Ia32.InitDefaultHandlers = FALSE; EssData.Ia32.InitDefaultHandlers = FALSE;
EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList); EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);
EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber; EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber;
EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize); EssData.Ia32.KnownGoodStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
// //
// Initialize Gdtr to suppress incorrect compiler/analyzer warnings. // Initialize Gdtr to suppress incorrect compiler/analyzer warnings.
// //
Gdtr.Base = 0; Gdtr.Base = 0;
Gdtr.Limit = 0; Gdtr.Limit = 0;
MpInitLibWhoAmI (&Bsp); MpInitLibWhoAmI (&Bsp);
for (Index = 0; Index < mNumberOfProcessors; ++Index) { for (Index = 0; Index < mNumberOfProcessors; ++Index) {
@@ -733,7 +734,7 @@ InitializeMpExceptionStackSwitchHandlers (
// | | // | |
// -------------------------------- // --------------------------------
// //
OldGdtSize = Gdtr.Limit + 1; OldGdtSize = Gdtr.Limit + 1;
EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) * EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) *
(ExceptionNumber + 1); (ExceptionNumber + 1);
EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) * EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) *
@@ -749,19 +750,21 @@ InitializeMpExceptionStackSwitchHandlers (
// //
// Make sure GDT table alignment // Make sure GDT table alignment
// //
EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR)); EssData.Ia32.GdtTable = ALIGN_POINTER (GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));
NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer); NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);
EssData.Ia32.GdtTableSize = NewGdtSize; EssData.Ia32.GdtTableSize = NewGdtSize;
EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize); EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize);
EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize + EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize +
EssData.Ia32.ExceptionTssDescSize); EssData.Ia32.ExceptionTssDescSize);
EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop; EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;
DEBUG ((DEBUG_INFO, DEBUG ((
"Exception stack top[cpu%lu]: 0x%lX\n", DEBUG_INFO,
(UINT64)(UINTN)Index, "Exception stack top[cpu%lu]: 0x%lX\n",
(UINT64)(UINTN)StackTop)); (UINT64)(UINTN)Index,
(UINT64)(UINTN)StackTop
));
if (Index == Bsp) { if (Index == Bsp) {
InitializeExceptionStackSwitchHandlers (&EssData); InitializeExceptionStackSwitchHandlers (&EssData);
@@ -776,7 +779,7 @@ InitializeMpExceptionStackSwitchHandlers (
); );
} }
StackTop -= NewStackSize; StackTop -= NewStackSize;
} }
} }
@@ -815,9 +818,9 @@ InitializeMpSupport (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN NumberOfProcessors; UINTN NumberOfProcessors;
UINTN NumberOfEnabledProcessors; UINTN NumberOfEnabledProcessors;
// //
// Wakeup APs to do initialization // Wakeup APs to do initialization
@@ -841,9 +844,9 @@ InitializeMpSupport (
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&mMpServiceHandle, &mMpServiceHandle,
&gEfiMpServiceProtocolGuid, &mMpServicesTemplate, &gEfiMpServiceProtocolGuid,
&mMpServicesTemplate,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }

1
UefiCpuPkg/CpuDxe/CpuMp.h
View File

@@ -467,4 +467,3 @@ WhoAmI (
); );
#endif // _CPU_MP_H_ #endif // _CPU_MP_H_

559
UefiCpuPkg/CpuDxe/CpuPageTable.c
View File

File diff suppressed because it is too large Load Diff

45
UefiCpuPkg/CpuDxe/CpuPageTable.h
View File

@@ -19,19 +19,19 @@
#define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED BIT31 #define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED BIT31
// Other bits are reserved for future use // Other bits are reserved for future use
typedef struct { typedef struct {
UINT32 PageTableBase; UINT32 PageTableBase;
UINT32 Reserved; UINT32 Reserved;
UINT32 Attributes; UINT32 Attributes;
} PAGE_TABLE_LIB_PAGING_CONTEXT_IA32; } PAGE_TABLE_LIB_PAGING_CONTEXT_IA32;
typedef struct { typedef struct {
UINT64 PageTableBase; UINT64 PageTableBase;
UINT32 Attributes; UINT32 Attributes;
} PAGE_TABLE_LIB_PAGING_CONTEXT_X64; } PAGE_TABLE_LIB_PAGING_CONTEXT_X64;
typedef union { typedef union {
PAGE_TABLE_LIB_PAGING_CONTEXT_IA32 Ia32; PAGE_TABLE_LIB_PAGING_CONTEXT_IA32 Ia32;
PAGE_TABLE_LIB_PAGING_CONTEXT_X64 X64; PAGE_TABLE_LIB_PAGING_CONTEXT_X64 X64;
} PAGE_TABLE_LIB_PAGING_CONTEXT_DATA; } PAGE_TABLE_LIB_PAGING_CONTEXT_DATA;
typedef struct { typedef struct {
@@ -41,8 +41,8 @@ typedef struct {
// #define IMAGE_FILE_MACHINE_I386 0x014c // #define IMAGE_FILE_MACHINE_I386 0x014c
// #define IMAGE_FILE_MACHINE_X64 0x8664 // #define IMAGE_FILE_MACHINE_X64 0x8664
// //
UINT16 MachineType; UINT16 MachineType;
PAGE_TABLE_LIB_PAGING_CONTEXT_DATA ContextData; PAGE_TABLE_LIB_PAGING_CONTEXT_DATA ContextData;
} PAGE_TABLE_LIB_PAGING_CONTEXT; } PAGE_TABLE_LIB_PAGING_CONTEXT;
#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB #define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB
@@ -52,12 +52,11 @@ typedef struct {
(~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1)) (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
typedef struct { typedef struct {
VOID *NextPool; VOID *NextPool;
UINTN Offset; UINTN Offset;
UINTN FreePages; UINTN FreePages;
} PAGE_TABLE_POOL; } PAGE_TABLE_POOL;
/** /**
Allocates one or more 4KB pages for page table. Allocates one or more 4KB pages for page table.
@@ -68,7 +67,7 @@ typedef struct {
**/ **/
typedef typedef
VOID * VOID *
(EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES) ( (EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES)(
IN UINTN Pages IN UINTN Pages
); );
@@ -103,11 +102,11 @@ VOID *
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
AssignMemoryPageAttributes ( AssignMemoryPageAttributes (
IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL,
IN PHYSICAL_ADDRESS BaseAddress, IN PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes, IN UINT64 Attributes,
IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL
); );
/** /**
@@ -136,7 +135,7 @@ InitializePageTableLib (
VOID * VOID *
EFIAPI EFIAPI
AllocatePageTableMemory ( AllocatePageTableMemory (
IN UINTN Pages IN UINTN Pages
); );
/** /**
@@ -149,9 +148,9 @@ AllocatePageTableMemory (
**/ **/
VOID VOID
GetPagingDetails ( GetPagingDetails (
IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData,
OUT UINTN **PageTableBase OPTIONAL, OUT UINTN **PageTableBase OPTIONAL,
OUT UINT32 **Attributes OPTIONAL OUT UINT32 **Attributes OPTIONAL
); );
#endif #endif

9
UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c
View File

@@ -8,7 +8,6 @@
#include "CpuPageTable.h" #include "CpuPageTable.h"
/** /**
Get paging details. Get paging details.
@@ -19,16 +18,16 @@
**/ **/
VOID VOID
GetPagingDetails ( GetPagingDetails (
IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData,
OUT UINTN **PageTableBase OPTIONAL, OUT UINTN **PageTableBase OPTIONAL,
OUT UINT32 **Attributes OPTIONAL OUT UINT32 **Attributes OPTIONAL
) )
{ {
if (PageTableBase != NULL) { if (PageTableBase != NULL) {
*PageTableBase = &PagingContextData->Ia32.PageTableBase; *PageTableBase = &PagingContextData->Ia32.PageTableBase;
} }
if (Attributes != NULL) { if (Attributes != NULL) {
*Attributes = &PagingContextData->Ia32.Attributes; *Attributes = &PagingContextData->Ia32.Attributes;
} }
} }

9
UefiCpuPkg/CpuDxe/X64/PagingAttribute.c
View File

@@ -8,7 +8,6 @@
#include "CpuPageTable.h" #include "CpuPageTable.h"
/** /**
Get paging details. Get paging details.
@@ -19,16 +18,16 @@
**/ **/
VOID VOID
GetPagingDetails ( GetPagingDetails (
IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData,
OUT UINTN **PageTableBase OPTIONAL, OUT UINTN **PageTableBase OPTIONAL,
OUT UINT32 **Attributes OPTIONAL OUT UINT32 **Attributes OPTIONAL
) )
{ {
if (PageTableBase != NULL) { if (PageTableBase != NULL) {
*PageTableBase = &PagingContextData->X64.PageTableBase; *PageTableBase = &PagingContextData->X64.PageTableBase;
} }
if (Attributes != NULL) { if (Attributes != NULL) {
*Attributes = &PagingContextData->X64.Attributes; *Attributes = &PagingContextData->X64.Attributes;
} }
} }

18
UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
View File

@@ -18,7 +18,6 @@
#include <Protocol/SmmConfiguration.h> #include <Protocol/SmmConfiguration.h>
#include <Guid/CpuFeaturesInitDone.h> #include <Guid/CpuFeaturesInitDone.h>
/** /**
Worker function to perform CPU feature initialization. Worker function to perform CPU feature initialization.
@@ -28,8 +27,8 @@ CpuFeaturesInitializeWorker (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_HANDLE Handle; EFI_HANDLE Handle;
CpuFeaturesDetect (); CpuFeaturesDetect ();
@@ -57,12 +56,12 @@ CpuFeaturesInitializeWorker (
VOID VOID
EFIAPI EFIAPI
SmmConfigurationEventNotify ( SmmConfigurationEventNotify (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_SMM_CONFIGURATION_PROTOCOL *SmmConfiguration; EFI_SMM_CONFIGURATION_PROTOCOL *SmmConfiguration;
// //
// Make sure this notification is for this handler // Make sure this notification is for this handler
@@ -91,8 +90,8 @@ SmmConfigurationEventNotify (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
CpuFeaturesDxeInitialize ( CpuFeaturesDxeInitialize (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
VOID *Registration; VOID *Registration;
@@ -133,4 +132,3 @@ CpuFeaturesDxeInitialize (
return EFI_SUCCESS; return EFI_SUCCESS;
} }

14
UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c
View File

@@ -16,7 +16,7 @@
#include <Guid/CpuFeaturesInitDone.h> #include <Guid/CpuFeaturesInitDone.h>
EFI_PEI_PPI_DESCRIPTOR mPeiCpuFeaturesInitDonePpiDesc = { EFI_PEI_PPI_DESCRIPTOR mPeiCpuFeaturesInitDonePpiDesc = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiCpuFeaturesInitDoneGuid, &gEdkiiCpuFeaturesInitDoneGuid,
NULL NULL
@@ -40,14 +40,15 @@ CpuFeaturesPeimInitialize (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_BOOT_MODE BootMode; EFI_BOOT_MODE BootMode;
Status = PeiServicesGetBootMode (&BootMode); Status = PeiServicesGetBootMode (&BootMode);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
if (BootMode == BOOT_ON_S3_RESUME && if ((BootMode == BOOT_ON_S3_RESUME) &&
!PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) { !PcdGetBool (PcdCpuFeaturesInitOnS3Resume))
{
// //
// Does nothing when if PcdCpuFeaturesInitOnS3Resume is FLASE // Does nothing when if PcdCpuFeaturesInitOnS3Resume is FLASE
// on S3 boot mode // on S3 boot mode
@@ -62,7 +63,7 @@ CpuFeaturesPeimInitialize (
// //
// Install CPU Features Init Done PPI // Install CPU Features Init Done PPI
// //
Status = PeiServicesInstallPpi(&mPeiCpuFeaturesInitDonePpiDesc); Status = PeiServicesInstallPpi (&mPeiCpuFeaturesInitDonePpiDesc);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// //
@@ -72,4 +73,3 @@ CpuFeaturesPeimInitialize (
return EFI_SUCCESS; return EFI_SUCCESS;
} }

106
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
View File

@@ -18,7 +18,7 @@ EFI_HANDLE mHandle = NULL;
// //
// CPU I/O 2 Protocol instance // CPU I/O 2 Protocol instance
// //
EFI_CPU_IO2_PROTOCOL mCpuIo2 = { EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
{ {
CpuMemoryServiceRead, CpuMemoryServiceRead,
CpuMemoryServiceWrite CpuMemoryServiceWrite
@@ -32,7 +32,7 @@ EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
// //
// Lookup table for increment values based on transfer widths // Lookup table for increment values based on transfer widths
// //
UINT8 mInStride[] = { UINT8 mInStride[] = {
1, // EfiCpuIoWidthUint8 1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16 2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32 4, // EfiCpuIoWidthUint32
@@ -50,7 +50,7 @@ UINT8 mInStride[] = {
// //
// Lookup table for increment values based on transfer widths // Lookup table for increment values based on transfer widths
// //
UINT8 mOutStride[] = { UINT8 mOutStride[] = {
1, // EfiCpuIoWidthUint8 1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16 2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32 4, // EfiCpuIoWidthUint32
@@ -120,14 +120,14 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access, // For FIFO type, the target address won't increase during the access,
// so treat Count as 1 // so treat Count as 1
// //
if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) { if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
Count = 1; Count = 1;
} }
// //
// Check to see if Width is in the valid range for I/O Port operations // Check to see if Width is in the valid range for I/O Port operations
// //
Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) { if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -164,6 +164,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) { if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@@ -243,9 +244,9 @@ CpuMemoryServiceRead (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) { if (OperationWidth == EfiCpuIoWidthUint8) {
*Uint8Buffer = MmioRead8 ((UINTN)Address); *Uint8Buffer = MmioRead8 ((UINTN)Address);
@@ -257,6 +258,7 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -323,9 +325,9 @@ CpuMemoryServiceWrite (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) { if (OperationWidth == EfiCpuIoWidthUint8) {
MmioWrite8 ((UINTN)Address, *Uint8Buffer); MmioWrite8 ((UINTN)Address, *Uint8Buffer);
@@ -337,6 +339,7 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -403,31 +406,31 @@ CpuIoServiceRead (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
// //
// Fifo operations supported for (mInStride[Width] == 0) // Fifo operations supported for (mInStride[Width] == 0)
// //
if (InStride == 0) { if (InStride == 0) {
switch (OperationWidth) { switch (OperationWidth) {
case EfiCpuIoWidthUint8: case EfiCpuIoWidthUint8:
IoReadFifo8 ((UINTN)Address, Count, Buffer); IoReadFifo8 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
case EfiCpuIoWidthUint16: case EfiCpuIoWidthUint16:
IoReadFifo16 ((UINTN)Address, Count, Buffer); IoReadFifo16 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
case EfiCpuIoWidthUint32: case EfiCpuIoWidthUint32:
IoReadFifo32 ((UINTN)Address, Count, Buffer); IoReadFifo32 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
default: default:
// //
// The CpuIoCheckParameter call above will ensure that this // The CpuIoCheckParameter call above will ensure that this
// path is not taken. // path is not taken.
// //
ASSERT (FALSE); ASSERT (FALSE);
break; break;
} }
} }
@@ -510,31 +513,31 @@ CpuIoServiceWrite (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
// //
// Fifo operations supported for (mInStride[Width] == 0) // Fifo operations supported for (mInStride[Width] == 0)
// //
if (InStride == 0) { if (InStride == 0) {
switch (OperationWidth) { switch (OperationWidth) {
case EfiCpuIoWidthUint8: case EfiCpuIoWidthUint8:
IoWriteFifo8 ((UINTN)Address, Count, Buffer); IoWriteFifo8 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
case EfiCpuIoWidthUint16: case EfiCpuIoWidthUint16:
IoWriteFifo16 ((UINTN)Address, Count, Buffer); IoWriteFifo16 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
case EfiCpuIoWidthUint32: case EfiCpuIoWidthUint32:
IoWriteFifo32 ((UINTN)Address, Count, Buffer); IoWriteFifo32 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
default: default:
// //
// The CpuIoCheckParameter call above will ensure that this // The CpuIoCheckParameter call above will ensure that this
// path is not taken. // path is not taken.
// //
ASSERT (FALSE); ASSERT (FALSE);
break; break;
} }
} }
@@ -568,12 +571,13 @@ CpuIo2Initialize (
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&mHandle, &mHandle,
&gEfiCpuIo2ProtocolGuid, &mCpuIo2, &gEfiCpuIo2ProtocolGuid,
&mCpuIo2,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

2
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h
View File

@@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
#define MAX_IO_PORT_ADDRESS 0xFFFF #define MAX_IO_PORT_ADDRESS 0xFFFF
/** /**
Reads memory-mapped registers. Reads memory-mapped registers.

7
UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c
View File

@@ -16,7 +16,7 @@ EFI_HANDLE mHandle = NULL;
// //
// SMM CPU I/O Protocol instance // SMM CPU I/O Protocol instance
// //
EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2 = { EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2 = {
{ {
CpuMemoryServiceRead, CpuMemoryServiceRead,
CpuMemoryServiceWrite CpuMemoryServiceWrite
@@ -30,7 +30,7 @@ EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2 = {
// //
// Lookup table for increment values based on transfer widths // Lookup table for increment values based on transfer widths
// //
UINT8 mStride[] = { UINT8 mStride[] = {
1, // SMM_IO_UINT8 1, // SMM_IO_UINT8
2, // SMM_IO_UINT16 2, // SMM_IO_UINT16
4, // SMM_IO_UINT32 4, // SMM_IO_UINT32
@@ -112,6 +112,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) { if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@@ -184,6 +185,7 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -244,6 +246,7 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }

2
UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h
View File

@@ -19,7 +19,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MmServicesTableLib.h> #include <Library/MmServicesTableLib.h>
#include <Library/BaseMemoryLib.h> #include <Library/BaseMemoryLib.h>
#define MAX_IO_PORT_ADDRESS 0xFFFF #define MAX_IO_PORT_ADDRESS 0xFFFF
/** /**
Reads memory-mapped registers. Reads memory-mapped registers.

111
UefiCpuPkg/CpuIoPei/CpuIoPei.c
View File

@@ -43,7 +43,7 @@ EFI_PEI_CPU_IO_PPI gCpuIoPpi = {
// //
// PPI Descriptor used to install the CPU I/O PPI // PPI Descriptor used to install the CPU I/O PPI
// //
EFI_PEI_PPI_DESCRIPTOR gPpiList = { EFI_PEI_PPI_DESCRIPTOR gPpiList = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiCpuIoPpiInstalledGuid, &gEfiPeiCpuIoPpiInstalledGuid,
NULL NULL
@@ -52,7 +52,7 @@ EFI_PEI_PPI_DESCRIPTOR gPpiList = {
// //
// Lookup table for increment values based on transfer widths // Lookup table for increment values based on transfer widths
// //
UINT8 mInStride[] = { UINT8 mInStride[] = {
1, // EfiPeiCpuIoWidthUint8 1, // EfiPeiCpuIoWidthUint8
2, // EfiPeiCpuIoWidthUint16 2, // EfiPeiCpuIoWidthUint16
4, // EfiPeiCpuIoWidthUint32 4, // EfiPeiCpuIoWidthUint32
@@ -70,7 +70,7 @@ UINT8 mInStride[] = {
// //
// Lookup table for increment values based on transfer widths // Lookup table for increment values based on transfer widths
// //
UINT8 mOutStride[] = { UINT8 mOutStride[] = {
1, // EfiPeiCpuIoWidthUint8 1, // EfiPeiCpuIoWidthUint8
2, // EfiPeiCpuIoWidthUint16 2, // EfiPeiCpuIoWidthUint16
4, // EfiPeiCpuIoWidthUint32 4, // EfiPeiCpuIoWidthUint32
@@ -131,14 +131,14 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access, // For FIFO type, the target address won't increase during the access,
// so treat Count as 1 // so treat Count as 1
// //
if (Width >= EfiPeiCpuIoWidthFifoUint8 && Width <= EfiPeiCpuIoWidthFifoUint64) { if ((Width >= EfiPeiCpuIoWidthFifoUint8) && (Width <= EfiPeiCpuIoWidthFifoUint64)) {
Count = 1; Count = 1;
} }
// //
// Check to see if Width is in the valid range for I/O Port operations // Check to see if Width is in the valid range for I/O Port operations
// //
Width = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); Width = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
if (!MmioOperation && (Width == EfiPeiCpuIoWidthUint64)) { if (!MmioOperation && (Width == EfiPeiCpuIoWidthUint64)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -168,6 +168,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) { if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@@ -220,10 +221,10 @@ CpuMemoryServiceRead (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00); Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiPeiCpuIoWidthUint8) { if (OperationWidth == EfiPeiCpuIoWidthUint8) {
*Uint8Buffer = MmioRead8 ((UINTN)Address); *Uint8Buffer = MmioRead8 ((UINTN)Address);
@@ -247,6 +248,7 @@ CpuMemoryServiceRead (
} }
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -294,10 +296,10 @@ CpuMemoryServiceWrite (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00); Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiPeiCpuIoWidthUint8) { if (OperationWidth == EfiPeiCpuIoWidthUint8) {
MmioWrite8 ((UINTN)Address, *Uint8Buffer); MmioWrite8 ((UINTN)Address, *Uint8Buffer);
@@ -321,6 +323,7 @@ CpuMemoryServiceWrite (
} }
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -368,31 +371,31 @@ CpuIoServiceRead (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
// //
// Fifo operations supported for (mInStride[Width] == 0) // Fifo operations supported for (mInStride[Width] == 0)
// //
if (InStride == 0) { if (InStride == 0) {
switch (OperationWidth) { switch (OperationWidth) {
case EfiPeiCpuIoWidthUint8: case EfiPeiCpuIoWidthUint8:
IoReadFifo8 ((UINTN)Address, Count, Buffer); IoReadFifo8 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
case EfiPeiCpuIoWidthUint16: case EfiPeiCpuIoWidthUint16:
IoReadFifo16 ((UINTN)Address, Count, Buffer); IoReadFifo16 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
case EfiPeiCpuIoWidthUint32: case EfiPeiCpuIoWidthUint32:
IoReadFifo32 ((UINTN)Address, Count, Buffer); IoReadFifo32 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
default: default:
// //
// The CpuIoCheckParameter call above will ensure that this // The CpuIoCheckParameter call above will ensure that this
// path is not taken. // path is not taken.
// //
ASSERT (FALSE); ASSERT (FALSE);
break; break;
} }
} }
@@ -465,31 +468,31 @@ CpuIoServiceWrite (
// //
// Select loop based on the width of the transfer // Select loop based on the width of the transfer
// //
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);
// //
// Fifo operations supported for (mInStride[Width] == 0) // Fifo operations supported for (mInStride[Width] == 0)
// //
if (InStride == 0) { if (InStride == 0) {
switch (OperationWidth) { switch (OperationWidth) {
case EfiPeiCpuIoWidthUint8: case EfiPeiCpuIoWidthUint8:
IoWriteFifo8 ((UINTN)Address, Count, Buffer); IoWriteFifo8 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
case EfiPeiCpuIoWidthUint16: case EfiPeiCpuIoWidthUint16:
IoWriteFifo16 ((UINTN)Address, Count, Buffer); IoWriteFifo16 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
case EfiPeiCpuIoWidthUint32: case EfiPeiCpuIoWidthUint32:
IoWriteFifo32 ((UINTN)Address, Count, Buffer); IoWriteFifo32 ((UINTN)Address, Count, Buffer);
return EFI_SUCCESS; return EFI_SUCCESS;
default: default:
// //
// The CpuIoCheckParameter call above will ensure that this // The CpuIoCheckParameter call above will ensure that this
// path is not taken. // path is not taken.
// //
ASSERT (FALSE); ASSERT (FALSE);
break; break;
} }
} }
@@ -572,9 +575,9 @@ CpuIoRead16 (
UINT32 UINT32
EFIAPI EFIAPI
CpuIoRead32 ( CpuIoRead32 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
) )
{ {
return IoRead32 ((UINTN)Address); return IoRead32 ((UINTN)Address);

114
UefiCpuPkg/CpuIoPei/CpuIoPei.h
View File

@@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Library/PeiServicesLib.h> #include <Library/PeiServicesLib.h>
#define MAX_IO_PORT_ADDRESS 0xFFFF #define MAX_IO_PORT_ADDRESS 0xFFFF
/** /**
Reads memory-mapped registers. Reads memory-mapped registers.
@@ -149,9 +149,9 @@ CpuIoServiceWrite (
UINT8 UINT8
EFIAPI EFIAPI
CpuIoRead8 ( CpuIoRead8 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
); );
/** /**
@@ -168,9 +168,9 @@ CpuIoRead8 (
UINT16 UINT16
EFIAPI EFIAPI
CpuIoRead16 ( CpuIoRead16 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
); );
/** /**
@@ -187,9 +187,9 @@ CpuIoRead16 (
UINT32 UINT32
EFIAPI EFIAPI
CpuIoRead32 ( CpuIoRead32 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
); );
/** /**
@@ -206,9 +206,9 @@ CpuIoRead32 (
UINT64 UINT64
EFIAPI EFIAPI
CpuIoRead64 ( CpuIoRead64 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
); );
/** /**
@@ -224,10 +224,10 @@ CpuIoRead64 (
VOID VOID
EFIAPI EFIAPI
CpuIoWrite8 ( CpuIoWrite8 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address, IN UINT64 Address,
IN UINT8 Data IN UINT8 Data
); );
/** /**
@@ -243,10 +243,10 @@ CpuIoWrite8 (
VOID VOID
EFIAPI EFIAPI
CpuIoWrite16 ( CpuIoWrite16 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address, IN UINT64 Address,
IN UINT16 Data IN UINT16 Data
); );
/** /**
@@ -262,10 +262,10 @@ CpuIoWrite16 (
VOID VOID
EFIAPI EFIAPI
CpuIoWrite32 ( CpuIoWrite32 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address, IN UINT64 Address,
IN UINT32 Data IN UINT32 Data
); );
/** /**
@@ -281,10 +281,10 @@ CpuIoWrite32 (
VOID VOID
EFIAPI EFIAPI
CpuIoWrite64 ( CpuIoWrite64 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address, IN UINT64 Address,
IN UINT64 Data IN UINT64 Data
); );
/** /**
@@ -301,9 +301,9 @@ CpuIoWrite64 (
UINT8 UINT8
EFIAPI EFIAPI
CpuMemRead8 ( CpuMemRead8 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
); );
/** /**
@@ -320,9 +320,9 @@ CpuMemRead8 (
UINT16 UINT16
EFIAPI EFIAPI
CpuMemRead16 ( CpuMemRead16 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
); );
/** /**
@@ -339,9 +339,9 @@ CpuMemRead16 (
UINT32 UINT32
EFIAPI EFIAPI
CpuMemRead32 ( CpuMemRead32 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
); );
/** /**
@@ -358,9 +358,9 @@ CpuMemRead32 (
UINT64 UINT64
EFIAPI EFIAPI
CpuMemRead64 ( CpuMemRead64 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address IN UINT64 Address
); );
/** /**
@@ -376,10 +376,10 @@ CpuMemRead64 (
VOID VOID
EFIAPI EFIAPI
CpuMemWrite8 ( CpuMemWrite8 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address, IN UINT64 Address,
IN UINT8 Data IN UINT8 Data
); );
/** /**
@@ -395,10 +395,10 @@ CpuMemWrite8 (
VOID VOID
EFIAPI EFIAPI
CpuMemWrite16 ( CpuMemWrite16 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address, IN UINT64 Address,
IN UINT16 Data IN UINT16 Data
); );
/** /**
@@ -414,10 +414,10 @@ CpuMemWrite16 (
VOID VOID
EFIAPI EFIAPI
CpuMemWrite32 ( CpuMemWrite32 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address, IN UINT64 Address,
IN UINT32 Data IN UINT32 Data
); );
/** /**
@@ -433,10 +433,10 @@ CpuMemWrite32 (
VOID VOID
EFIAPI EFIAPI
CpuMemWrite64 ( CpuMemWrite64 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_PEI_CPU_IO_PPI *This, IN CONST EFI_PEI_CPU_IO_PPI *This,
IN UINT64 Address, IN UINT64 Address,
IN UINT64 Data IN UINT64 Data
); );
#endif #endif

91
UefiCpuPkg/CpuMpPei/CpuBist.c
View File

@@ -8,11 +8,11 @@
#include "CpuMpPei.h" #include "CpuMpPei.h"
EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2Ppi = { EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2Ppi = {
SecPlatformInformation2 SecPlatformInformation2
}; };
EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi = { EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi = {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiSecPlatformInformation2PpiGuid, &gEfiSecPlatformInformation2PpiGuid,
&mSecPlatformInformation2Ppi &mSecPlatformInformation2Ppi
@@ -33,14 +33,14 @@ EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SecPlatformInformation2 ( SecPlatformInformation2 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN OUT UINT64 *StructureSize, IN OUT UINT64 *StructureSize,
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2
) )
{ {
EFI_HOB_GUID_TYPE *GuidHob; EFI_HOB_GUID_TYPE *GuidHob;
VOID *DataInHob; VOID *DataInHob;
UINTN DataSize; UINTN DataSize;
GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformation2PpiGuid); GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformation2PpiGuid);
if (GuidHob == NULL) { if (GuidHob == NULL) {
@@ -54,12 +54,12 @@ SecPlatformInformation2 (
// //
// return the information from BistHob // return the information from BistHob
// //
if ((*StructureSize) < (UINT64) DataSize) { if ((*StructureSize) < (UINT64)DataSize) {
*StructureSize = (UINT64) DataSize; *StructureSize = (UINT64)DataSize;
return EFI_BUFFER_TOO_SMALL; return EFI_BUFFER_TOO_SMALL;
} }
*StructureSize = (UINT64) DataSize; *StructureSize = (UINT64)DataSize;
CopyMem (PlatformInformationRecord2, DataInHob, DataSize); CopyMem (PlatformInformationRecord2, DataInHob, DataSize);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -82,11 +82,11 @@ SecPlatformInformation2 (
**/ **/
EFI_STATUS EFI_STATUS
GetBistInfoFromPpi ( GetBistInfoFromPpi (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN CONST EFI_GUID *Guid, IN CONST EFI_GUID *Guid,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor,
OUT VOID **BistInformationData, OUT VOID **BistInformationData,
OUT UINT64 *BistInformationSize OPTIONAL OUT UINT64 *BistInformationSize OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@@ -110,15 +110,15 @@ GetBistInfoFromPpi (
// //
InformationSize = 0; InformationSize = 0;
SecPlatformInformation2 = NULL; SecPlatformInformation2 = NULL;
Status = SecPlatformInformation2Ppi->PlatformInformation2 ( Status = SecPlatformInformation2Ppi->PlatformInformation2 (
PeiServices, PeiServices,
&InformationSize, &InformationSize,
SecPlatformInformation2 SecPlatformInformation2
); );
if (Status == EFI_BUFFER_TOO_SMALL) { if (Status == EFI_BUFFER_TOO_SMALL) {
Status = PeiServicesAllocatePool ( Status = PeiServicesAllocatePool (
(UINTN) InformationSize, (UINTN)InformationSize,
(VOID **) &SecPlatformInformation2 (VOID **)&SecPlatformInformation2
); );
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
// //
@@ -134,6 +134,7 @@ GetBistInfoFromPpi (
if (BistInformationSize != NULL) { if (BistInformationSize != NULL) {
*BistInformationSize = InformationSize; *BistInformationSize = InformationSize;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
} }
@@ -154,7 +155,7 @@ GetBistInfoFromPpi (
**/ **/
VOID VOID
CollectBistDataFromPpi ( CollectBistDataFromPpi (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@@ -174,14 +175,13 @@ CollectBistDataFromPpi (
EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2; EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2;
EFI_SEC_PLATFORM_INFORMATION_CPU *CpuInstanceInHob; EFI_SEC_PLATFORM_INFORMATION_CPU *CpuInstanceInHob;
MpInitLibGetNumberOfProcessors (&NumberOfProcessors, &NumberOfEnabledProcessors);
MpInitLibGetNumberOfProcessors(&NumberOfProcessors, &NumberOfEnabledProcessors);
BistInformationSize = sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2) + BistInformationSize = sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2) +
sizeof (EFI_SEC_PLATFORM_INFORMATION_CPU) * NumberOfProcessors; sizeof (EFI_SEC_PLATFORM_INFORMATION_CPU) * NumberOfProcessors;
Status = PeiServicesAllocatePool ( Status = PeiServicesAllocatePool (
(UINTN) BistInformationSize, (UINTN)BistInformationSize,
(VOID **) &PlatformInformationRecord2 (VOID **)&PlatformInformationRecord2
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
PlatformInformationRecord2->NumberOfCpus = (UINT32)NumberOfProcessors; PlatformInformationRecord2->NumberOfCpus = (UINT32)NumberOfProcessors;
@@ -197,7 +197,7 @@ CollectBistDataFromPpi (
PeiServices, PeiServices,
&gEfiSecPlatformInformation2PpiGuid, &gEfiSecPlatformInformation2PpiGuid,
&SecInformationDescriptor, &SecInformationDescriptor,
(VOID *) &SecPlatformInformation2, (VOID *)&SecPlatformInformation2,
NULL NULL
); );
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
@@ -214,7 +214,7 @@ CollectBistDataFromPpi (
PeiServices, PeiServices,
&gEfiSecPlatformInformationPpiGuid, &gEfiSecPlatformInformationPpiGuid,
&SecInformationDescriptor, &SecInformationDescriptor,
(VOID *) &SecPlatformInformation, (VOID *)&SecPlatformInformation,
NULL NULL
); );
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
@@ -223,16 +223,17 @@ CollectBistDataFromPpi (
// SEC Platform Information only includes BSP's BIST information // SEC Platform Information only includes BSP's BIST information
// and does not have BSP's APIC ID // and does not have BSP's APIC ID
// //
BspCpuInstance.CpuLocation = GetInitialApicId (); BspCpuInstance.CpuLocation = GetInitialApicId ();
BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32;
CpuInstance = &BspCpuInstance; CpuInstance = &BspCpuInstance;
} else { } else {
DEBUG ((DEBUG_INFO, "Does not find any stored CPU BIST information from PPI!\n")); DEBUG ((DEBUG_INFO, "Does not find any stored CPU BIST information from PPI!\n"));
} }
} }
for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber ++) {
for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber++) {
MpInitLibGetProcessorInfo (ProcessorNumber, &ProcessorInfo, &BistData); MpInitLibGetProcessorInfo (ProcessorNumber, &ProcessorInfo, &BistData);
for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex ++) { for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex++) {
ASSERT (CpuInstance != NULL); ASSERT (CpuInstance != NULL);
if (ProcessorInfo.ProcessorId == CpuInstance[CpuIndex].CpuLocation) { if (ProcessorInfo.ProcessorId == CpuInstance[CpuIndex].CpuLocation) {
// //
@@ -241,6 +242,7 @@ CollectBistDataFromPpi (
BistData = CpuInstance[CpuIndex].InfoRecord.IA32HealthFlags; BistData = CpuInstance[CpuIndex].InfoRecord.IA32HealthFlags;
} }
} }
if (BistData.Uint32 != 0) { if (BistData.Uint32 != 0) {
// //
// Report Status Code that self test is failed // Report Status Code that self test is failed
@@ -250,12 +252,15 @@ CollectBistDataFromPpi (
(EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST) (EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST)
); );
} }
DEBUG ((DEBUG_INFO, " APICID - 0x%08x, BIST - 0x%08x\n",
(UINT32) ProcessorInfo.ProcessorId, DEBUG ((
BistData DEBUG_INFO,
)); " APICID - 0x%08x, BIST - 0x%08x\n",
CpuInstanceInHob = PlatformInformationRecord2->CpuInstance; (UINT32)ProcessorInfo.ProcessorId,
CpuInstanceInHob[ProcessorNumber].CpuLocation = (UINT32) ProcessorInfo.ProcessorId; BistData
));
CpuInstanceInHob = PlatformInformationRecord2->CpuInstance;
CpuInstanceInHob[ProcessorNumber].CpuLocation = (UINT32)ProcessorInfo.ProcessorId;
CpuInstanceInHob[ProcessorNumber].InfoRecord.IA32HealthFlags = BistData; CpuInstanceInHob[ProcessorNumber].InfoRecord.IA32HealthFlags = BistData;
} }
@@ -266,7 +271,7 @@ CollectBistDataFromPpi (
BuildGuidDataHob ( BuildGuidDataHob (
&gEfiSecPlatformInformation2PpiGuid, &gEfiSecPlatformInformation2PpiGuid,
PlatformInformationRecord2, PlatformInformationRecord2,
(UINTN) BistInformationSize (UINTN)BistInformationSize
); );
if (SecPlatformInformation2 != NULL) { if (SecPlatformInformation2 != NULL) {
@@ -285,6 +290,6 @@ CollectBistDataFromPpi (
// Install SecPlatformInformation2 PPI // Install SecPlatformInformation2 PPI
// //
Status = PeiServicesInstallPpi (&mPeiSecPlatformInformation2Ppi); Status = PeiServicesInstallPpi (&mPeiSecPlatformInformation2Ppi);
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR (Status);
} }
} }

51
UefiCpuPkg/CpuMpPei/CpuMp2Pei.c
View File

@@ -43,9 +43,9 @@
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EdkiiPeiGetNumberOfProcessors ( EdkiiPeiGetNumberOfProcessors (
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfProcessors,
OUT UINTN *NumberOfEnabledProcessors OUT UINTN *NumberOfEnabledProcessors
) )
{ {
if ((NumberOfProcessors == NULL) || (NumberOfEnabledProcessors == NULL)) { if ((NumberOfProcessors == NULL) || (NumberOfEnabledProcessors == NULL)) {
@@ -85,9 +85,9 @@ EdkiiPeiGetNumberOfProcessors (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EdkiiPeiGetProcessorInfo ( EdkiiPeiGetProcessorInfo (
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
) )
{ {
return MpInitLibGetProcessorInfo (ProcessorNumber, ProcessorInfoBuffer, NULL); return MpInitLibGetProcessorInfo (ProcessorNumber, ProcessorInfoBuffer, NULL);
@@ -157,11 +157,11 @@ EdkiiPeiGetProcessorInfo (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EdkiiPeiStartupAllAPs ( EdkiiPeiStartupAllAPs (
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
IN UINTN TimeoutInMicroSeconds, IN UINTN TimeoutInMicroSeconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
) )
{ {
return MpInitLibStartupAllAPs ( return MpInitLibStartupAllAPs (
@@ -221,11 +221,11 @@ EdkiiPeiStartupAllAPs (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EdkiiPeiStartupThisAP ( EdkiiPeiStartupThisAP (
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
) )
{ {
return MpInitLibStartupThisAP ( return MpInitLibStartupThisAP (
@@ -321,10 +321,10 @@ EdkiiPeiSwitchBSP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EdkiiPeiEnableDisableAP ( EdkiiPeiEnableDisableAP (
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL IN UINT32 *HealthFlag OPTIONAL
) )
{ {
return MpInitLibEnableDisableAP (ProcessorNumber, EnableAP, HealthFlag); return MpInitLibEnableDisableAP (ProcessorNumber, EnableAP, HealthFlag);
@@ -388,10 +388,10 @@ EdkiiPeiWhoAmI (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
EdkiiPeiStartupAllCPUs ( EdkiiPeiStartupAllCPUs (
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN TimeoutInMicroSeconds, IN UINTN TimeoutInMicroSeconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
) )
{ {
return MpInitLibStartupAllCPUs ( return MpInitLibStartupAllCPUs (
@@ -404,7 +404,7 @@ EdkiiPeiStartupAllCPUs (
// //
// CPU MP2 PPI to be installed // CPU MP2 PPI to be installed
// //
EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi = { EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi = {
EdkiiPeiGetNumberOfProcessors, EdkiiPeiGetNumberOfProcessors,
EdkiiPeiGetProcessorInfo, EdkiiPeiGetProcessorInfo,
EdkiiPeiStartupAllAPs, EdkiiPeiStartupAllAPs,
@@ -414,4 +414,3 @@ EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi = {
EdkiiPeiWhoAmI, EdkiiPeiWhoAmI,
EdkiiPeiStartupAllCPUs EdkiiPeiStartupAllCPUs
}; };

149
UefiCpuPkg/CpuMpPei/CpuMpPei.c
View File

@@ -8,12 +8,12 @@
#include "CpuMpPei.h" #include "CpuMpPei.h"
extern EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi; extern EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi;
// //
// CPU MP PPI to be installed // CPU MP PPI to be installed
// //
EFI_PEI_MP_SERVICES_PPI mMpServicesPpi = { EFI_PEI_MP_SERVICES_PPI mMpServicesPpi = {
PeiGetNumberOfProcessors, PeiGetNumberOfProcessors,
PeiGetProcessorInfo, PeiGetProcessorInfo,
PeiStartupAllAPs, PeiStartupAllAPs,
@@ -23,7 +23,7 @@ EFI_PEI_MP_SERVICES_PPI mMpServicesPpi = {
PeiWhoAmI, PeiWhoAmI,
}; };
EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiList[] = { EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiList[] = {
{ {
EFI_PEI_PPI_DESCRIPTOR_PPI, EFI_PEI_PPI_DESCRIPTOR_PPI,
&gEdkiiPeiMpServices2PpiGuid, &gEdkiiPeiMpServices2PpiGuid,
@@ -73,10 +73,10 @@ EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiList[] = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PeiGetNumberOfProcessors ( PeiGetNumberOfProcessors (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_PEI_MP_SERVICES_PPI *This,
OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfProcessors,
OUT UINTN *NumberOfEnabledProcessors OUT UINTN *NumberOfEnabledProcessors
) )
{ {
if ((NumberOfProcessors == NULL) || (NumberOfEnabledProcessors == NULL)) { if ((NumberOfProcessors == NULL) || (NumberOfEnabledProcessors == NULL)) {
@@ -193,12 +193,12 @@ PeiGetProcessorInfo (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PeiStartupAllAPs ( PeiStartupAllAPs (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_PEI_MP_SERVICES_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
IN UINTN TimeoutInMicroSeconds, IN UINTN TimeoutInMicroSeconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
) )
{ {
return MpInitLibStartupAllAPs ( return MpInitLibStartupAllAPs (
@@ -260,12 +260,12 @@ PeiStartupAllAPs (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PeiStartupThisAP ( PeiStartupThisAP (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_PEI_MP_SERVICES_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
) )
{ {
return MpInitLibStartupThisAP ( return MpInitLibStartupThisAP (
@@ -366,11 +366,11 @@ PeiSwitchBSP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PeiEnableDisableAP ( PeiEnableDisableAP (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_PEI_MP_SERVICES_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL IN UINT32 *HealthFlag OPTIONAL
) )
{ {
return MpInitLibEnableDisableAP (ProcessorNumber, EnableAP, HealthFlag); return MpInitLibEnableDisableAP (ProcessorNumber, EnableAP, HealthFlag);
@@ -423,7 +423,7 @@ PeiWhoAmI (
VOID VOID
EFIAPI EFIAPI
GetGdtr ( GetGdtr (
IN OUT VOID *Buffer IN OUT VOID *Buffer
) )
{ {
AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer); AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);
@@ -441,12 +441,12 @@ GetGdtr (
VOID VOID
EFIAPI EFIAPI
InitializeExceptionStackSwitchHandlers ( InitializeExceptionStackSwitchHandlers (
IN OUT VOID *Buffer IN OUT VOID *Buffer
) )
{ {
CPU_EXCEPTION_INIT_DATA *EssData; CPU_EXCEPTION_INIT_DATA *EssData;
IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Idtr;
EFI_STATUS Status; EFI_STATUS Status;
EssData = Buffer; EssData = Buffer;
// //
@@ -454,9 +454,9 @@ InitializeExceptionStackSwitchHandlers (
// the AP's IDT is the same as BSP's IDT either. // the AP's IDT is the same as BSP's IDT either.
// //
AsmReadIdtr (&Idtr); AsmReadIdtr (&Idtr);
EssData->Ia32.IdtTable = (VOID *)Idtr.Base; EssData->Ia32.IdtTable = (VOID *)Idtr.Base;
EssData->Ia32.IdtTableSize = Idtr.Limit + 1; EssData->Ia32.IdtTableSize = Idtr.Limit + 1;
Status = InitializeCpuExceptionHandlersEx (NULL, EssData); Status = InitializeCpuExceptionHandlersEx (NULL, EssData);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -472,58 +472,59 @@ InitializeMpExceptionStackSwitchHandlers (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Index; UINTN Index;
UINTN Bsp; UINTN Bsp;
UINTN ExceptionNumber; UINTN ExceptionNumber;
UINTN OldGdtSize; UINTN OldGdtSize;
UINTN NewGdtSize; UINTN NewGdtSize;
UINTN NewStackSize; UINTN NewStackSize;
IA32_DESCRIPTOR Gdtr; IA32_DESCRIPTOR Gdtr;
CPU_EXCEPTION_INIT_DATA EssData; CPU_EXCEPTION_INIT_DATA EssData;
UINT8 *GdtBuffer; UINT8 *GdtBuffer;
UINT8 *StackTop; UINT8 *StackTop;
UINTN NumberOfProcessors; UINTN NumberOfProcessors;
if (!PcdGetBool (PcdCpuStackGuard)) { if (!PcdGetBool (PcdCpuStackGuard)) {
return; return;
} }
MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL); MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);
MpInitLibWhoAmI (&Bsp); MpInitLibWhoAmI (&Bsp);
ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList); ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);
NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber; NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;
StackTop = AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfProcessors)); StackTop = AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfProcessors));
ASSERT(StackTop != NULL); ASSERT (StackTop != NULL);
if (StackTop == NULL) { if (StackTop == NULL) {
return; return;
} }
StackTop += NewStackSize * NumberOfProcessors; StackTop += NewStackSize * NumberOfProcessors;
// //
// The default exception handlers must have been initialized. Let's just skip // The default exception handlers must have been initialized. Let's just skip
// it in this method. // it in this method.
// //
EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV; EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV;
EssData.Ia32.InitDefaultHandlers = FALSE; EssData.Ia32.InitDefaultHandlers = FALSE;
EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList); EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);
EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber; EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber;
EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize); EssData.Ia32.KnownGoodStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize);
// //
// Initialize Gdtr to suppress incorrect compiler/analyzer warnings. // Initialize Gdtr to suppress incorrect compiler/analyzer warnings.
// //
Gdtr.Base = 0; Gdtr.Base = 0;
Gdtr.Limit = 0; Gdtr.Limit = 0;
for (Index = 0; Index < NumberOfProcessors; ++Index) { for (Index = 0; Index < NumberOfProcessors; ++Index) {
// //
// To support stack switch, we need to re-construct GDT but not IDT. // To support stack switch, we need to re-construct GDT but not IDT.
// //
if (Index == Bsp) { if (Index == Bsp) {
GetGdtr(&Gdtr); GetGdtr (&Gdtr);
} else { } else {
// //
// AP might have different size of GDT from BSP. // AP might have different size of GDT from BSP.
@@ -560,7 +561,7 @@ InitializeMpExceptionStackSwitchHandlers (
// | | // | |
// -------------------------------- // --------------------------------
// //
OldGdtSize = Gdtr.Limit + 1; OldGdtSize = Gdtr.Limit + 1;
EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) * EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) *
(ExceptionNumber + 1); (ExceptionNumber + 1);
EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) * EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) *
@@ -583,19 +584,21 @@ InitializeMpExceptionStackSwitchHandlers (
// //
// Make sure GDT table alignment // Make sure GDT table alignment
// //
EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR)); EssData.Ia32.GdtTable = ALIGN_POINTER (GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));
NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer); NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);
EssData.Ia32.GdtTableSize = NewGdtSize; EssData.Ia32.GdtTableSize = NewGdtSize;
EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize); EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize);
EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize + EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize +
EssData.Ia32.ExceptionTssDescSize); EssData.Ia32.ExceptionTssDescSize);
EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop; EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;
DEBUG ((DEBUG_INFO, DEBUG ((
"Exception stack top[cpu%lu]: 0x%lX\n", DEBUG_INFO,
(UINT64)(UINTN)Index, "Exception stack top[cpu%lu]: 0x%lX\n",
(UINT64)(UINTN)StackTop)); (UINT64)(UINTN)Index,
(UINT64)(UINTN)StackTop
));
if (Index == Bsp) { if (Index == Bsp) {
InitializeExceptionStackSwitchHandlers (&EssData); InitializeExceptionStackSwitchHandlers (&EssData);
@@ -610,7 +613,7 @@ InitializeMpExceptionStackSwitchHandlers (
); );
} }
StackTop -= NewStackSize; StackTop -= NewStackSize;
} }
} }
@@ -625,23 +628,23 @@ InitializeMpExceptionStackSwitchHandlers (
**/ **/
EFI_STATUS EFI_STATUS
InitializeCpuMpWorker ( InitializeCpuMpWorker (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_VECTOR_HANDOFF_INFO *VectorInfo; EFI_VECTOR_HANDOFF_INFO *VectorInfo;
EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi; EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;
// //
// Get Vector Hand-off Info PPI // Get Vector Hand-off Info PPI
// //
VectorInfo = NULL; VectorInfo = NULL;
Status = PeiServicesLocatePpi ( Status = PeiServicesLocatePpi (
&gEfiVectorHandoffInfoPpiGuid, &gEfiVectorHandoffInfoPpiGuid,
0, 0,
NULL, NULL,
(VOID **)&VectorHandoffInfoPpi (VOID **)&VectorHandoffInfoPpi
); );
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
VectorInfo = VectorHandoffInfoPpi->Info; VectorInfo = VectorHandoffInfoPpi->Info;
} }
@@ -672,7 +675,7 @@ InitializeCpuMpWorker (
// //
// Install CPU MP PPI // Install CPU MP PPI
// //
Status = PeiServicesInstallPpi(mPeiCpuMpPpiList); Status = PeiServicesInstallPpi (mPeiCpuMpPpiList);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return Status; return Status;
@@ -697,7 +700,7 @@ CpuMpPeimInit (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
// //
// For the sake of special initialization needing to be done right after // For the sake of special initialization needing to be done right after

54
UefiCpuPkg/CpuMpPei/CpuMpPei.h
View File

@@ -29,7 +29,7 @@
#include <Library/BaseMemoryLib.h> #include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc; extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc;
/** /**
This service retrieves the number of logical processor in the platform This service retrieves the number of logical processor in the platform
@@ -68,10 +68,10 @@ extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc;
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PeiGetNumberOfProcessors ( PeiGetNumberOfProcessors (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_PEI_MP_SERVICES_PPI *This,
OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfProcessors,
OUT UINTN *NumberOfEnabledProcessors OUT UINTN *NumberOfEnabledProcessors
); );
/** /**
@@ -175,12 +175,12 @@ PeiGetProcessorInfo (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PeiStartupAllAPs ( PeiStartupAllAPs (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_PEI_MP_SERVICES_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
IN UINTN TimeoutInMicroSeconds, IN UINTN TimeoutInMicroSeconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
); );
/** /**
@@ -232,12 +232,12 @@ PeiStartupAllAPs (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PeiStartupThisAP ( PeiStartupThisAP (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_PEI_MP_SERVICES_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
); );
/** /**
@@ -325,11 +325,11 @@ PeiSwitchBSP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PeiEnableDisableAP ( PeiEnableDisableAP (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_PEI_MP_SERVICES_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL IN UINT32 *HealthFlag OPTIONAL
); );
/** /**
@@ -375,7 +375,7 @@ PeiWhoAmI (
**/ **/
VOID VOID
CollectBistDataFromPpi ( CollectBistDataFromPpi (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
); );
/** /**
@@ -393,9 +393,9 @@ CollectBistDataFromPpi (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SecPlatformInformation2 ( SecPlatformInformation2 (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN OUT UINT64 *StructureSize, IN OUT UINT64 *StructureSize,
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2 OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2
); );
/** /**
@@ -421,7 +421,7 @@ MigrateGdt (
**/ **/
EFI_STATUS EFI_STATUS
InitializeCpuMpWorker ( InitializeCpuMpWorker (
IN CONST EFI_PEI_SERVICES **PeiServices IN CONST EFI_PEI_SERVICES **PeiServices
); );
/** /**

250
UefiCpuPkg/CpuMpPei/CpuPaging.c
View File

@@ -16,23 +16,23 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include "CpuMpPei.h" #include "CpuMpPei.h"
#define IA32_PG_P BIT0 #define IA32_PG_P BIT0
#define IA32_PG_RW BIT1 #define IA32_PG_RW BIT1
#define IA32_PG_U BIT2 #define IA32_PG_U BIT2
#define IA32_PG_A BIT5 #define IA32_PG_A BIT5
#define IA32_PG_D BIT6 #define IA32_PG_D BIT6
#define IA32_PG_PS BIT7 #define IA32_PG_PS BIT7
#define IA32_PG_NX BIT63 #define IA32_PG_NX BIT63
#define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P) #define PAGE_ATTRIBUTE_BITS (IA32_PG_RW | IA32_PG_P)
#define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U |\ #define PAGE_PROGATE_BITS (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U | \
PAGE_ATTRIBUTE_BITS) PAGE_ATTRIBUTE_BITS)
#define PAGING_PAE_INDEX_MASK 0x1FF #define PAGING_PAE_INDEX_MASK 0x1FF
#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
#define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull #define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull
typedef enum { typedef enum {
PageNone = 0, PageNone = 0,
@@ -45,19 +45,19 @@ typedef enum {
} PAGE_ATTRIBUTE; } PAGE_ATTRIBUTE;
typedef struct { typedef struct {
PAGE_ATTRIBUTE Attribute; PAGE_ATTRIBUTE Attribute;
UINT64 Length; UINT64 Length;
UINT64 AddressMask; UINT64 AddressMask;
UINTN AddressBitOffset; UINTN AddressBitOffset;
UINTN AddressBitLength; UINTN AddressBitLength;
} PAGE_ATTRIBUTE_TABLE; } PAGE_ATTRIBUTE_TABLE;
PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
{PageNone, 0, 0, 0, 0}, { PageNone, 0, 0, 0, 0 },
{Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9}, { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9 },
{Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9}, { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9 },
{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9}, { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9 },
{Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9}, { Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9 },
}; };
EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] = { EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[] = {
@@ -80,8 +80,8 @@ IsIa32PaeSupported (
VOID VOID
) )
{ {
UINT32 RegEax; UINT32 RegEax;
CPUID_VERSION_INFO_EDX RegEdx; CPUID_VERSION_INFO_EDX RegEdx;
AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);
if (RegEax >= CPUID_VERSION_INFO) { if (RegEax >= CPUID_VERSION_INFO) {
@@ -104,14 +104,14 @@ IsIa32PaeSupported (
**/ **/
VOID * VOID *
AllocatePageTableMemory ( AllocatePageTableMemory (
IN UINTN Pages IN UINTN Pages
) )
{ {
VOID *Address; VOID *Address;
Address = AllocatePages(Pages); Address = AllocatePages (Pages);
if (Address != NULL) { if (Address != NULL) {
ZeroMem(Address, EFI_PAGES_TO_SIZE (Pages)); ZeroMem (Address, EFI_PAGES_TO_SIZE (Pages));
} }
return Address; return Address;
@@ -129,13 +129,13 @@ GetPhysicalAddressWidth (
VOID VOID
) )
{ {
UINT32 RegEax; UINT32 RegEax;
if (sizeof(UINTN) == 4) { if (sizeof (UINTN) == 4) {
return 32; return 32;
} }
AsmCpuid(CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) { if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL);
RegEax &= 0xFF; RegEax &= 0xFF;
@@ -161,7 +161,7 @@ GetPageTableTopLevelType (
VOID VOID
) )
{ {
MSR_IA32_EFER_REGISTER MsrEfer; MSR_IA32_EFER_REGISTER MsrEfer;
MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER); MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
@@ -178,19 +178,19 @@ GetPageTableTopLevelType (
**/ **/
VOID * VOID *
GetPageTableEntry ( GetPageTableEntry (
IN PHYSICAL_ADDRESS Address, IN PHYSICAL_ADDRESS Address,
OUT PAGE_ATTRIBUTE *PageAttribute OUT PAGE_ATTRIBUTE *PageAttribute
) )
{ {
INTN Level; INTN Level;
UINTN Index; UINTN Index;
UINT64 *PageTable; UINT64 *PageTable;
UINT64 AddressEncMask; UINT64 AddressEncMask;
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
PageTable = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); PageTable = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
for (Level = (INTN)GetPageTableTopLevelType (); Level > 0; --Level) { for (Level = (INTN)GetPageTableTopLevelType (); Level > 0; --Level) {
Index = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset); Index = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset);
Index &= PAGING_PAE_INDEX_MASK; Index &= PAGING_PAE_INDEX_MASK;
// //
@@ -204,7 +204,7 @@ GetPageTableEntry (
// //
// Page memory? // Page memory?
// //
if ((PageTable[Index] & IA32_PG_PS) != 0 || Level == PageMin) { if (((PageTable[Index] & IA32_PG_PS) != 0) || (Level == PageMin)) {
*PageAttribute = (PAGE_ATTRIBUTE)Level; *PageAttribute = (PAGE_ATTRIBUTE)Level;
return &PageTable[Index]; return &PageTable[Index];
} }
@@ -235,19 +235,19 @@ GetPageTableEntry (
**/ **/
RETURN_STATUS RETURN_STATUS
SplitPage ( SplitPage (
IN UINT64 *PageEntry, IN UINT64 *PageEntry,
IN PAGE_ATTRIBUTE PageAttribute, IN PAGE_ATTRIBUTE PageAttribute,
IN PAGE_ATTRIBUTE SplitAttribute, IN PAGE_ATTRIBUTE SplitAttribute,
IN BOOLEAN Recursively IN BOOLEAN Recursively
) )
{ {
UINT64 BaseAddress; UINT64 BaseAddress;
UINT64 *NewPageEntry; UINT64 *NewPageEntry;
UINTN Index; UINTN Index;
UINT64 AddressEncMask; UINT64 AddressEncMask;
PAGE_ATTRIBUTE SplitTo; PAGE_ATTRIBUTE SplitTo;
if (SplitAttribute == PageNone || SplitAttribute >= PageAttribute) { if ((SplitAttribute == PageNone) || (SplitAttribute >= PageAttribute)) {
ASSERT (SplitAttribute != PageNone); ASSERT (SplitAttribute != PageNone);
ASSERT (SplitAttribute < PageAttribute); ASSERT (SplitAttribute < PageAttribute);
return RETURN_INVALID_PARAMETER; return RETURN_INVALID_PARAMETER;
@@ -262,13 +262,13 @@ SplitPage (
// //
// One level down each step to achieve more compact page table. // One level down each step to achieve more compact page table.
// //
SplitTo = PageAttribute - 1; SplitTo = PageAttribute - 1;
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
mPageAttributeTable[SplitTo].AddressMask; mPageAttributeTable[SplitTo].AddressMask;
BaseAddress = *PageEntry & BaseAddress = *PageEntry &
~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
mPageAttributeTable[PageAttribute].AddressMask; mPageAttributeTable[PageAttribute].AddressMask;
for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = BaseAddress | AddressEncMask | NewPageEntry[Index] = BaseAddress | AddressEncMask |
((*PageEntry) & PAGE_PROGATE_BITS); ((*PageEntry) & PAGE_PROGATE_BITS);
@@ -276,7 +276,7 @@ SplitPage (
NewPageEntry[Index] |= IA32_PG_PS; NewPageEntry[Index] |= IA32_PG_PS;
} }
if (Recursively && SplitTo > SplitAttribute) { if (Recursively && (SplitTo > SplitAttribute)) {
SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively); SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively);
} }
@@ -313,20 +313,20 @@ SplitPage (
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
ConvertMemoryPageAttributes ( ConvertMemoryPageAttributes (
IN PHYSICAL_ADDRESS BaseAddress, IN PHYSICAL_ADDRESS BaseAddress,
IN UINT64 Length, IN UINT64 Length,
IN UINT64 Attributes IN UINT64 Attributes
) )
{ {
UINT64 *PageEntry; UINT64 *PageEntry;
PAGE_ATTRIBUTE PageAttribute; PAGE_ATTRIBUTE PageAttribute;
RETURN_STATUS Status; RETURN_STATUS Status;
EFI_PHYSICAL_ADDRESS MaximumAddress; EFI_PHYSICAL_ADDRESS MaximumAddress;
if (Length == 0 ||
(BaseAddress & (SIZE_4KB - 1)) != 0 ||
(Length & (SIZE_4KB - 1)) != 0) {
if ((Length == 0) ||
((BaseAddress & (SIZE_4KB - 1)) != 0) ||
((Length & (SIZE_4KB - 1)) != 0))
{
ASSERT (Length > 0); ASSERT (Length > 0);
ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0); ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
ASSERT ((Length & (SIZE_4KB - 1)) == 0); ASSERT ((Length & (SIZE_4KB - 1)) == 0);
@@ -335,9 +335,10 @@ ConvertMemoryPageAttributes (
} }
MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32; MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32;
if (BaseAddress > MaximumAddress || if ((BaseAddress > MaximumAddress) ||
Length > MaximumAddress || (Length > MaximumAddress) ||
(BaseAddress > MaximumAddress - (Length - 1))) { (BaseAddress > MaximumAddress - (Length - 1)))
{
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
@@ -355,6 +356,7 @@ ConvertMemoryPageAttributes (
if (RETURN_ERROR (Status)) { if (RETURN_ERROR (Status)) {
return Status; return Status;
} }
// //
// Do it again until the page is 4K. // Do it again until the page is 4K.
// //
@@ -374,7 +376,7 @@ ConvertMemoryPageAttributes (
// Convert success, move to next // Convert success, move to next
// //
BaseAddress += SIZE_4KB; BaseAddress += SIZE_4KB;
Length -= SIZE_4KB; Length -= SIZE_4KB;
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;
@@ -394,8 +396,8 @@ GetMaxMemoryPage (
IN PAGE_ATTRIBUTE TopLevelType IN PAGE_ATTRIBUTE TopLevelType
) )
{ {
UINT32 RegEax; UINT32 RegEax;
UINT32 RegEdx; UINT32 RegEdx;
if (TopLevelType == Page512G) { if (TopLevelType == Page512G) {
AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
@@ -421,31 +423,31 @@ CreatePageTable (
VOID VOID
) )
{ {
RETURN_STATUS Status; RETURN_STATUS Status;
UINTN PhysicalAddressBits; UINTN PhysicalAddressBits;
UINTN NumberOfEntries; UINTN NumberOfEntries;
PAGE_ATTRIBUTE TopLevelPageAttr; PAGE_ATTRIBUTE TopLevelPageAttr;
UINTN PageTable; UINTN PageTable;
PAGE_ATTRIBUTE MaxMemoryPage; PAGE_ATTRIBUTE MaxMemoryPage;
UINTN Index; UINTN Index;
UINT64 AddressEncMask; UINT64 AddressEncMask;
UINT64 *PageEntry; UINT64 *PageEntry;
EFI_PHYSICAL_ADDRESS PhysicalAddress; EFI_PHYSICAL_ADDRESS PhysicalAddress;
TopLevelPageAttr = (PAGE_ATTRIBUTE)GetPageTableTopLevelType (); TopLevelPageAttr = (PAGE_ATTRIBUTE)GetPageTableTopLevelType ();
PhysicalAddressBits = GetPhysicalAddressWidth (); PhysicalAddressBits = GetPhysicalAddressWidth ();
NumberOfEntries = (UINTN)1 << (PhysicalAddressBits - NumberOfEntries = (UINTN)1 << (PhysicalAddressBits -
mPageAttributeTable[TopLevelPageAttr].AddressBitOffset); mPageAttributeTable[TopLevelPageAttr].AddressBitOffset);
PageTable = (UINTN) AllocatePageTableMemory (1); PageTable = (UINTN)AllocatePageTableMemory (1);
if (PageTable == 0) { if (PageTable == 0) {
return 0; return 0;
} }
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
AddressEncMask &= mPageAttributeTable[TopLevelPageAttr].AddressMask; AddressEncMask &= mPageAttributeTable[TopLevelPageAttr].AddressMask;
MaxMemoryPage = GetMaxMemoryPage (TopLevelPageAttr); MaxMemoryPage = GetMaxMemoryPage (TopLevelPageAttr);
PageEntry = (UINT64 *)PageTable; PageEntry = (UINT64 *)PageTable;
PhysicalAddress = 0; PhysicalAddress = 0;
for (Index = 0; Index < NumberOfEntries; ++Index) { for (Index = 0; Index < NumberOfEntries; ++Index) {
@@ -455,7 +457,7 @@ CreatePageTable (
// Split the top page table down to the maximum page size supported // Split the top page table down to the maximum page size supported
// //
if (MaxMemoryPage < TopLevelPageAttr) { if (MaxMemoryPage < TopLevelPageAttr) {
Status = SplitPage(PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE); Status = SplitPage (PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -466,11 +468,10 @@ CreatePageTable (
*PageEntry &= ~(UINT64)(IA32_PG_RW | IA32_PG_U); *PageEntry &= ~(UINT64)(IA32_PG_RW | IA32_PG_U);
} }
PageEntry += 1; PageEntry += 1;
PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length; PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length;
} }
return PageTable; return PageTable;
} }
@@ -483,12 +484,12 @@ EnablePaging (
VOID VOID
) )
{ {
UINTN PageTable; UINTN PageTable;
PageTable = CreatePageTable (); PageTable = CreatePageTable ();
ASSERT (PageTable != 0); ASSERT (PageTable != 0);
if (PageTable != 0) { if (PageTable != 0) {
AsmWriteCr3(PageTable); AsmWriteCr3 (PageTable);
AsmWriteCr4 (AsmReadCr4 () | BIT5); // CR4.PAE AsmWriteCr4 (AsmReadCr4 () | BIT5); // CR4.PAE
AsmWriteCr0 (AsmReadCr0 () | BIT31); // CR0.PG AsmWriteCr0 (AsmReadCr0 () | BIT31); // CR0.PG
} }
@@ -509,15 +510,15 @@ EnablePaging (
VOID VOID
EFIAPI EFIAPI
GetStackBase ( GetStackBase (
IN OUT VOID *Buffer IN OUT VOID *Buffer
) )
{ {
EFI_PHYSICAL_ADDRESS StackBase; EFI_PHYSICAL_ADDRESS StackBase;
StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase; StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase;
StackBase += BASE_4KB; StackBase += BASE_4KB;
StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1); StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1);
StackBase -= PcdGet32(PcdCpuApStackSize); StackBase -= PcdGet32 (PcdCpuApStackSize);
*(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase; *(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase;
} }
@@ -532,21 +533,21 @@ SetupStackGuardPage (
VOID VOID
) )
{ {
EFI_PEI_HOB_POINTERS Hob; EFI_PEI_HOB_POINTERS Hob;
EFI_PHYSICAL_ADDRESS StackBase; EFI_PHYSICAL_ADDRESS StackBase;
UINTN NumberOfProcessors; UINTN NumberOfProcessors;
UINTN Bsp; UINTN Bsp;
UINTN Index; UINTN Index;
// //
// One extra page at the bottom of the stack is needed for Guard page. // One extra page at the bottom of the stack is needed for Guard page.
// //
if (PcdGet32(PcdCpuApStackSize) <= EFI_PAGE_SIZE) { if (PcdGet32 (PcdCpuApStackSize) <= EFI_PAGE_SIZE) {
DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n")); DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n"));
ASSERT (FALSE); ASSERT (FALSE);
} }
MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL); MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);
MpInitLibWhoAmI (&Bsp); MpInitLibWhoAmI (&Bsp);
for (Index = 0; Index < NumberOfProcessors; ++Index) { for (Index = 0; Index < NumberOfProcessors; ++Index) {
StackBase = 0; StackBase = 0;
@@ -554,26 +555,35 @@ SetupStackGuardPage (
if (Index == Bsp) { if (Index == Bsp) {
Hob.Raw = GetHobList (); Hob.Raw = GetHobList ();
while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) { while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {
if (CompareGuid (&gEfiHobMemoryAllocStackGuid, if (CompareGuid (
&(Hob.MemoryAllocationStack->AllocDescriptor.Name))) { &gEfiHobMemoryAllocStackGuid,
&(Hob.MemoryAllocationStack->AllocDescriptor.Name)
))
{
StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress; StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress;
break; break;
} }
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
} }
} else { } else {
// //
// Ask AP to return is stack base address. // Ask AP to return is stack base address.
// //
MpInitLibStartupThisAP(GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL); MpInitLibStartupThisAP (GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);
} }
ASSERT (StackBase != 0); ASSERT (StackBase != 0);
// //
// Set Guard page at stack base address. // Set Guard page at stack base address.
// //
ConvertMemoryPageAttributes(StackBase, EFI_PAGE_SIZE, 0); ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0);
DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n", DEBUG ((
(UINT64)StackBase, (UINT64)Index)); DEBUG_INFO,
"Stack Guard set at %lx [cpu%lu]!\n",
(UINT64)StackBase,
(UINT64)Index
));
} }
// //
@@ -614,13 +624,13 @@ MemoryDiscoveredPpiNotifyCallback (
// the task switch (for the sake of stack switch). // the task switch (for the sake of stack switch).
// //
InitStackGuard = FALSE; InitStackGuard = FALSE;
Hob.Raw = NULL; Hob.Raw = NULL;
if (IsIa32PaeSupported ()) { if (IsIa32PaeSupported ()) {
Hob.Raw = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid); Hob.Raw = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid);
InitStackGuard = PcdGetBool (PcdCpuStackGuard); InitStackGuard = PcdGetBool (PcdCpuStackGuard);
} }
if (InitStackGuard || Hob.Raw != NULL) { if (InitStackGuard || (Hob.Raw != NULL)) {
EnablePaging (); EnablePaging ();
} }
@@ -643,8 +653,8 @@ MemoryDiscoveredPpiNotifyCallback (
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw); Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw);
} }
CpuFlushTlb (); CpuFlushTlb ();
return Status; return Status;
} }

77
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
View File

@@ -34,10 +34,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Data structure used to allocate ACPI_CPU_DATA and its supporting structures // Data structure used to allocate ACPI_CPU_DATA and its supporting structures
// //
typedef struct { typedef struct {
ACPI_CPU_DATA AcpiCpuData; ACPI_CPU_DATA AcpiCpuData;
MTRR_SETTINGS MtrrTable; MTRR_SETTINGS MtrrTable;
IA32_DESCRIPTOR GdtrProfile; IA32_DESCRIPTOR GdtrProfile;
IA32_DESCRIPTOR IdtrProfile; IA32_DESCRIPTOR IdtrProfile;
} ACPI_CPU_DATA_EX; } ACPI_CPU_DATA_EX;
/** /**
@@ -57,12 +57,12 @@ AllocateAcpiNvsMemory (
EFI_STATUS Status; EFI_STATUS Status;
VOID *Buffer; VOID *Buffer;
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateAnyPages, AllocateAnyPages,
EfiACPIMemoryNVS, EfiACPIMemoryNVS,
EFI_SIZE_TO_PAGES (Size), EFI_SIZE_TO_PAGES (Size),
&Address &Address
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return NULL; return NULL;
} }
@@ -86,7 +86,7 @@ AllocateZeroPages (
IN UINTN Size IN UINTN Size
) )
{ {
VOID *Buffer; VOID *Buffer;
Buffer = AllocatePages (EFI_SIZE_TO_PAGES (Size)); Buffer = AllocatePages (EFI_SIZE_TO_PAGES (Size));
if (Buffer != NULL) { if (Buffer != NULL) {
@@ -95,6 +95,7 @@ AllocateZeroPages (
return Buffer; return Buffer;
} }
/** /**
Callback function executed when the EndOfDxe event group is signaled. Callback function executed when the EndOfDxe event group is signaled.
@@ -110,20 +111,20 @@ CpuS3DataOnEndOfDxe (
OUT VOID *Context OUT VOID *Context
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
ACPI_CPU_DATA_EX *AcpiCpuDataEx; ACPI_CPU_DATA_EX *AcpiCpuDataEx;
AcpiCpuDataEx = (ACPI_CPU_DATA_EX *) Context; AcpiCpuDataEx = (ACPI_CPU_DATA_EX *)Context;
// //
// Allocate a 4KB reserved page below 1MB // Allocate a 4KB reserved page below 1MB
// //
AcpiCpuDataEx->AcpiCpuData.StartupVector = BASE_1MB - 1; AcpiCpuDataEx->AcpiCpuData.StartupVector = BASE_1MB - 1;
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
EfiReservedMemoryType, EfiReservedMemoryType,
1, 1,
&AcpiCpuDataEx->AcpiCpuData.StartupVector &AcpiCpuDataEx->AcpiCpuData.StartupVector
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_VERBOSE, "%a\n", __FUNCTION__)); DEBUG ((DEBUG_VERBOSE, "%a\n", __FUNCTION__));
@@ -158,19 +159,19 @@ CpuS3DataInitialize (
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
ACPI_CPU_DATA_EX *AcpiCpuDataEx; ACPI_CPU_DATA_EX *AcpiCpuDataEx;
ACPI_CPU_DATA *AcpiCpuData; ACPI_CPU_DATA *AcpiCpuData;
EFI_MP_SERVICES_PROTOCOL *MpServices; EFI_MP_SERVICES_PROTOCOL *MpServices;
UINTN NumberOfCpus; UINTN NumberOfCpus;
UINTN NumberOfEnabledProcessors; UINTN NumberOfEnabledProcessors;
VOID *Stack; VOID *Stack;
UINTN GdtSize; UINTN GdtSize;
UINTN IdtSize; UINTN IdtSize;
VOID *Gdt; VOID *Gdt;
VOID *Idt; VOID *Idt;
EFI_EVENT Event; EFI_EVENT Event;
ACPI_CPU_DATA *OldAcpiCpuData; ACPI_CPU_DATA *OldAcpiCpuData;
if (!PcdGetBool (PcdAcpiS3Enable)) { if (!PcdGetBool (PcdAcpiS3Enable)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@@ -179,7 +180,7 @@ CpuS3DataInitialize (
// //
// Set PcdCpuS3DataAddress to the base address of the ACPI_CPU_DATA structure // Set PcdCpuS3DataAddress to the base address of the ACPI_CPU_DATA structure
// //
OldAcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress); OldAcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);
AcpiCpuDataEx = AllocateZeroPages (sizeof (ACPI_CPU_DATA_EX)); AcpiCpuDataEx = AllocateZeroPages (sizeof (ACPI_CPU_DATA_EX));
ASSERT (AcpiCpuDataEx != NULL); ASSERT (AcpiCpuDataEx != NULL);
@@ -212,9 +213,9 @@ CpuS3DataInitialize (
AcpiCpuData->StackSize = PcdGet32 (PcdCpuApStackSize); AcpiCpuData->StackSize = PcdGet32 (PcdCpuApStackSize);
AcpiCpuData->ApMachineCheckHandlerBase = 0; AcpiCpuData->ApMachineCheckHandlerBase = 0;
AcpiCpuData->ApMachineCheckHandlerSize = 0; AcpiCpuData->ApMachineCheckHandlerSize = 0;
AcpiCpuData->GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->GdtrProfile; AcpiCpuData->GdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->GdtrProfile;
AcpiCpuData->IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->IdtrProfile; AcpiCpuData->IdtrProfile = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->IdtrProfile;
AcpiCpuData->MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->MtrrTable; AcpiCpuData->MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->MtrrTable;
// //
// Allocate stack space for all CPUs. // Allocate stack space for all CPUs.
@@ -238,7 +239,7 @@ CpuS3DataInitialize (
// //
GdtSize = AcpiCpuDataEx->GdtrProfile.Limit + 1; GdtSize = AcpiCpuDataEx->GdtrProfile.Limit + 1;
IdtSize = AcpiCpuDataEx->IdtrProfile.Limit + 1; IdtSize = AcpiCpuDataEx->IdtrProfile.Limit + 1;
Gdt = AllocateZeroPages (GdtSize + IdtSize); Gdt = AllocateZeroPages (GdtSize + IdtSize);
ASSERT (Gdt != NULL); ASSERT (Gdt != NULL);
Idt = (VOID *)((UINTN)Gdt + GdtSize); Idt = (VOID *)((UINTN)Gdt + GdtSize);
CopyMem (Gdt, (VOID *)AcpiCpuDataEx->GdtrProfile.Base, GdtSize); CopyMem (Gdt, (VOID *)AcpiCpuDataEx->GdtrProfile.Base, GdtSize);

60
UefiCpuPkg/Include/AcpiCpuData.h
View File

@@ -52,19 +52,19 @@ typedef struct {
// //
// Record the package count in this CPU. // Record the package count in this CPU.
// //
UINT32 PackageCount; UINT32 PackageCount;
// //
// Record the max core count in this CPU. // Record the max core count in this CPU.
// Different packages may have different core count, this value // Different packages may have different core count, this value
// save the max core count in all the packages. // save the max core count in all the packages.
// //
UINT32 MaxCoreCount; UINT32 MaxCoreCount;
// //
// Record the max thread count in this CPU. // Record the max thread count in this CPU.
// Different cores may have different thread count, this value // Different cores may have different thread count, this value
// save the max thread count in all the cores. // save the max thread count in all the cores.
// //
UINT32 MaxThreadCount; UINT32 MaxThreadCount;
// //
// This field points to an array. // This field points to an array.
// This array saves thread count (type UINT32) of each package. // This array saves thread count (type UINT32) of each package.
@@ -74,7 +74,7 @@ typedef struct {
// therefore it doesn't need the dependency semaphores, it should set // therefore it doesn't need the dependency semaphores, it should set
// this field to 0. // this field to 0.
// //
EFI_PHYSICAL_ADDRESS ThreadCountPerPackage; EFI_PHYSICAL_ADDRESS ThreadCountPerPackage;
// //
// This field points to an array. // This field points to an array.
// This array saves thread count (type UINT8) of each core. // This array saves thread count (type UINT8) of each core.
@@ -84,21 +84,21 @@ typedef struct {
// therefore it doesn't need the dependency semaphores, it should set // therefore it doesn't need the dependency semaphores, it should set
// this field to 0. // this field to 0.
// //
EFI_PHYSICAL_ADDRESS ThreadCountPerCore; EFI_PHYSICAL_ADDRESS ThreadCountPerCore;
} CPU_STATUS_INFORMATION; } CPU_STATUS_INFORMATION;
// //
// Element of register table entry // Element of register table entry
// //
typedef struct { typedef struct {
REGISTER_TYPE RegisterType; // offset 0 - 3 REGISTER_TYPE RegisterType; // offset 0 - 3
UINT32 Index; // offset 4 - 7 UINT32 Index; // offset 4 - 7
UINT8 ValidBitStart; // offset 8 UINT8 ValidBitStart; // offset 8
UINT8 ValidBitLength; // offset 9 UINT8 ValidBitLength; // offset 9
BOOLEAN TestThenWrite; // offset 10 BOOLEAN TestThenWrite; // offset 10
UINT8 Reserved1; // offset 11 UINT8 Reserved1; // offset 11
UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped
UINT64 Value; // offset 16-23 UINT64 Value; // offset 16-23
} CPU_REGISTER_TABLE_ENTRY; } CPU_REGISTER_TABLE_ENTRY;
// //
@@ -109,20 +109,20 @@ typedef struct {
// //
// The number of valid entries in the RegisterTableEntry buffer // The number of valid entries in the RegisterTableEntry buffer
// //
UINT32 TableLength; UINT32 TableLength;
UINT32 NumberBeforeReset; UINT32 NumberBeforeReset;
// //
// The size, in bytes, of the RegisterTableEntry buffer // The size, in bytes, of the RegisterTableEntry buffer
// //
UINT32 AllocatedSize; UINT32 AllocatedSize;
// //
// The initial APIC ID of the CPU this register table applies to // The initial APIC ID of the CPU this register table applies to
// //
UINT32 InitialApicId; UINT32 InitialApicId;
// //
// Physical address of CPU_REGISTER_TABLE_ENTRY structures. // Physical address of CPU_REGISTER_TABLE_ENTRY structures.
// //
EFI_PHYSICAL_ADDRESS RegisterTableEntry; EFI_PHYSICAL_ADDRESS RegisterTableEntry;
} CPU_REGISTER_TABLE; } CPU_REGISTER_TABLE;
// //
@@ -151,11 +151,11 @@ typedef struct {
// If a register table is not required for any one of the CPUs, then // If a register table is not required for any one of the CPUs, then
// RegisterTable may be set to 0. // RegisterTable may be set to 0.
// //
EFI_PHYSICAL_ADDRESS RegisterTable; EFI_PHYSICAL_ADDRESS RegisterTable;
// //
// CPU information which is required when set the register table. // CPU information which is required when set the register table.
// //
CPU_STATUS_INFORMATION CpuStatus; CPU_STATUS_INFORMATION CpuStatus;
// //
// Location info for each AP. // Location info for each AP.
// It points to an array which saves all APs location info. // It points to an array which saves all APs location info.
@@ -180,7 +180,7 @@ typedef struct {
// it is recommended that the buffer be zero-filled. This buffer is used to // it is recommended that the buffer be zero-filled. This buffer is used to
// wake APs during an ACPI S3 resume. // wake APs during an ACPI S3 resume.
// //
EFI_PHYSICAL_ADDRESS StartupVector; EFI_PHYSICAL_ADDRESS StartupVector;
// //
// Physical address of structure of type IA32_DESCRIPTOR. The // Physical address of structure of type IA32_DESCRIPTOR. The
// IA32_DESCRIPTOR structure provides the base address and length of a GDT // IA32_DESCRIPTOR structure provides the base address and length of a GDT
@@ -188,7 +188,7 @@ typedef struct {
// used during an ACPI S3 resume. This is typically the contents of the GDT // used during an ACPI S3 resume. This is typically the contents of the GDT
// used by the boot processor when the platform is booted. // used by the boot processor when the platform is booted.
// //
EFI_PHYSICAL_ADDRESS GdtrProfile; EFI_PHYSICAL_ADDRESS GdtrProfile;
// //
// Physical address of structure of type IA32_DESCRIPTOR. The // Physical address of structure of type IA32_DESCRIPTOR. The
// IA32_DESCRIPTOR structure provides the base address and length of an IDT. // IA32_DESCRIPTOR structure provides the base address and length of an IDT.
@@ -196,31 +196,31 @@ typedef struct {
// used during an ACPI S3 resume. This is typically the contents of the IDT // used during an ACPI S3 resume. This is typically the contents of the IDT
// used by the boot processor when the platform is booted. // used by the boot processor when the platform is booted.
// //
EFI_PHYSICAL_ADDRESS IdtrProfile; EFI_PHYSICAL_ADDRESS IdtrProfile;
// //
// Physical address of a buffer that is used as stacks during ACPI S3 resume. // Physical address of a buffer that is used as stacks during ACPI S3 resume.
// The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This // The total size of this buffer, in bytes, is NumberOfCpus * StackSize. This
// structure must be allocated from memory of type EfiACPIMemoryNVS. // structure must be allocated from memory of type EfiACPIMemoryNVS.
// //
EFI_PHYSICAL_ADDRESS StackAddress; EFI_PHYSICAL_ADDRESS StackAddress;
// //
// The size, in bytes, of the stack provided to each CPU during ACPI S3 resume. // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume.
// //
UINT32 StackSize; UINT32 StackSize;
// //
// The number of CPUs. If a platform does not support hot plug CPUs, then // The number of CPUs. If a platform does not support hot plug CPUs, then
// this is the number of CPUs detected when the platform is booted, regardless // this is the number of CPUs detected when the platform is booted, regardless
// of being enabled or disabled. If a platform does support hot plug CPUs, // of being enabled or disabled. If a platform does support hot plug CPUs,
// then this is the maximum number of CPUs that the platform supports. // then this is the maximum number of CPUs that the platform supports.
// //
UINT32 NumberOfCpus; UINT32 NumberOfCpus;
// //
// Physical address of structure of type MTRR_SETTINGS that contains a copy // Physical address of structure of type MTRR_SETTINGS that contains a copy
// of the MTRR settings that are compatible with the MTRR settings used by // of the MTRR settings that are compatible with the MTRR settings used by
// the boot processor when the platform was booted. These MTRR settings are // the boot processor when the platform was booted. These MTRR settings are
// used during an ACPI S3 resume. // used during an ACPI S3 resume.
// //
EFI_PHYSICAL_ADDRESS MtrrTable; EFI_PHYSICAL_ADDRESS MtrrTable;
// //
// Physical address of a buffer that contains the machine check handler that // Physical address of a buffer that contains the machine check handler that
// is used during an ACPI S3 Resume. In order for this machine check // is used during an ACPI S3 Resume. In order for this machine check
@@ -228,18 +228,18 @@ typedef struct {
// vector in the IDT provided by IdtrProfile must be initialized to transfer // vector in the IDT provided by IdtrProfile must be initialized to transfer
// control to this physical address. // control to this physical address.
// //
EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase; EFI_PHYSICAL_ADDRESS ApMachineCheckHandlerBase;
// //
// The size, in bytes, of the machine check handler that is used during an // The size, in bytes, of the machine check handler that is used during an
// ACPI S3 Resume. If this field is 0, then a machine check handler is not // ACPI S3 Resume. If this field is 0, then a machine check handler is not
// provided. // provided.
// //
UINT32 ApMachineCheckHandlerSize; UINT32 ApMachineCheckHandlerSize;
// //
// Data structure that is used for CPU feature initialization during ACPI S3 // Data structure that is used for CPU feature initialization during ACPI S3
// resume. // resume.
// //
CPU_FEATURE_INIT_DATA CpuFeatureInitData; CPU_FEATURE_INIT_DATA CpuFeatureInitData;
} ACPI_CPU_DATA; } ACPI_CPU_DATA;
#endif #endif

2
UefiCpuPkg/Include/CpuHotPlugData.h
View File

@@ -9,7 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _CPU_HOT_PLUG_DATA_H_ #ifndef _CPU_HOT_PLUG_DATA_H_
#define _CPU_HOT_PLUG_DATA_H_ #define _CPU_HOT_PLUG_DATA_H_
#define CPU_HOT_PLUG_DATA_REVISION_1 0x00000001 #define CPU_HOT_PLUG_DATA_REVISION_1 0x00000001
typedef struct { typedef struct {
UINT32 Revision; // Used for version identification for this structure UINT32 Revision; // Used for version identification for this structure

2
UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h
View File

@@ -15,6 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
{ 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 } \ { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 } \
} }
extern EFI_GUID gEdkiiCpuFeaturesInitDoneGuid; extern EFI_GUID gEdkiiCpuFeaturesInitDoneGuid;
#endif #endif

2
UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h
View File

@@ -15,6 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
{ 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 } \ { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 } \
} }
extern EFI_GUID gEdkiiCpuFeaturesSetDoneGuid; extern EFI_GUID gEdkiiCpuFeaturesSetDoneGuid;
#endif #endif

2
UefiCpuPkg/Include/Guid/MicrocodePatchHob.h
View File

@@ -11,7 +11,7 @@
#ifndef _MICROCODE_PATCH_HOB_H_ #ifndef _MICROCODE_PATCH_HOB_H_
#define _MICROCODE_PATCH_HOB_H_ #define _MICROCODE_PATCH_HOB_H_
extern EFI_GUID gEdkiiMicrocodePatchHobGuid; extern EFI_GUID gEdkiiMicrocodePatchHobGuid;
// //
// The EDKII microcode patch HOB will be produced by MpInitLib and it can be // The EDKII microcode patch HOB will be produced by MpInitLib and it can be

2
UefiCpuPkg/Include/Guid/MsegSmram.h
View File

@@ -15,7 +15,7 @@
0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 } \ 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 } \
} }
extern EFI_GUID gMsegSmramGuid; extern EFI_GUID gMsegSmramGuid;
// //
// The data portion of this HOB is type EFI_SMRAM_DESCRIPTOR // The data portion of this HOB is type EFI_SMRAM_DESCRIPTOR

24
UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
View File

@@ -13,49 +13,49 @@ typedef struct {
// //
// Package number. // Package number.
// //
UINT32 Package; UINT32 Package;
// //
// Core type of logical processor. // Core type of logical processor.
// Value = CPUID.1Ah:EAX[31:24] // Value = CPUID.1Ah:EAX[31:24]
// //
UINT8 CoreType; UINT8 CoreType;
// //
// Level of the cache that this package's this type of logical processor corresponds to. // Level of the cache that this package's this type of logical processor corresponds to.
// Value = CPUID.04h:EAX[07:05] // Value = CPUID.04h:EAX[07:05]
// //
UINT8 CacheLevel : 3; UINT8 CacheLevel : 3;
// //
// Type of the cache that this package's this type of logical processor corresponds to. // Type of the cache that this package's this type of logical processor corresponds to.
// Value = CPUID.04h:EAX[04:00] // Value = CPUID.04h:EAX[04:00]
// //
UINT8 CacheType : 5; UINT8 CacheType : 5;
// //
// Ways of associativity. // Ways of associativity.
// Value = CPUID.04h:EBX[31:22] // Value = CPUID.04h:EBX[31:22]
// //
UINT16 CacheWays : 10; UINT16 CacheWays : 10;
// //
// Fully associative cache. // Fully associative cache.
// Value = CPUID.04h:EAX[09] // Value = CPUID.04h:EAX[09]
// //
UINT16 FullyAssociativeCache : 1; UINT16 FullyAssociativeCache : 1;
// //
// Direct mapped cache. // Direct mapped cache.
// Value = CPUID.04h:EDX[02] // Value = CPUID.04h:EDX[02]
// //
UINT16 DirectMappedCache : 1; UINT16 DirectMappedCache : 1;
UINT16 Reserved : 4; UINT16 Reserved : 4;
// //
// Size of single cache that this package's this type of logical processor corresponds to. // Size of single cache that this package's this type of logical processor corresponds to.
// Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) * // Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *
// (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1) // (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1)
// //
UINT32 CacheSizeinKB; UINT32 CacheSizeinKB;
// //
// Number of the cache that this package's this type of logical processor corresponds to. // Number of the cache that this package's this type of logical processor corresponds to.
// Have subtracted the number of caches that are shared. // Have subtracted the number of caches that are shared.
// //
UINT16 CacheCount; UINT16 CacheCount;
} CPU_CACHE_INFO; } CPU_CACHE_INFO;
/** /**
@@ -78,8 +78,8 @@ typedef struct {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GetCpuCacheInfo ( GetCpuCacheInfo (
IN OUT CPU_CACHE_INFO *CpuCacheInfo, IN OUT CPU_CACHE_INFO *CpuCacheInfo,
IN OUT UINTN *CpuCacheInfoCount IN OUT UINTN *CpuCacheInfoCount
); );
#endif #endif

28
UefiCpuPkg/Include/Library/LocalApicLib.h
View File

@@ -38,7 +38,7 @@ GetLocalApicBaseAddress (
VOID VOID
EFIAPI EFIAPI
SetLocalApicBaseAddress ( SetLocalApicBaseAddress (
IN UINTN BaseAddress IN UINTN BaseAddress
); );
/** /**
@@ -120,8 +120,8 @@ GetApicVersion (
VOID VOID
EFIAPI EFIAPI
SendFixedIpi ( SendFixedIpi (
IN UINT32 ApicId, IN UINT32 ApicId,
IN UINT8 Vector IN UINT8 Vector
); );
/** /**
@@ -134,7 +134,7 @@ SendFixedIpi (
VOID VOID
EFIAPI EFIAPI
SendFixedIpiAllExcludingSelf ( SendFixedIpiAllExcludingSelf (
IN UINT8 Vector IN UINT8 Vector
); );
/** /**
@@ -147,7 +147,7 @@ SendFixedIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendSmiIpi ( SendSmiIpi (
IN UINT32 ApicId IN UINT32 ApicId
); );
/** /**
@@ -171,7 +171,7 @@ SendSmiIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendInitIpi ( SendInitIpi (
IN UINT32 ApicId IN UINT32 ApicId
); );
/** /**
@@ -200,8 +200,8 @@ SendInitIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendInitSipiSipi ( SendInitSipiSipi (
IN UINT32 ApicId, IN UINT32 ApicId,
IN UINT32 StartupRoutine IN UINT32 StartupRoutine
); );
/** /**
@@ -218,7 +218,7 @@ SendInitSipiSipi (
VOID VOID
EFIAPI EFIAPI
SendInitSipiSipiAllExcludingSelf ( SendInitSipiSipiAllExcludingSelf (
IN UINT32 StartupRoutine IN UINT32 StartupRoutine
); );
/** /**
@@ -296,10 +296,10 @@ GetApicTimerCurrentCount (
VOID VOID
EFIAPI EFIAPI
InitializeApicTimer ( InitializeApicTimer (
IN UINTN DivideValue, IN UINTN DivideValue,
IN UINT32 InitCount, IN UINT32 InitCount,
IN BOOLEAN PeriodicMode, IN BOOLEAN PeriodicMode,
IN UINT8 Vector IN UINT8 Vector
); );
/** /**
@@ -453,5 +453,5 @@ GetProcessorLocation2ByApicId (
OUT UINT32 *Core OPTIONAL, OUT UINT32 *Core OPTIONAL,
OUT UINT32 *Thread OPTIONAL OUT UINT32 *Thread OPTIONAL
); );
#endif
#endif

16
UefiCpuPkg/Include/Library/MicrocodeLib.h
View File

@@ -52,7 +52,7 @@ GetProcessorMicrocodeCpuId (
UINT32 UINT32
EFIAPI EFIAPI
GetMicrocodeLength ( GetMicrocodeLength (
IN CPU_MICROCODE_HEADER *Microcode IN CPU_MICROCODE_HEADER *Microcode
); );
/** /**
@@ -65,7 +65,7 @@ GetMicrocodeLength (
VOID VOID
EFIAPI EFIAPI
LoadMicrocode ( LoadMicrocode (
IN CPU_MICROCODE_HEADER *Microcode IN CPU_MICROCODE_HEADER *Microcode
); );
/** /**
@@ -109,12 +109,12 @@ LoadMicrocode (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
IsValidMicrocode ( IsValidMicrocode (
IN CPU_MICROCODE_HEADER *Microcode, IN CPU_MICROCODE_HEADER *Microcode,
IN UINTN MicrocodeLength, IN UINTN MicrocodeLength,
IN UINT32 MinimumRevision, IN UINT32 MinimumRevision,
IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds, IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds,
IN UINTN MicrocodeCpuIdCount, IN UINTN MicrocodeCpuIdCount,
IN BOOLEAN VerifyChecksum IN BOOLEAN VerifyChecksum
); );
#endif #endif

46
UefiCpuPkg/Include/Library/MpInitLib.h
View File

@@ -54,8 +54,8 @@ MpInitLibInitialize (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibGetNumberOfProcessors ( MpInitLibGetNumberOfProcessors (
OUT UINTN *NumberOfProcessors OPTIONAL, OUT UINTN *NumberOfProcessors OPTIONAL,
OUT UINTN *NumberOfEnabledProcessors OPTIONAL OUT UINTN *NumberOfEnabledProcessors OPTIONAL
); );
/** /**
@@ -161,12 +161,12 @@ MpInitLibGetProcessorInfo (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupAllAPs ( MpInitLibStartupAllAPs (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT UINTN **FailedCpuList OPTIONAL OUT UINTN **FailedCpuList OPTIONAL
); );
/** /**
@@ -243,12 +243,12 @@ MpInitLibStartupAllAPs (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupThisAP ( MpInitLibStartupThisAP (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT BOOLEAN *Finished OPTIONAL OUT BOOLEAN *Finished OPTIONAL
); );
/** /**
@@ -280,8 +280,8 @@ MpInitLibStartupThisAP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibSwitchBSP ( MpInitLibSwitchBSP (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableOldBSP IN BOOLEAN EnableOldBSP
); );
/** /**
@@ -317,9 +317,9 @@ MpInitLibSwitchBSP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibEnableDisableAP ( MpInitLibEnableDisableAP (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL IN UINT32 *HealthFlag OPTIONAL
); );
/** /**
@@ -341,7 +341,7 @@ MpInitLibEnableDisableAP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibWhoAmI ( MpInitLibWhoAmI (
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
); );
/** /**
@@ -373,9 +373,9 @@ MpInitLibWhoAmI (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupAllCPUs ( MpInitLibStartupAllCPUs (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
); );
#endif #endif

63
UefiCpuPkg/Include/Library/MtrrLib.h
View File

@@ -24,27 +24,27 @@
// //
#define RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER 2 #define RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER 2
#define MTRR_NUMBER_OF_FIXED_MTRR 11 #define MTRR_NUMBER_OF_FIXED_MTRR 11
// //
// Structure to describe a fixed MTRR // Structure to describe a fixed MTRR
// //
typedef struct { typedef struct {
UINT32 Msr; UINT32 Msr;
UINT32 BaseAddress; UINT32 BaseAddress;
UINT32 Length; UINT32 Length;
} FIXED_MTRR; } FIXED_MTRR;
// //
// Structure to describe a variable MTRR // Structure to describe a variable MTRR
// //
typedef struct { typedef struct {
UINT64 BaseAddress; UINT64 BaseAddress;
UINT64 Length; UINT64 Length;
UINT64 Type; UINT64 Type;
UINT32 Msr; UINT32 Msr;
BOOLEAN Valid; BOOLEAN Valid;
BOOLEAN Used; BOOLEAN Used;
} VARIABLE_MTRR; } VARIABLE_MTRR;
// //
@@ -59,14 +59,14 @@ typedef struct _MTRR_VARIABLE_SETTING_ {
// Array for variable MTRRs // Array for variable MTRRs
// //
typedef struct _MTRR_VARIABLE_SETTINGS_ { typedef struct _MTRR_VARIABLE_SETTINGS_ {
MTRR_VARIABLE_SETTING Mtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; MTRR_VARIABLE_SETTING Mtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
} MTRR_VARIABLE_SETTINGS; } MTRR_VARIABLE_SETTINGS;
// //
// Array for fixed MTRRs // Array for fixed MTRRs
// //
typedef struct _MTRR_FIXED_SETTINGS_ { typedef struct _MTRR_FIXED_SETTINGS_ {
UINT64 Mtrr[MTRR_NUMBER_OF_FIXED_MTRR]; UINT64 Mtrr[MTRR_NUMBER_OF_FIXED_MTRR];
} MTRR_FIXED_SETTINGS; } MTRR_FIXED_SETTINGS;
// //
@@ -98,9 +98,9 @@ typedef enum {
#define MTRR_CACHE_INVALID_TYPE 7 #define MTRR_CACHE_INVALID_TYPE 7
typedef struct { typedef struct {
UINT64 BaseAddress; UINT64 BaseAddress;
UINT64 Length; UINT64 Length;
MTRR_MEMORY_CACHE_TYPE Type; MTRR_MEMORY_CACHE_TYPE Type;
} MTRR_MEMORY_RANGE; } MTRR_MEMORY_RANGE;
/** /**
@@ -168,7 +168,6 @@ MtrrSetMemoryAttribute (
IN MTRR_MEMORY_CACHE_TYPE Attribute IN MTRR_MEMORY_CACHE_TYPE Attribute
); );
/** /**
This function will get the memory cache type of the specific address. This function will get the memory cache type of the specific address.
This function is mainly for debugging purposes. This function is mainly for debugging purposes.
@@ -181,10 +180,9 @@ MtrrSetMemoryAttribute (
MTRR_MEMORY_CACHE_TYPE MTRR_MEMORY_CACHE_TYPE
EFIAPI EFIAPI
MtrrGetMemoryAttribute ( MtrrGetMemoryAttribute (
IN PHYSICAL_ADDRESS Address IN PHYSICAL_ADDRESS Address
); );
/** /**
This function gets the content in fixed MTRRs This function gets the content in fixed MTRRs
@@ -193,13 +191,12 @@ MtrrGetMemoryAttribute (
@return The pointer of FixedSettings @return The pointer of FixedSettings
**/ **/
MTRR_FIXED_SETTINGS* MTRR_FIXED_SETTINGS *
EFIAPI EFIAPI
MtrrGetFixedMtrr ( MtrrGetFixedMtrr (
OUT MTRR_FIXED_SETTINGS *FixedSettings OUT MTRR_FIXED_SETTINGS *FixedSettings
); );
/** /**
This function gets the content in all MTRRs (variable and fixed) This function gets the content in all MTRRs (variable and fixed)
@@ -211,10 +208,9 @@ MtrrGetFixedMtrr (
MTRR_SETTINGS * MTRR_SETTINGS *
EFIAPI EFIAPI
MtrrGetAllMtrrs ( MtrrGetAllMtrrs (
OUT MTRR_SETTINGS *MtrrSetting OUT MTRR_SETTINGS *MtrrSetting
); );
/** /**
This function sets all MTRRs (variable and fixed) This function sets all MTRRs (variable and fixed)
@@ -226,10 +222,9 @@ MtrrGetAllMtrrs (
MTRR_SETTINGS * MTRR_SETTINGS *
EFIAPI EFIAPI
MtrrSetAllMtrrs ( MtrrSetAllMtrrs (
IN MTRR_SETTINGS *MtrrSetting IN MTRR_SETTINGS *MtrrSetting
); );
/** /**
Get the attribute of variable MTRRs. Get the attribute of variable MTRRs.
@@ -248,12 +243,11 @@ MtrrSetAllMtrrs (
UINT32 UINT32
EFIAPI EFIAPI
MtrrGetMemoryAttributeInVariableMtrr ( MtrrGetMemoryAttributeInVariableMtrr (
IN UINT64 MtrrValidBitsMask, IN UINT64 MtrrValidBitsMask,
IN UINT64 MtrrValidAddressMask, IN UINT64 MtrrValidAddressMask,
OUT VARIABLE_MTRR *VariableMtrr OUT VARIABLE_MTRR *VariableMtrr
); );
/** /**
This function prints all MTRRs for debugging. This function prints all MTRRs for debugging.
**/ **/
@@ -355,10 +349,11 @@ MtrrSetMemoryAttributeInMtrrSettings (
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
MtrrSetMemoryAttributesInMtrrSettings ( MtrrSetMemoryAttributesInMtrrSettings (
IN OUT MTRR_SETTINGS *MtrrSetting, IN OUT MTRR_SETTINGS *MtrrSetting,
IN VOID *Scratch, IN VOID *Scratch,
IN OUT UINTN *ScratchSize, IN OUT UINTN *ScratchSize,
IN CONST MTRR_MEMORY_RANGE *Ranges, IN CONST MTRR_MEMORY_RANGE *Ranges,
IN UINTN RangeCount IN UINTN RangeCount
); );
#endif // _MTRR_LIB_H_ #endif // _MTRR_LIB_H_

8
UefiCpuPkg/Include/Library/PlatformSecLib.h
View File

@@ -30,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
EFI_PEI_PPI_DESCRIPTOR * EFI_PEI_PPI_DESCRIPTOR *
EFIAPI EFIAPI
SecPlatformMain ( SecPlatformMain (
IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
); );
/** /**
@@ -47,9 +47,9 @@ SecPlatformMain (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SecPlatformInformation ( SecPlatformInformation (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN OUT UINT64 *StructureSize, IN OUT UINT64 *StructureSize,
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
); );
/** /**

182
UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
View File

@@ -20,62 +20,62 @@
/// modifiers of a CPU feature. When used in a list, the define value /// modifiers of a CPU feature. When used in a list, the define value
/// CPU_FEATURE_END is used to terminate a list of CPU feature values. /// CPU_FEATURE_END is used to terminate a list of CPU feature values.
/// @{ /// @{
#define CPU_FEATURE_AESNI 0 #define CPU_FEATURE_AESNI 0
#define CPU_FEATURE_TURBO_MODE 1 #define CPU_FEATURE_TURBO_MODE 1
#define CPU_FEATURE_MWAIT 2 #define CPU_FEATURE_MWAIT 2
#define CPU_FEATURE_ACPI 3 #define CPU_FEATURE_ACPI 3
#define CPU_FEATURE_EIST 4 #define CPU_FEATURE_EIST 4
#define CPU_FEATURE_RESERVED_5 5 #define CPU_FEATURE_RESERVED_5 5
#define CPU_FEATURE_FASTSTRINGS 6 #define CPU_FEATURE_FASTSTRINGS 6
#define CPU_FEATURE_VMX 7 #define CPU_FEATURE_VMX 7
#define CPU_FEATURE_SMX 8 #define CPU_FEATURE_SMX 8
#define CPU_FEATURE_LMCE 9 #define CPU_FEATURE_LMCE 9
#define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER 10 #define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER 10
#define CPU_FEATURE_LIMIT_CPUID_MAX_VAL 11 #define CPU_FEATURE_LIMIT_CPUID_MAX_VAL 11
#define CPU_FEATURE_MCE 12 #define CPU_FEATURE_MCE 12
#define CPU_FEATURE_MCA 13 #define CPU_FEATURE_MCA 13
#define CPU_FEATURE_MCG_CTL 14 #define CPU_FEATURE_MCG_CTL 14
#define CPU_FEATURE_PENDING_BREAK 15 #define CPU_FEATURE_PENDING_BREAK 15
#define CPU_FEATURE_C1E 16 #define CPU_FEATURE_C1E 16
#define CPU_FEATURE_C1_AUTO_DEMOTION 17 #define CPU_FEATURE_C1_AUTO_DEMOTION 17
#define CPU_FEATURE_C3_AUTO_DEMOTION 18 #define CPU_FEATURE_C3_AUTO_DEMOTION 18
#define CPU_FEATURE_C1_UNDEMOTION 19 #define CPU_FEATURE_C1_UNDEMOTION 19
#define CPU_FEATURE_C3_UNDEMOTION 20 #define CPU_FEATURE_C3_UNDEMOTION 20
#define CPU_FEATURE_C_STATE 21 #define CPU_FEATURE_C_STATE 21
#define CPU_FEATURE_TM 22 #define CPU_FEATURE_TM 22
#define CPU_FEATURE_TM2 23 #define CPU_FEATURE_TM2 23
#define CPU_FEATURE_X2APIC 24 #define CPU_FEATURE_X2APIC 24
#define CPU_FEATURE_RESERVED_25 25 #define CPU_FEATURE_RESERVED_25 25
#define CPU_FEATURE_RESERVED_26 26 #define CPU_FEATURE_RESERVED_26 26
#define CPU_FEATURE_RESERVED_27 27 #define CPU_FEATURE_RESERVED_27 27
#define CPU_FEATURE_RESERVED_28 28 #define CPU_FEATURE_RESERVED_28 28
#define CPU_FEATURE_RESERVED_29 29 #define CPU_FEATURE_RESERVED_29 29
#define CPU_FEATURE_RESERVED_30 30 #define CPU_FEATURE_RESERVED_30 30
#define CPU_FEATURE_RESERVED_31 31 #define CPU_FEATURE_RESERVED_31 31
#define CPU_FEATURE_L2_PREFETCHER (32+0) #define CPU_FEATURE_L2_PREFETCHER (32+0)
#define CPU_FEATURE_L1_DATA_PREFETCHER (32+1) #define CPU_FEATURE_L1_DATA_PREFETCHER (32+1)
#define CPU_FEATURE_HARDWARE_PREFETCHER (32+2) #define CPU_FEATURE_HARDWARE_PREFETCHER (32+2)
#define CPU_FEATURE_ADJACENT_CACHE_LINE_PREFETCH (32+3) #define CPU_FEATURE_ADJACENT_CACHE_LINE_PREFETCH (32+3)
#define CPU_FEATURE_DCU_PREFETCHER (32+4) #define CPU_FEATURE_DCU_PREFETCHER (32+4)
#define CPU_FEATURE_IP_PREFETCHER (32+5) #define CPU_FEATURE_IP_PREFETCHER (32+5)
#define CPU_FEATURE_MLC_STREAMER_PREFETCHER (32+6) #define CPU_FEATURE_MLC_STREAMER_PREFETCHER (32+6)
#define CPU_FEATURE_MLC_SPATIAL_PREFETCHER (32+7) #define CPU_FEATURE_MLC_SPATIAL_PREFETCHER (32+7)
#define CPU_FEATURE_THREE_STRIKE_COUNTER (32+8) #define CPU_FEATURE_THREE_STRIKE_COUNTER (32+8)
#define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9) #define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9)
#define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10) #define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10)
#define CPU_FEATURE_PPIN (32+11) #define CPU_FEATURE_PPIN (32+11)
#define CPU_FEATURE_PROC_TRACE (32+12) #define CPU_FEATURE_PROC_TRACE (32+12)
#define CPU_FEATURE_BEFORE_ALL BIT23 #define CPU_FEATURE_BEFORE_ALL BIT23
#define CPU_FEATURE_AFTER_ALL BIT24 #define CPU_FEATURE_AFTER_ALL BIT24
#define CPU_FEATURE_THREAD_BEFORE BIT25 #define CPU_FEATURE_THREAD_BEFORE BIT25
#define CPU_FEATURE_THREAD_AFTER BIT26 #define CPU_FEATURE_THREAD_AFTER BIT26
#define CPU_FEATURE_CORE_BEFORE BIT27 #define CPU_FEATURE_CORE_BEFORE BIT27
#define CPU_FEATURE_CORE_AFTER BIT28 #define CPU_FEATURE_CORE_AFTER BIT28
#define CPU_FEATURE_PACKAGE_BEFORE BIT29 #define CPU_FEATURE_PACKAGE_BEFORE BIT29
#define CPU_FEATURE_PACKAGE_AFTER BIT30 #define CPU_FEATURE_PACKAGE_AFTER BIT30
#define CPU_FEATURE_END MAX_UINT32 #define CPU_FEATURE_END MAX_UINT32
/// @} /// @}
/// ///
@@ -85,28 +85,28 @@ typedef struct {
// //
// Set to 1 when current processor is the first thread in the core it resides in. // Set to 1 when current processor is the first thread in the core it resides in.
// //
UINT32 Thread : 1; UINT32 Thread : 1;
// //
// Set to 1 when current processor is a thread of the first core in the module it resides in. // Set to 1 when current processor is a thread of the first core in the module it resides in.
// //
UINT32 Core : 1; UINT32 Core : 1;
// //
// Set to 1 when current processor is a thread of the first module in the tile it resides in. // Set to 1 when current processor is a thread of the first module in the tile it resides in.
// //
UINT32 Module : 1; UINT32 Module : 1;
// //
// Set to 1 when current processor is a thread of the first tile in the die it resides in. // Set to 1 when current processor is a thread of the first tile in the die it resides in.
// //
UINT32 Tile : 1; UINT32 Tile : 1;
// //
// Set to 1 when current processor is a thread of the first die in the package it resides in. // Set to 1 when current processor is a thread of the first die in the package it resides in.
// //
UINT32 Die : 1; UINT32 Die : 1;
// //
// Set to 1 when current processor is a thread of the first package in the system. // Set to 1 when current processor is a thread of the first package in the system.
// //
UINT32 Package : 1; UINT32 Package : 1;
UINT32 Reserved : 26; UINT32 Reserved : 26;
} REGISTER_CPU_FEATURE_FIRST_PROCESSOR; } REGISTER_CPU_FEATURE_FIRST_PROCESSOR;
/// ///
@@ -118,36 +118,36 @@ typedef struct {
/// ///
/// The package that the CPU resides /// The package that the CPU resides
/// ///
EFI_PROCESSOR_INFORMATION ProcessorInfo; EFI_PROCESSOR_INFORMATION ProcessorInfo;
/// ///
/// The bit flag indicating whether the CPU is the first Thread/Core/Module/Tile/Die/Package in its parent scope. /// The bit flag indicating whether the CPU is the first Thread/Core/Module/Tile/Die/Package in its parent scope.
/// ///
REGISTER_CPU_FEATURE_FIRST_PROCESSOR First; REGISTER_CPU_FEATURE_FIRST_PROCESSOR First;
/// ///
/// The Display Family of the CPU computed from CPUID leaf CPUID_VERSION_INFO /// The Display Family of the CPU computed from CPUID leaf CPUID_VERSION_INFO
/// ///
UINT32 DisplayFamily; UINT32 DisplayFamily;
/// ///
/// The Display Model of the CPU computed from CPUID leaf CPUID_VERSION_INFO /// The Display Model of the CPU computed from CPUID leaf CPUID_VERSION_INFO
/// ///
UINT32 DisplayModel; UINT32 DisplayModel;
/// ///
/// The Stepping ID of the CPU computed from CPUID leaf CPUID_VERSION_INFO /// The Stepping ID of the CPU computed from CPUID leaf CPUID_VERSION_INFO
/// ///
UINT32 SteppingId; UINT32 SteppingId;
/// ///
/// The Processor Type of the CPU computed from CPUID leaf CPUID_VERSION_INFO /// The Processor Type of the CPU computed from CPUID leaf CPUID_VERSION_INFO
/// ///
UINT32 ProcessorType; UINT32 ProcessorType;
/// ///
/// Bit field structured returned in ECX from CPUID leaf CPUID_VERSION_INFO /// Bit field structured returned in ECX from CPUID leaf CPUID_VERSION_INFO
/// ///
CPUID_VERSION_INFO_ECX CpuIdVersionInfoEcx; CPUID_VERSION_INFO_ECX CpuIdVersionInfoEcx;
/// ///
/// Bit field structured returned in EDX from CPUID leaf CPUID_VERSION_INFO /// Bit field structured returned in EDX from CPUID leaf CPUID_VERSION_INFO
/// ///
CPUID_VERSION_INFO_EDX CpuIdVersionInfoEdx; CPUID_VERSION_INFO_EDX CpuIdVersionInfoEdx;
} REGISTER_CPU_FEATURE_INFORMATION; } REGISTER_CPU_FEATURE_INFORMATION;
/** /**
@@ -167,7 +167,7 @@ typedef struct {
BOOLEAN BOOLEAN
EFIAPI EFIAPI
IsCpuFeatureSupported ( IsCpuFeatureSupported (
IN UINT32 Feature IN UINT32 Feature
); );
/** /**
@@ -184,7 +184,7 @@ IsCpuFeatureSupported (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
IsCpuFeatureInSetting ( IsCpuFeatureInSetting (
IN UINT32 Feature IN UINT32 Feature
); );
/** /**
@@ -303,10 +303,10 @@ RETURN_STATUS
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
RegisterCpuFeature ( RegisterCpuFeature (
IN CHAR8 *FeatureName OPTIONAL, IN CHAR8 *FeatureName OPTIONAL,
IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc OPTIONAL, IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc OPTIONAL,
IN CPU_FEATURE_SUPPORT SupportFunc OPTIONAL, IN CPU_FEATURE_SUPPORT SupportFunc OPTIONAL,
IN CPU_FEATURE_INITIALIZE InitializeFunc OPTIONAL, IN CPU_FEATURE_INITIALIZE InitializeFunc OPTIONAL,
... ...
); );
@@ -348,7 +348,7 @@ CpuFeaturesInitialize (
VOID VOID
EFIAPI EFIAPI
SwitchBspAfterFeaturesInitialize ( SwitchBspAfterFeaturesInitialize (
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
); );
/** /**
@@ -368,11 +368,11 @@ SwitchBspAfterFeaturesInitialize (
VOID VOID
EFIAPI EFIAPI
CpuRegisterTableWrite ( CpuRegisterTableWrite (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN REGISTER_TYPE RegisterType, IN REGISTER_TYPE RegisterType,
IN UINT64 Index, IN UINT64 Index,
IN UINT64 ValueMask, IN UINT64 ValueMask,
IN UINT64 Value IN UINT64 Value
); );
/** /**
@@ -394,11 +394,11 @@ CpuRegisterTableWrite (
VOID VOID
EFIAPI EFIAPI
CpuRegisterTableTestThenWrite ( CpuRegisterTableTestThenWrite (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN REGISTER_TYPE RegisterType, IN REGISTER_TYPE RegisterType,
IN UINT64 Index, IN UINT64 Index,
IN UINT64 ValueMask, IN UINT64 ValueMask,
IN UINT64 Value IN UINT64 Value
); );
/** /**
@@ -418,11 +418,11 @@ CpuRegisterTableTestThenWrite (
VOID VOID
EFIAPI EFIAPI
PreSmmCpuRegisterTableWrite ( PreSmmCpuRegisterTableWrite (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN REGISTER_TYPE RegisterType, IN REGISTER_TYPE RegisterType,
IN UINT64 Index, IN UINT64 Index,
IN UINT64 ValueMask, IN UINT64 ValueMask,
IN UINT64 Value IN UINT64 Value
); );
/** /**

2
UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
View File

@@ -408,7 +408,7 @@ SmmCpuFeaturesCompleteSmmReadyToLock (
VOID * VOID *
EFIAPI EFIAPI
SmmCpuFeaturesAllocatePageTableMemory ( SmmCpuFeaturesAllocatePageTableMemory (
IN UINTN Pages IN UINTN Pages
); );
#endif #endif

18
UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h
View File

@@ -13,10 +13,10 @@
/// SMM Page Size Type /// SMM Page Size Type
/// ///
typedef enum { typedef enum {
SmmPageSize4K, SmmPageSize4K,
SmmPageSize2M, SmmPageSize2M,
SmmPageSize1G, SmmPageSize1G,
MaxSmmPageSizeType MaxSmmPageSizeType
} SMM_PAGE_SIZE_TYPE; } SMM_PAGE_SIZE_TYPE;
/** /**
@@ -74,7 +74,7 @@ ClearTopLevelSmiStatus (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
PlatformSmmBspElection ( PlatformSmmBspElection (
OUT BOOLEAN *IsBsp OUT BOOLEAN *IsBsp
); );
/** /**
@@ -94,10 +94,10 @@ PlatformSmmBspElection (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GetPlatformPageTableAttribute ( GetPlatformPageTableAttribute (
IN UINT64 Address, IN UINT64 Address,
OUT SMM_PAGE_SIZE_TYPE *PageSize, OUT SMM_PAGE_SIZE_TYPE *PageSize,
OUT UINTN *NumOfPages, OUT UINTN *NumOfPages,
OUT UINTN *PageAttribute OUT UINTN *PageAttribute
); );
#endif #endif

2
UefiCpuPkg/Include/Library/UefiCpuLib.h
View File

@@ -13,8 +13,6 @@
#ifndef __UEFI_CPU_LIB_H__ #ifndef __UEFI_CPU_LIB_H__
#define __UEFI_CPU_LIB_H__ #define __UEFI_CPU_LIB_H__
/** /**
Initializes floating point units for requirement of UEFI specification. Initializes floating point units for requirement of UEFI specification.

25
UefiCpuPkg/Include/Library/VmgExitLib.h
View File

@@ -15,7 +15,6 @@
#include <Protocol/DebugSupport.h> #include <Protocol/DebugSupport.h>
#include <Register/Amd/Ghcb.h> #include <Register/Amd/Ghcb.h>
/** /**
Perform VMGEXIT. Perform VMGEXIT.
@@ -38,10 +37,10 @@
UINT64 UINT64
EFIAPI EFIAPI
VmgExit ( VmgExit (
IN OUT GHCB *Ghcb, IN OUT GHCB *Ghcb,
IN UINT64 ExitCode, IN UINT64 ExitCode,
IN UINT64 ExitInfo1, IN UINT64 ExitInfo1,
IN UINT64 ExitInfo2 IN UINT64 ExitInfo2
); );
/** /**
@@ -58,8 +57,8 @@ VmgExit (
VOID VOID
EFIAPI EFIAPI
VmgInit ( VmgInit (
IN OUT GHCB *Ghcb, IN OUT GHCB *Ghcb,
IN OUT BOOLEAN *InterruptState IN OUT BOOLEAN *InterruptState
); );
/** /**
@@ -76,8 +75,8 @@ VmgInit (
VOID VOID
EFIAPI EFIAPI
VmgDone ( VmgDone (
IN OUT GHCB *Ghcb, IN OUT GHCB *Ghcb,
IN BOOLEAN InterruptState IN BOOLEAN InterruptState
); );
/** /**
@@ -93,8 +92,8 @@ VmgDone (
VOID VOID
EFIAPI EFIAPI
VmgSetOffsetValid ( VmgSetOffsetValid (
IN OUT GHCB *Ghcb, IN OUT GHCB *Ghcb,
IN GHCB_REGISTER Offset IN GHCB_REGISTER Offset
); );
/** /**
@@ -113,8 +112,8 @@ VmgSetOffsetValid (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
VmgIsOffsetValid ( VmgIsOffsetValid (
IN GHCB *Ghcb, IN GHCB *Ghcb,
IN GHCB_REGISTER Offset IN GHCB_REGISTER Offset
); );
/** /**

37
UefiCpuPkg/Include/Ppi/MpServices2.h
View File

@@ -16,7 +16,7 @@
0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba} \ 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba} \
} }
typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI; typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI;
/** /**
Get the number of CPU's. Get the number of CPU's.
@@ -35,7 +35,7 @@ typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI;
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) ( (EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfProcessors,
OUT UINTN *NumberOfEnabledProcessors OUT UINTN *NumberOfEnabledProcessors
@@ -57,7 +57,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO) ( (EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
@@ -97,7 +97,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS) ( (EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
@@ -139,7 +139,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP) ( (EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
@@ -171,7 +171,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP) ( (EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableOldBSP IN BOOLEAN EnableOldBSP
@@ -205,7 +205,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP) ( (EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
@@ -227,12 +227,11 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI) ( (EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
); );
/** /**
Activate all of the application proessors. Activate all of the application proessors.
@@ -256,7 +255,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS) ( (EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS)(
IN EDKII_PEI_MP_SERVICES2_PPI *This, IN EDKII_PEI_MP_SERVICES2_PPI *This,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN TimeoutInMicroSeconds, IN UINTN TimeoutInMicroSeconds,
@@ -264,16 +263,16 @@ EFI_STATUS
); );
struct _EDKII_PEI_MP_SERVICES2_PPI { struct _EDKII_PEI_MP_SERVICES2_PPI {
EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors; EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS GetNumberOfProcessors;
EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo; EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO GetProcessorInfo;
EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs; EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS StartupAllAPs;
EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP; EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP StartupThisAP;
EDKII_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP; EDKII_PEI_MP_SERVICES_SWITCH_BSP SwitchBSP;
EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP; EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP EnableDisableAP;
EDKII_PEI_MP_SERVICES_WHOAMI WhoAmI; EDKII_PEI_MP_SERVICES_WHOAMI WhoAmI;
EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS StartupAllCPUs; EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS StartupAllCPUs;
}; };
extern EFI_GUID gEdkiiPeiMpServices2PpiGuid; extern EFI_GUID gEdkiiPeiMpServices2PpiGuid;
#endif #endif

4
UefiCpuPkg/Include/Ppi/RepublishSecPpi.h
View File

@@ -46,9 +46,9 @@ EFI_STATUS
/// Republish SEC PPIs /// Republish SEC PPIs
/// ///
struct _REPUBLISH_SEC_PPI_PPI { struct _REPUBLISH_SEC_PPI_PPI {
REPUBLISH_SEC_PPI_REPUBLISH_SEC_PPIS RepublishSecPpis; REPUBLISH_SEC_PPI_REPUBLISH_SEC_PPIS RepublishSecPpis;
}; };
extern EFI_GUID gRepublishSecPpiPpiGuid; extern EFI_GUID gRepublishSecPpiPpiGuid;
#endif #endif

13
UefiCpuPkg/Include/Ppi/ShadowMicrocode.h
View File

@@ -14,11 +14,11 @@
0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 } \ 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 } \
} }
typedef struct _EDKII_PEI_SHADOW_MICROCODE_PPI EDKII_PEI_SHADOW_MICROCODE_PPI; typedef struct _EDKII_PEI_SHADOW_MICROCODE_PPI EDKII_PEI_SHADOW_MICROCODE_PPI;
typedef struct { typedef struct {
UINT32 ProcessorSignature; UINT32 ProcessorSignature;
UINT8 PlatformId; UINT8 PlatformId;
} EDKII_PEI_MICROCODE_CPU_ID; } EDKII_PEI_MICROCODE_CPU_ID;
/** /**
@@ -44,7 +44,7 @@ typedef struct {
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EDKII_PEI_SHADOW_MICROCODE) ( (EFIAPI *EDKII_PEI_SHADOW_MICROCODE)(
IN EDKII_PEI_SHADOW_MICROCODE_PPI *This, IN EDKII_PEI_SHADOW_MICROCODE_PPI *This,
IN UINTN CpuIdCount, IN UINTN CpuIdCount,
IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
@@ -57,10 +57,9 @@ EFI_STATUS
/// abstracts handling microcode shadow support. /// abstracts handling microcode shadow support.
/// ///
struct _EDKII_PEI_SHADOW_MICROCODE_PPI { struct _EDKII_PEI_SHADOW_MICROCODE_PPI {
EDKII_PEI_SHADOW_MICROCODE ShadowMicrocode; EDKII_PEI_SHADOW_MICROCODE ShadowMicrocode;
}; };
extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid; extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid;
#endif #endif

26
UefiCpuPkg/Include/Protocol/SmMonitorInit.h
View File

@@ -34,7 +34,7 @@
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR) ( (EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR)(
IN EFI_PHYSICAL_ADDRESS StmImage, IN EFI_PHYSICAL_ADDRESS StmImage,
IN UINTN StmImageSize IN UINTN StmImageSize
); );
@@ -54,7 +54,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE) ( (EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE)(
IN STM_RSC *ResourceList, IN STM_RSC *ResourceList,
IN UINT32 NumEntries OPTIONAL IN UINT32 NumEntries OPTIONAL
); );
@@ -74,7 +74,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE) ( (EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE)(
IN STM_RSC *ResourceList OPTIONAL, IN STM_RSC *ResourceList OPTIONAL,
IN UINT32 NumEntries OPTIONAL IN UINT32 NumEntries OPTIONAL
); );
@@ -94,14 +94,14 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE) ( (EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE)(
OUT STM_RSC *ResourceList, OUT STM_RSC *ResourceList,
IN OUT UINT32 *ResourceSize IN OUT UINT32 *ResourceSize
); );
typedef UINT32 EFI_SM_MONITOR_STATE; typedef UINT32 EFI_SM_MONITOR_STATE;
#define EFI_SM_MONITOR_STATE_ENABLED 0x1 #define EFI_SM_MONITOR_STATE_ENABLED 0x1
#define EFI_SM_MONITOR_STATE_ACTIVATED 0x2 #define EFI_SM_MONITOR_STATE_ACTIVATED 0x2
/** /**
@@ -112,7 +112,7 @@ typedef UINT32 EFI_SM_MONITOR_STATE;
**/ **/
typedef typedef
EFI_SM_MONITOR_STATE EFI_SM_MONITOR_STATE
(EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE) ( (EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE)(
VOID VOID
); );
@@ -120,16 +120,16 @@ typedef struct _EFI_SM_MONITOR_INIT_PROTOCOL {
// //
// Valid at boot-time only // Valid at boot-time only
// //
EFI_SM_MONITOR_LOAD_MONITOR LoadMonitor; EFI_SM_MONITOR_LOAD_MONITOR LoadMonitor;
EFI_SM_MONITOR_ADD_PI_RESOURCE AddPiResource; EFI_SM_MONITOR_ADD_PI_RESOURCE AddPiResource;
EFI_SM_MONITOR_DELETE_PI_RESOURCE DeletePiResource; EFI_SM_MONITOR_DELETE_PI_RESOURCE DeletePiResource;
EFI_SM_MONITOR_GET_PI_RESOURCE GetPiResource; EFI_SM_MONITOR_GET_PI_RESOURCE GetPiResource;
// //
// Valid at runtime // Valid at runtime
// //
EFI_SM_MONITOR_GET_MONITOR_STATE GetMonitorState; EFI_SM_MONITOR_GET_MONITOR_STATE GetMonitorState;
} EFI_SM_MONITOR_INIT_PROTOCOL; } EFI_SM_MONITOR_INIT_PROTOCOL;
extern EFI_GUID gEfiSmMonitorInitProtocolGuid; extern EFI_GUID gEfiSmMonitorInitProtocolGuid;
#endif #endif

26
UefiCpuPkg/Include/Protocol/SmmCpuService.h
View File

@@ -44,7 +44,7 @@ typedef struct _EFI_SMM_CPU_SERVICE_PROTOCOL EFI_SMM_CPU_SERVICE_PROTOCOL;
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI * EFI_SMM_GET_PROCESSOR_INFO) ( (EFIAPI *EFI_SMM_GET_PROCESSOR_INFO)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
@@ -82,7 +82,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI * EFI_SMM_SWITCH_BSP) ( (EFIAPI *EFI_SMM_SWITCH_BSP)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
); );
@@ -106,7 +106,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SMM_ADD_PROCESSOR) ( (EFIAPI *EFI_SMM_ADD_PROCESSOR)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINT64 ProcessorId, IN UINT64 ProcessorId,
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
@@ -128,7 +128,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SMM_REMOVE_PROCESSOR) ( (EFIAPI *EFI_SMM_REMOVE_PROCESSOR)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
); );
@@ -156,7 +156,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI * EFI_SMM_WHOAMI) ( (EFIAPI *EFI_SMM_WHOAMI)(
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
); );
@@ -180,7 +180,7 @@ EFI_STATUS
**/ **/
typedef typedef
EFI_STATUS EFI_STATUS
(EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER) ( (EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER)(
IN EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
@@ -190,14 +190,14 @@ EFI_STATUS
// This protocol provides CPU services from SMM. // This protocol provides CPU services from SMM.
// //
struct _EFI_SMM_CPU_SERVICE_PROTOCOL { struct _EFI_SMM_CPU_SERVICE_PROTOCOL {
EFI_SMM_GET_PROCESSOR_INFO GetProcessorInfo; EFI_SMM_GET_PROCESSOR_INFO GetProcessorInfo;
EFI_SMM_SWITCH_BSP SwitchBsp; EFI_SMM_SWITCH_BSP SwitchBsp;
EFI_SMM_ADD_PROCESSOR AddProcessor; EFI_SMM_ADD_PROCESSOR AddProcessor;
EFI_SMM_REMOVE_PROCESSOR RemoveProcessor; EFI_SMM_REMOVE_PROCESSOR RemoveProcessor;
EFI_SMM_WHOAMI WhoAmI; EFI_SMM_WHOAMI WhoAmI;
EFI_SMM_REGISTER_EXCEPTION_HANDLER RegisterExceptionHandler; EFI_SMM_REGISTER_EXCEPTION_HANDLER RegisterExceptionHandler;
}; };
extern EFI_GUID gEfiSmmCpuServiceProtocolGuid; extern EFI_GUID gEfiSmmCpuServiceProtocolGuid;
#endif #endif

1
UefiCpuPkg/Include/Register/LocalApic.h
View File

@@ -11,4 +11,3 @@
#include <Register/Intel/LocalApic.h> #include <Register/Intel/LocalApic.h>
#endif #endif

2
UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
View File

@@ -77,5 +77,5 @@ GetCpuSteppingId (
AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL); AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);
return (UINT8) Eax.Bits.SteppingId; return (UINT8)Eax.Bits.SteppingId;
} }

284
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
View File

@@ -44,13 +44,14 @@ LocalApicBaseAddressMsrSupported (
AsmCpuid (1, &RegEax, NULL, NULL, NULL); AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11); FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) { if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
// //
// CPUs with a FamilyId of 0x04 or 0x05 do not support the // CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR // Local APIC Base Address MSR
// //
return FALSE; return FALSE;
} }
return TRUE; return TRUE;
} }
@@ -78,8 +79,8 @@ GetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
} }
/** /**
@@ -93,7 +94,7 @@ GetLocalApicBaseAddress (
VOID VOID
EFIAPI EFIAPI
SetLocalApicBaseAddress ( SetLocalApicBaseAddress (
IN UINTN BaseAddress IN UINTN BaseAddress
) )
{ {
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
@@ -109,8 +110,8 @@ SetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12); ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32)); ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
} }
@@ -137,7 +138,7 @@ ReadLocalApicReg (
ASSERT ((MmioOffset & 0xf) == 0); ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset); return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
} }
/** /**
@@ -157,14 +158,14 @@ ReadLocalApicReg (
VOID VOID
EFIAPI EFIAPI
WriteLocalApicReg ( WriteLocalApicReg (
IN UINTN MmioOffset, IN UINTN MmioOffset,
IN UINT32 Value IN UINT32 Value
) )
{ {
ASSERT ((MmioOffset & 0xf) == 0); ASSERT ((MmioOffset & 0xf) == 0);
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value); MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
} }
/** /**
@@ -177,13 +178,13 @@ WriteLocalApicReg (
**/ **/
VOID VOID
SendIpi ( SendIpi (
IN UINT32 IcrLow, IN UINT32 IcrLow,
IN UINT32 ApicId IN UINT32 ApicId
) )
{ {
LOCAL_APIC_ICR_LOW IcrLowReg; LOCAL_APIC_ICR_LOW IcrLowReg;
UINT32 IcrHigh; UINT32 IcrHigh;
BOOLEAN InterruptState; BOOLEAN InterruptState;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
ASSERT (ApicId <= 0xff); ASSERT (ApicId <= 0xff);
@@ -222,7 +223,6 @@ SendIpi (
WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh); WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState); SetInterruptState (InterruptState);
} }
// //
@@ -244,21 +244,21 @@ GetApicMode (
) )
{ {
DEBUG_CODE_BEGIN (); DEBUG_CODE_BEGIN ();
{ {
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
//
// Check to see if the CPU supports the APIC Base Address MSR
//
if (LocalApicBaseAddressMsrSupported ()) {
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
// //
// Check to see if the CPU supports the APIC Base Address MSR // Local APIC should have been enabled
// //
if (LocalApicBaseAddressMsrSupported ()) { ASSERT (ApicBaseMsr.Bits.EN != 0);
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ASSERT (ApicBaseMsr.Bits.EXTD == 0);
//
// Local APIC should have been enabled
//
ASSERT (ApicBaseMsr.Bits.EN != 0);
ASSERT (ApicBaseMsr.Bits.EXTD == 0);
}
} }
}
DEBUG_CODE_END (); DEBUG_CODE_END ();
return LOCAL_APIC_MODE_XAPIC; return LOCAL_APIC_MODE_XAPIC;
} }
@@ -299,9 +299,9 @@ GetInitialApicId (
VOID VOID
) )
{ {
UINT32 ApicId; UINT32 ApicId;
UINT32 MaxCpuIdIndex; UINT32 MaxCpuIdIndex;
UINT32 RegEbx; UINT32 RegEbx;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
@@ -338,7 +338,7 @@ GetApicId (
VOID VOID
) )
{ {
UINT32 ApicId; UINT32 ApicId;
ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC); ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);
@@ -347,9 +347,10 @@ GetApicId (
// If the initial local APIC ID is less 0x100, read APIC ID from // If the initial local APIC ID is less 0x100, read APIC ID from
// XAPIC_ID_OFFSET, otherwise return the initial local APIC ID. // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
// //
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET); ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
ApicId >>= 24; ApicId >>= 24;
} }
return ApicId; return ApicId;
} }
@@ -378,16 +379,16 @@ GetApicVersion (
VOID VOID
EFIAPI EFIAPI
SendFixedIpi ( SendFixedIpi (
IN UINT32 ApicId, IN UINT32 ApicId,
IN UINT8 Vector IN UINT8 Vector
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.Vector = Vector; IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, ApicId); SendIpi (IcrLow.Uint32, ApicId);
} }
@@ -401,16 +402,16 @@ SendFixedIpi (
VOID VOID
EFIAPI EFIAPI
SendFixedIpiAllExcludingSelf ( SendFixedIpiAllExcludingSelf (
IN UINT8 Vector IN UINT8 Vector
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
IcrLow.Bits.Vector = Vector; IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, 0); SendIpi (IcrLow.Uint32, 0);
} }
@@ -424,14 +425,14 @@ SendFixedIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendSmiIpi ( SendSmiIpi (
IN UINT32 ApicId IN UINT32 ApicId
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId); SendIpi (IcrLow.Uint32, ApicId);
} }
@@ -446,11 +447,11 @@ SendSmiIpiAllExcludingSelf (
VOID VOID
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0); SendIpi (IcrLow.Uint32, 0);
} }
@@ -465,14 +466,14 @@ SendSmiIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendInitIpi ( SendInitIpi (
IN UINT32 ApicId IN UINT32 ApicId
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId); SendIpi (IcrLow.Uint32, ApicId);
} }
@@ -487,11 +488,11 @@ SendInitIpiAllExcludingSelf (
VOID VOID
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0); SendIpi (IcrLow.Uint32, 0);
} }
@@ -511,21 +512,21 @@ SendInitIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendInitSipiSipi ( SendInitSipiSipi (
IN UINT32 ApicId, IN UINT32 ApicId,
IN UINT32 StartupRoutine IN UINT32 StartupRoutine
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000); ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0); ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId); SendInitIpi (ApicId);
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId); SendIpi (IcrLow.Uint32, ApicId);
if (!StandardSignatureIsAuthenticAMD ()) { if (!StandardSignatureIsAuthenticAMD ()) {
MicroSecondDelay (200); MicroSecondDelay (200);
@@ -547,20 +548,20 @@ SendInitSipiSipi (
VOID VOID
EFIAPI EFIAPI
SendInitSipiSipiAllExcludingSelf ( SendInitSipiSipiAllExcludingSelf (
IN UINT32 StartupRoutine IN UINT32 StartupRoutine
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000); ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0); ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf (); SendInitIpiAllExcludingSelf ();
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0); SendIpi (IcrLow.Uint32, 0);
if (!StandardSignatureIsAuthenticAMD ()) { if (!StandardSignatureIsAuthenticAMD ()) {
@@ -616,13 +617,13 @@ ProgramVirtualWireMode (
VOID VOID
) )
{ {
LOCAL_APIC_SVR Svr; LOCAL_APIC_SVR Svr;
LOCAL_APIC_LVT_LINT Lint; LOCAL_APIC_LVT_LINT Lint;
// //
// Enable the APIC via SVR and set the spurious interrupt to use Int 00F. // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
// //
Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET); Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
Svr.Bits.SpuriousVector = 0xf; Svr.Bits.SpuriousVector = 0xf;
Svr.Bits.SoftwareEnable = 1; Svr.Bits.SoftwareEnable = 1;
WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32); WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
@@ -630,21 +631,21 @@ ProgramVirtualWireMode (
// //
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high. // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
// //
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT; Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
Lint.Bits.InputPinPolarity = 0; Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0; Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0; Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32); WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
// //
// Program the LINT0 vector entry as NMI. Not masked, edge, active high. // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
// //
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI; Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
Lint.Bits.InputPinPolarity = 0; Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0; Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0; Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32); WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
} }
@@ -659,13 +660,13 @@ DisableLvtInterrupts (
VOID VOID
) )
{ {
LOCAL_APIC_LVT_LINT LvtLint; LOCAL_APIC_LVT_LINT LvtLint;
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
LvtLint.Bits.Mask = 1; LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32); WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
LvtLint.Bits.Mask = 1; LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32); WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
} }
@@ -712,15 +713,15 @@ GetApicTimerCurrentCount (
VOID VOID
EFIAPI EFIAPI
InitializeApicTimer ( InitializeApicTimer (
IN UINTN DivideValue, IN UINTN DivideValue,
IN UINT32 InitCount, IN UINT32 InitCount,
IN BOOLEAN PeriodicMode, IN BOOLEAN PeriodicMode,
IN UINT8 Vector IN UINT8 Vector
) )
{ {
LOCAL_APIC_DCR Dcr; LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
UINT32 Divisor; UINT32 Divisor;
// //
// Ensure local APIC is in software-enabled state. // Ensure local APIC is in software-enabled state.
@@ -734,10 +735,10 @@ InitializeApicTimer (
if (DivideValue != 0) { if (DivideValue != 0) {
ASSERT (DivideValue <= 128); ASSERT (DivideValue <= 128);
ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue)); ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7); Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Bits.DivideValue1 = (Divisor & 0x3); Dcr.Bits.DivideValue1 = (Divisor & 0x3);
Dcr.Bits.DivideValue2 = (Divisor >> 2); Dcr.Bits.DivideValue2 = (Divisor >> 2);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
@@ -752,7 +753,8 @@ InitializeApicTimer (
} else { } else {
LvtTimer.Bits.TimerMode = 0; LvtTimer.Bits.TimerMode = 0;
} }
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector; LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
} }
@@ -774,25 +776,25 @@ GetApicTimerState (
OUT UINT8 *Vector OPTIONAL OUT UINT8 *Vector OPTIONAL
) )
{ {
UINT32 Divisor; UINT32 Divisor;
LOCAL_APIC_DCR Dcr; LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
// //
// Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
// Vector Register. // Vector Register.
// This bit will be 1, if local APIC is software enabled. // This bit will be 1, if local APIC is software enabled.
// //
ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
if (DivideValue != NULL) { if (DivideValue != NULL) {
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2); Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
Divisor = (Divisor + 1) & 0x7; Divisor = (Divisor + 1) & 0x7;
*DivideValue = ((UINTN)1) << Divisor; *DivideValue = ((UINTN)1) << Divisor;
} }
if (PeriodicMode != NULL || Vector != NULL) { if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) { if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) { if (LvtTimer.Bits.TimerMode == 1) {
@@ -801,8 +803,9 @@ GetApicTimerState (
*PeriodicMode = FALSE; *PeriodicMode = FALSE;
} }
} }
if (Vector != NULL) { if (Vector != NULL) {
*Vector = (UINT8) LvtTimer.Bits.Vector; *Vector = (UINT8)LvtTimer.Bits.Vector;
} }
} }
} }
@@ -816,9 +819,9 @@ EnableApicTimerInterrupt (
VOID VOID
) )
{ {
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
} }
@@ -832,9 +835,9 @@ DisableApicTimerInterrupt (
VOID VOID
) )
{ {
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 1; LvtTimer.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
} }
@@ -851,7 +854,7 @@ GetApicTimerInterruptState (
VOID VOID
) )
{ {
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
return (BOOLEAN)(LvtTimer.Bits.Mask == 0); return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
@@ -944,6 +947,7 @@ GetApicMsiValue (
MsiData.Bits.Level = 1; MsiData.Bits.Level = 1;
} }
} }
return MsiData.Uint64; return MsiData.Uint64;
} }
@@ -995,12 +999,15 @@ GetProcessorLocationByApicId (
if (Thread != NULL) { if (Thread != NULL) {
*Thread = 0; *Thread = 0;
} }
if (Core != NULL) { if (Core != NULL) {
*Core = 0; *Core = 0;
} }
if (Package != NULL) { if (Package != NULL) {
*Package = 0; *Package = 0;
} }
return; return;
} }
@@ -1008,7 +1015,7 @@ GetProcessorLocationByApicId (
// Assume three-level mapping of APIC ID: Package|Core|Thread. // Assume three-level mapping of APIC ID: Package|Core|Thread.
// //
ThreadBits = 0; ThreadBits = 0;
CoreBits = 0; CoreBits = 0;
// //
// Get max index of CPUID // Get max index of CPUID
@@ -1022,7 +1029,7 @@ GetProcessorLocationByApicId (
// //
TopologyLeafSupported = FALSE; TopologyLeafSupported = FALSE;
if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx( AsmCpuidEx (
CPUID_EXTENDED_TOPOLOGY, CPUID_EXTENDED_TOPOLOGY,
0, 0,
&ExtendedTopologyEax.Uint32, &ExtendedTopologyEax.Uint32,
@@ -1065,6 +1072,7 @@ GetProcessorLocationByApicId (
CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break; break;
} }
SubIndex++; SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
} }
@@ -1085,7 +1093,7 @@ GetProcessorLocationByApicId (
// //
// Check for topology extensions on AMD processor // Check for topology extensions on AMD processor
// //
if (StandardSignatureIsAuthenticAMD()) { if (StandardSignatureIsAuthenticAMD ()) {
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
@@ -1102,8 +1110,7 @@ GetProcessorLocationByApicId (
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
} }
} }
} } else {
else {
// //
// Extract core count based on CACHE information // Extract core count based on CACHE information
// //
@@ -1115,16 +1122,18 @@ GetProcessorLocationByApicId (
} }
} }
ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
} }
if (Thread != NULL) { if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1); *Thread = InitialApicId & ((1 << ThreadBits) - 1);
} }
if (Core != NULL) { if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
} }
if (Package != NULL) { if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits)); *Package = (InitialApicId >> (ThreadBits + CoreBits));
} }
@@ -1158,13 +1167,13 @@ GetProcessorLocation2ByApicId (
OUT UINT32 *Thread OPTIONAL OUT UINT32 *Thread OPTIONAL
) )
{ {
CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
UINT32 MaxStandardCpuIdIndex; UINT32 MaxStandardCpuIdIndex;
UINT32 Index; UINT32 Index;
UINTN LevelType; UINTN LevelType;
UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
Bits[LevelType] = 0; Bits[LevelType] = 0;
@@ -1178,12 +1187,15 @@ GetProcessorLocation2ByApicId (
if (Die != NULL) { if (Die != NULL) {
*Die = 0; *Die = 0;
} }
if (Tile != NULL) { if (Tile != NULL) {
*Tile = 0; *Tile = 0;
} }
if (Module != NULL) { if (Module != NULL) {
*Module = 0; *Module = 0;
} }
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return; return;
} }
@@ -1193,7 +1205,7 @@ GetProcessorLocation2ByApicId (
// is the preferred mechanism for enumerating topology. // is the preferred mechanism for enumerating topology.
// //
for (Index = 0; ; Index++) { for (Index = 0; ; Index++) {
AsmCpuidEx( AsmCpuidEx (
CPUID_V2_EXTENDED_TOPOLOGY, CPUID_V2_EXTENDED_TOPOLOGY,
Index, Index,
&ExtendedTopologyEax.Uint32, &ExtendedTopologyEax.Uint32,
@@ -1211,6 +1223,7 @@ GetProcessorLocation2ByApicId (
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break; break;
} }
ASSERT (LevelType < ARRAY_SIZE (Bits)); ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift; Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
} }
@@ -1226,18 +1239,19 @@ GetProcessorLocation2ByApicId (
} }
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core; Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread; Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32; Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
; LevelType ++ ; LevelType++
) { )
{
if (Location[LevelType] != NULL) { if (Location[LevelType] != NULL) {
// //
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique

280
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
View File

@@ -45,13 +45,14 @@ LocalApicBaseAddressMsrSupported (
AsmCpuid (1, &RegEax, NULL, NULL, NULL); AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11); FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) { if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
// //
// CPUs with a FamilyId of 0x04 or 0x05 do not support the // CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR // Local APIC Base Address MSR
// //
return FALSE; return FALSE;
} }
return TRUE; return TRUE;
} }
@@ -79,8 +80,8 @@ GetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
} }
/** /**
@@ -94,7 +95,7 @@ GetLocalApicBaseAddress (
VOID VOID
EFIAPI EFIAPI
SetLocalApicBaseAddress ( SetLocalApicBaseAddress (
IN UINTN BaseAddress IN UINTN BaseAddress
) )
{ {
MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
@@ -110,8 +111,8 @@ SetLocalApicBaseAddress (
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.ApicBase = (UINT32) (BaseAddress >> 12); ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32)); ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
} }
@@ -135,12 +136,12 @@ ReadLocalApicReg (
IN UINTN MmioOffset IN UINTN MmioOffset
) )
{ {
UINT32 MsrIndex; UINT32 MsrIndex;
ASSERT ((MmioOffset & 0xf) == 0); ASSERT ((MmioOffset & 0xf) == 0);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset); return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);
} else { } else {
// //
// DFR is not supported in x2APIC mode. // DFR is not supported in x2APIC mode.
@@ -174,16 +175,16 @@ ReadLocalApicReg (
VOID VOID
EFIAPI EFIAPI
WriteLocalApicReg ( WriteLocalApicReg (
IN UINTN MmioOffset, IN UINTN MmioOffset,
IN UINT32 Value IN UINT32 Value
) )
{ {
UINT32 MsrIndex; UINT32 MsrIndex;
ASSERT ((MmioOffset & 0xf) == 0); ASSERT ((MmioOffset & 0xf) == 0);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value); MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);
} else { } else {
// //
// DFR is not supported in x2APIC mode. // DFR is not supported in x2APIC mode.
@@ -216,15 +217,15 @@ WriteLocalApicReg (
**/ **/
VOID VOID
SendIpi ( SendIpi (
IN UINT32 IcrLow, IN UINT32 IcrLow,
IN UINT32 ApicId IN UINT32 ApicId
) )
{ {
UINT64 MsrValue; UINT64 MsrValue;
LOCAL_APIC_ICR_LOW IcrLowReg; LOCAL_APIC_ICR_LOW IcrLowReg;
UINTN LocalApciBaseAddress; UINTN LocalApciBaseAddress;
UINT32 IcrHigh; UINT32 IcrHigh;
BOOLEAN InterruptState; BOOLEAN InterruptState;
// //
// Legacy APIC or X2APIC? // Legacy APIC or X2APIC?
@@ -237,7 +238,7 @@ SendIpi (
// //
// Get base address of this LAPIC // Get base address of this LAPIC
// //
LocalApciBaseAddress = GetLocalApicBaseAddress(); LocalApciBaseAddress = GetLocalApicBaseAddress ();
// //
// Save existing contents of ICR high 32 bits // Save existing contents of ICR high 32 bits
@@ -271,13 +272,12 @@ SendIpi (
MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh); MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState); SetInterruptState (InterruptState);
} else { } else {
// //
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
// interrupt in x2APIC mode. // interrupt in x2APIC mode.
// //
MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow; MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow;
AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue); AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);
} }
} }
@@ -354,7 +354,7 @@ SetApicMode (
case LOCAL_APIC_MODE_XAPIC: case LOCAL_APIC_MODE_XAPIC:
break; break;
case LOCAL_APIC_MODE_X2APIC: case LOCAL_APIC_MODE_X2APIC:
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.EXTD = 1; ApicBaseMsr.Bits.EXTD = 1;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
break; break;
@@ -368,9 +368,9 @@ SetApicMode (
// Transition from x2APIC mode to xAPIC mode is a two-step process: // Transition from x2APIC mode to xAPIC mode is a two-step process:
// x2APIC -> Local APIC disabled -> xAPIC // x2APIC -> Local APIC disabled -> xAPIC
// //
ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.EXTD = 0; ApicBaseMsr.Bits.EXTD = 0;
ApicBaseMsr.Bits.EN = 0; ApicBaseMsr.Bits.EN = 0;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
ApicBaseMsr.Bits.EN = 1; ApicBaseMsr.Bits.EN = 1;
AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
@@ -398,9 +398,9 @@ GetInitialApicId (
VOID VOID
) )
{ {
UINT32 ApicId; UINT32 ApicId;
UINT32 MaxCpuIdIndex; UINT32 MaxCpuIdIndex;
UINT32 RegEbx; UINT32 RegEbx;
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
// //
@@ -419,6 +419,7 @@ GetInitialApicId (
return ApicId; return ApicId;
} }
} }
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
return RegEbx >> 24; return RegEbx >> 24;
} else { } else {
@@ -437,8 +438,8 @@ GetApicId (
VOID VOID
) )
{ {
UINT32 ApicId; UINT32 ApicId;
UINT32 InitApicId; UINT32 InitApicId;
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET); ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) { if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {
@@ -473,16 +474,16 @@ GetApicVersion (
VOID VOID
EFIAPI EFIAPI
SendFixedIpi ( SendFixedIpi (
IN UINT32 ApicId, IN UINT32 ApicId,
IN UINT8 Vector IN UINT8 Vector
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.Vector = Vector; IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, ApicId); SendIpi (IcrLow.Uint32, ApicId);
} }
@@ -496,16 +497,16 @@ SendFixedIpi (
VOID VOID
EFIAPI EFIAPI
SendFixedIpiAllExcludingSelf ( SendFixedIpiAllExcludingSelf (
IN UINT8 Vector IN UINT8 Vector
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
IcrLow.Bits.Vector = Vector; IcrLow.Bits.Vector = Vector;
SendIpi (IcrLow.Uint32, 0); SendIpi (IcrLow.Uint32, 0);
} }
@@ -519,14 +520,14 @@ SendFixedIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendSmiIpi ( SendSmiIpi (
IN UINT32 ApicId IN UINT32 ApicId
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId); SendIpi (IcrLow.Uint32, ApicId);
} }
@@ -541,11 +542,11 @@ SendSmiIpiAllExcludingSelf (
VOID VOID
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0); SendIpi (IcrLow.Uint32, 0);
} }
@@ -560,14 +561,14 @@ SendSmiIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendInitIpi ( SendInitIpi (
IN UINT32 ApicId IN UINT32 ApicId
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId); SendIpi (IcrLow.Uint32, ApicId);
} }
@@ -582,11 +583,11 @@ SendInitIpiAllExcludingSelf (
VOID VOID
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0); SendIpi (IcrLow.Uint32, 0);
} }
@@ -606,21 +607,21 @@ SendInitIpiAllExcludingSelf (
VOID VOID
EFIAPI EFIAPI
SendInitSipiSipi ( SendInitSipiSipi (
IN UINT32 ApicId, IN UINT32 ApicId,
IN UINT32 StartupRoutine IN UINT32 StartupRoutine
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000); ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0); ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpi (ApicId); SendInitIpi (ApicId);
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
SendIpi (IcrLow.Uint32, ApicId); SendIpi (IcrLow.Uint32, ApicId);
if (!StandardSignatureIsAuthenticAMD ()) { if (!StandardSignatureIsAuthenticAMD ()) {
MicroSecondDelay (200); MicroSecondDelay (200);
@@ -642,20 +643,20 @@ SendInitSipiSipi (
VOID VOID
EFIAPI EFIAPI
SendInitSipiSipiAllExcludingSelf ( SendInitSipiSipiAllExcludingSelf (
IN UINT32 StartupRoutine IN UINT32 StartupRoutine
) )
{ {
LOCAL_APIC_ICR_LOW IcrLow; LOCAL_APIC_ICR_LOW IcrLow;
ASSERT (StartupRoutine < 0x100000); ASSERT (StartupRoutine < 0x100000);
ASSERT ((StartupRoutine & 0xfff) == 0); ASSERT ((StartupRoutine & 0xfff) == 0);
SendInitIpiAllExcludingSelf (); SendInitIpiAllExcludingSelf ();
MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds)); MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));
IcrLow.Uint32 = 0; IcrLow.Uint32 = 0;
IcrLow.Bits.Vector = (StartupRoutine >> 12); IcrLow.Bits.Vector = (StartupRoutine >> 12);
IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP; IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;
IcrLow.Bits.Level = 1; IcrLow.Bits.Level = 1;
IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;
SendIpi (IcrLow.Uint32, 0); SendIpi (IcrLow.Uint32, 0);
if (!StandardSignatureIsAuthenticAMD ()) { if (!StandardSignatureIsAuthenticAMD ()) {
@@ -711,13 +712,13 @@ ProgramVirtualWireMode (
VOID VOID
) )
{ {
LOCAL_APIC_SVR Svr; LOCAL_APIC_SVR Svr;
LOCAL_APIC_LVT_LINT Lint; LOCAL_APIC_LVT_LINT Lint;
// //
// Enable the APIC via SVR and set the spurious interrupt to use Int 00F. // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
// //
Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET); Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);
Svr.Bits.SpuriousVector = 0xf; Svr.Bits.SpuriousVector = 0xf;
Svr.Bits.SoftwareEnable = 1; Svr.Bits.SoftwareEnable = 1;
WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32); WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);
@@ -725,21 +726,21 @@ ProgramVirtualWireMode (
// //
// Program the LINT0 vector entry as ExtInt. Not masked, edge, active high. // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
// //
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT; Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;
Lint.Bits.InputPinPolarity = 0; Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0; Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0; Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32); WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);
// //
// Program the LINT0 vector entry as NMI. Not masked, edge, active high. // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
// //
Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI; Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;
Lint.Bits.InputPinPolarity = 0; Lint.Bits.InputPinPolarity = 0;
Lint.Bits.TriggerMode = 0; Lint.Bits.TriggerMode = 0;
Lint.Bits.Mask = 0; Lint.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32); WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);
} }
@@ -754,13 +755,13 @@ DisableLvtInterrupts (
VOID VOID
) )
{ {
LOCAL_APIC_LVT_LINT LvtLint; LOCAL_APIC_LVT_LINT LvtLint;
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET); LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);
LvtLint.Bits.Mask = 1; LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32); WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);
LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET); LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);
LvtLint.Bits.Mask = 1; LvtLint.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32); WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);
} }
@@ -807,15 +808,15 @@ GetApicTimerCurrentCount (
VOID VOID
EFIAPI EFIAPI
InitializeApicTimer ( InitializeApicTimer (
IN UINTN DivideValue, IN UINTN DivideValue,
IN UINT32 InitCount, IN UINT32 InitCount,
IN BOOLEAN PeriodicMode, IN BOOLEAN PeriodicMode,
IN UINT8 Vector IN UINT8 Vector
) )
{ {
LOCAL_APIC_DCR Dcr; LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
UINT32 Divisor; UINT32 Divisor;
// //
// Ensure local APIC is in software-enabled state. // Ensure local APIC is in software-enabled state.
@@ -829,10 +830,10 @@ InitializeApicTimer (
if (DivideValue != 0) { if (DivideValue != 0) {
ASSERT (DivideValue <= 128); ASSERT (DivideValue <= 128);
ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue)); ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));
Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7); Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Dcr.Bits.DivideValue1 = (Divisor & 0x3); Dcr.Bits.DivideValue1 = (Divisor & 0x3);
Dcr.Bits.DivideValue2 = (Divisor >> 2); Dcr.Bits.DivideValue2 = (Divisor >> 2);
WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);
@@ -847,7 +848,8 @@ InitializeApicTimer (
} else { } else {
LvtTimer.Bits.TimerMode = 0; LvtTimer.Bits.TimerMode = 0;
} }
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector; LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
} }
@@ -869,25 +871,25 @@ GetApicTimerState (
OUT UINT8 *Vector OPTIONAL OUT UINT8 *Vector OPTIONAL
) )
{ {
UINT32 Divisor; UINT32 Divisor;
LOCAL_APIC_DCR Dcr; LOCAL_APIC_DCR Dcr;
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
// //
// Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
// Vector Register. // Vector Register.
// This bit will be 1, if local APIC is software enabled. // This bit will be 1, if local APIC is software enabled.
// //
ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0); ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);
if (DivideValue != NULL) { if (DivideValue != NULL) {
Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET); Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);
Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2); Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);
Divisor = (Divisor + 1) & 0x7; Divisor = (Divisor + 1) & 0x7;
*DivideValue = ((UINTN)1) << Divisor; *DivideValue = ((UINTN)1) << Divisor;
} }
if (PeriodicMode != NULL || Vector != NULL) { if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) { if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) { if (LvtTimer.Bits.TimerMode == 1) {
@@ -896,8 +898,9 @@ GetApicTimerState (
*PeriodicMode = FALSE; *PeriodicMode = FALSE;
} }
} }
if (Vector != NULL) { if (Vector != NULL) {
*Vector = (UINT8) LvtTimer.Bits.Vector; *Vector = (UINT8)LvtTimer.Bits.Vector;
} }
} }
} }
@@ -911,9 +914,9 @@ EnableApicTimerInterrupt (
VOID VOID
) )
{ {
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Mask = 0;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
} }
@@ -927,9 +930,9 @@ DisableApicTimerInterrupt (
VOID VOID
) )
{ {
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
LvtTimer.Bits.Mask = 1; LvtTimer.Bits.Mask = 1;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
} }
@@ -946,7 +949,7 @@ GetApicTimerInterruptState (
VOID VOID
) )
{ {
LOCAL_APIC_LVT_TIMER LvtTimer; LOCAL_APIC_LVT_TIMER LvtTimer;
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET); LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
return (BOOLEAN)(LvtTimer.Bits.Mask == 0); return (BOOLEAN)(LvtTimer.Bits.Mask == 0);
@@ -1039,6 +1042,7 @@ GetApicMsiValue (
MsiData.Bits.Level = 1; MsiData.Bits.Level = 1;
} }
} }
return MsiData.Uint64; return MsiData.Uint64;
} }
@@ -1090,12 +1094,15 @@ GetProcessorLocationByApicId (
if (Thread != NULL) { if (Thread != NULL) {
*Thread = 0; *Thread = 0;
} }
if (Core != NULL) { if (Core != NULL) {
*Core = 0; *Core = 0;
} }
if (Package != NULL) { if (Package != NULL) {
*Package = 0; *Package = 0;
} }
return; return;
} }
@@ -1103,7 +1110,7 @@ GetProcessorLocationByApicId (
// Assume three-level mapping of APIC ID: Package|Core|Thread. // Assume three-level mapping of APIC ID: Package|Core|Thread.
// //
ThreadBits = 0; ThreadBits = 0;
CoreBits = 0; CoreBits = 0;
// //
// Get max index of CPUID // Get max index of CPUID
@@ -1117,7 +1124,7 @@ GetProcessorLocationByApicId (
// //
TopologyLeafSupported = FALSE; TopologyLeafSupported = FALSE;
if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) { if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx( AsmCpuidEx (
CPUID_EXTENDED_TOPOLOGY, CPUID_EXTENDED_TOPOLOGY,
0, 0,
&ExtendedTopologyEax.Uint32, &ExtendedTopologyEax.Uint32,
@@ -1160,6 +1167,7 @@ GetProcessorLocationByApicId (
CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break; break;
} }
SubIndex++; SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
} }
@@ -1180,7 +1188,7 @@ GetProcessorLocationByApicId (
// //
// Check for topology extensions on AMD processor // Check for topology extensions on AMD processor
// //
if (StandardSignatureIsAuthenticAMD()) { if (StandardSignatureIsAuthenticAMD ()) {
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) { if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL); AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) { if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
@@ -1197,8 +1205,7 @@ GetProcessorLocationByApicId (
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
} }
} }
} } else {
else {
// //
// Extract core count based on CACHE information // Extract core count based on CACHE information
// //
@@ -1210,16 +1217,18 @@ GetProcessorLocationByApicId (
} }
} }
ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1); ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); CoreBits = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);
} }
if (Thread != NULL) { if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1); *Thread = InitialApicId & ((1 << ThreadBits) - 1);
} }
if (Core != NULL) { if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
} }
if (Package != NULL) { if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits)); *Package = (InitialApicId >> (ThreadBits + CoreBits));
} }
@@ -1253,13 +1262,13 @@ GetProcessorLocation2ByApicId (
OUT UINT32 *Thread OPTIONAL OUT UINT32 *Thread OPTIONAL
) )
{ {
CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
UINT32 MaxStandardCpuIdIndex; UINT32 MaxStandardCpuIdIndex;
UINT32 Index; UINT32 Index;
UINTN LevelType; UINTN LevelType;
UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; UINT32 Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2]; UINT32 *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];
for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) { for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {
Bits[LevelType] = 0; Bits[LevelType] = 0;
@@ -1273,12 +1282,15 @@ GetProcessorLocation2ByApicId (
if (Die != NULL) { if (Die != NULL) {
*Die = 0; *Die = 0;
} }
if (Tile != NULL) { if (Tile != NULL) {
*Tile = 0; *Tile = 0;
} }
if (Module != NULL) { if (Module != NULL) {
*Module = 0; *Module = 0;
} }
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread); GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return; return;
} }
@@ -1288,7 +1300,7 @@ GetProcessorLocation2ByApicId (
// is the preferred mechanism for enumerating topology. // is the preferred mechanism for enumerating topology.
// //
for (Index = 0; ; Index++) { for (Index = 0; ; Index++) {
AsmCpuidEx( AsmCpuidEx (
CPUID_V2_EXTENDED_TOPOLOGY, CPUID_V2_EXTENDED_TOPOLOGY,
Index, Index,
&ExtendedTopologyEax.Uint32, &ExtendedTopologyEax.Uint32,
@@ -1306,6 +1318,7 @@ GetProcessorLocation2ByApicId (
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) { if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break; break;
} }
ASSERT (LevelType < ARRAY_SIZE (Bits)); ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift; Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
} }
@@ -1321,18 +1334,19 @@ GetProcessorLocation2ByApicId (
} }
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE ] = Die; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE] = Die;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE ] = Tile; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE] = Tile;
Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module; Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE] = Module;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE ] = Core; Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE] = Core;
Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT ] = Thread; Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT] = Thread;
Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32; Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1 ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
; LevelType ++ ; LevelType++
) { )
{
if (Location[LevelType] != NULL) { if (Location[LevelType] != NULL) {
// //
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique

193
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
View File

@@ -17,21 +17,31 @@
**/ **/
VOID VOID
CpuCacheInfoPrintCpuCacheInfoTable ( CpuCacheInfoPrintCpuCacheInfoTable (
IN CPU_CACHE_INFO *CpuCacheInfo, IN CPU_CACHE_INFO *CpuCacheInfo,
IN UINTN CpuCacheInfoCount IN UINTN CpuCacheInfoCount
) )
{ {
UINTN Index; UINTN Index;
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n")); DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType CacheWays (FA|DM) CacheSizeinKB CacheCount |\n")); DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType CacheWays (FA|DM) CacheSizeinKB CacheCount |\n"));
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n")); DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
for (Index = 0; Index < CpuCacheInfoCount; Index++) { for (Index = 0; Index < CpuCacheInfoCount; Index++) {
DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n", DEBUG ((
Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel, DEBUG_INFO,
CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n",
CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount)); Index,
CpuCacheInfo[Index].Package,
CpuCacheInfo[Index].CoreType,
CpuCacheInfo[Index].CacheLevel,
CpuCacheInfo[Index].CacheType,
CpuCacheInfo[Index].CacheWays,
CpuCacheInfo[Index].FullyAssociativeCache,
CpuCacheInfo[Index].DirectMappedCache,
CpuCacheInfo[Index].CacheSizeinKB,
CpuCacheInfo[Index].CacheCount
));
} }
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n")); DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
@@ -50,24 +60,24 @@ CpuCacheInfoPrintCpuCacheInfoTable (
INTN INTN
EFIAPI EFIAPI
CpuCacheInfoCompare ( CpuCacheInfoCompare (
IN CONST VOID *Buffer1, IN CONST VOID *Buffer1,
IN CONST VOID *Buffer2 IN CONST VOID *Buffer2
) )
{ {
CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2; CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2;
ZeroMem (&Comparator1, sizeof (Comparator1)); ZeroMem (&Comparator1, sizeof (Comparator1));
ZeroMem (&Comparator2, sizeof (Comparator2)); ZeroMem (&Comparator2, sizeof (Comparator2));
Comparator1.Bits.Package = ((CPU_CACHE_INFO*)Buffer1)->Package; Comparator1.Bits.Package = ((CPU_CACHE_INFO *)Buffer1)->Package;
Comparator1.Bits.CoreType = ((CPU_CACHE_INFO*)Buffer1)->CoreType; Comparator1.Bits.CoreType = ((CPU_CACHE_INFO *)Buffer1)->CoreType;
Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer1)->CacheLevel; Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer1)->CacheLevel;
Comparator1.Bits.CacheType = ((CPU_CACHE_INFO*)Buffer1)->CacheType; Comparator1.Bits.CacheType = ((CPU_CACHE_INFO *)Buffer1)->CacheType;
Comparator2.Bits.Package = ((CPU_CACHE_INFO*)Buffer2)->Package; Comparator2.Bits.Package = ((CPU_CACHE_INFO *)Buffer2)->Package;
Comparator2.Bits.CoreType = ((CPU_CACHE_INFO*)Buffer2)->CoreType; Comparator2.Bits.CoreType = ((CPU_CACHE_INFO *)Buffer2)->CoreType;
Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer2)->CacheLevel; Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer2)->CacheLevel;
Comparator2.Bits.CacheType = ((CPU_CACHE_INFO*)Buffer2)->CacheType; Comparator2.Bits.CacheType = ((CPU_CACHE_INFO *)Buffer2)->CacheType;
if (Comparator1.Uint64 == Comparator2.Uint64) { if (Comparator1.Uint64 == Comparator2.Uint64) {
return 0; return 0;
@@ -89,15 +99,15 @@ CpuCacheInfoCompare (
**/ **/
UINT32 UINT32
CpuCacheInfoGetNumberOfPackages ( CpuCacheInfoGetNumberOfPackages (
IN CPUID_PROCESSOR_INFO *ProcessorInfo, IN CPUID_PROCESSOR_INFO *ProcessorInfo,
IN UINTN NumberOfProcessors, IN UINTN NumberOfProcessors,
IN OUT UINT32 *Package IN OUT UINT32 *Package
) )
{ {
UINTN ProcessorIndex; UINTN ProcessorIndex;
UINT32 PackageIndex; UINT32 PackageIndex;
UINT32 PackageCount; UINT32 PackageCount;
UINT32 CurrentPackage; UINT32 CurrentPackage;
PackageCount = 0; PackageCount = 0;
@@ -135,21 +145,21 @@ CpuCacheInfoGetNumberOfPackages (
@retval Return the number of CoreType of requested package. @retval Return the number of CoreType of requested package.
**/ **/
UINTN UINTN
CpuCacheInfoGetNumberOfCoreTypePerPackage( CpuCacheInfoGetNumberOfCoreTypePerPackage (
IN CPUID_PROCESSOR_INFO *ProcessorInfo, IN CPUID_PROCESSOR_INFO *ProcessorInfo,
IN UINTN NumberOfProcessors, IN UINTN NumberOfProcessors,
IN UINTN Package IN UINTN Package
) )
{ {
UINTN ProcessorIndex; UINTN ProcessorIndex;
// //
// Core Type value comes from CPUID.1Ah.EAX[31:24]. // Core Type value comes from CPUID.1Ah.EAX[31:24].
// So max number of core types should be MAX_UINT8. // So max number of core types should be MAX_UINT8.
// //
UINT8 CoreType[MAX_UINT8]; UINT8 CoreType[MAX_UINT8];
UINTN CoreTypeIndex; UINTN CoreTypeIndex;
UINTN CoreTypeCount; UINTN CoreTypeCount;
UINT8 CurrentCoreType; UINT8 CurrentCoreType;
// //
// CoreType array is empty. // CoreType array is empty.
@@ -192,23 +202,23 @@ CpuCacheInfoGetNumberOfCoreTypePerPackage(
VOID VOID
EFIAPI EFIAPI
CpuCacheInfoCollectCoreAndCacheData ( CpuCacheInfoCollectCoreAndCacheData (
IN OUT VOID *Buffer IN OUT VOID *Buffer
) )
{ {
UINTN ProcessorIndex; UINTN ProcessorIndex;
UINT32 CpuidMaxInput; UINT32 CpuidMaxInput;
UINT8 CacheParamLeafIndex; UINT8 CacheParamLeafIndex;
CPUID_CACHE_PARAMS_EAX CacheParamEax; CPUID_CACHE_PARAMS_EAX CacheParamEax;
CPUID_CACHE_PARAMS_EBX CacheParamEbx; CPUID_CACHE_PARAMS_EBX CacheParamEbx;
UINT32 CacheParamEcx; UINT32 CacheParamEcx;
CPUID_CACHE_PARAMS_EDX CacheParamEdx; CPUID_CACHE_PARAMS_EDX CacheParamEdx;
CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax; CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax;
COLLECT_CPUID_CACHE_DATA_CONTEXT *Context; COLLECT_CPUID_CACHE_DATA_CONTEXT *Context;
CPUID_CACHE_DATA *CacheData; CPUID_CACHE_DATA *CacheData;
Context = (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer; Context = (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer;
ProcessorIndex = CpuCacheInfoWhoAmI (Context->MpServices); ProcessorIndex = CpuCacheInfoWhoAmI (Context->MpServices);
CacheData = &Context->CacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF * ProcessorIndex]; CacheData = &Context->CacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF * ProcessorIndex];
AsmCpuid (CPUID_SIGNATURE, &CpuidMaxInput, NULL, NULL, NULL); AsmCpuid (CPUID_SIGNATURE, &CpuidMaxInput, NULL, NULL, NULL);
@@ -218,7 +228,7 @@ CpuCacheInfoCollectCoreAndCacheData (
Context->ProcessorInfo[ProcessorIndex].CoreType = 0; Context->ProcessorInfo[ProcessorIndex].CoreType = 0;
if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) { if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) {
AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL); AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL);
Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8) NativeModelIdAndCoreTypeEax.Bits.CoreType; Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8)NativeModelIdAndCoreTypeEax.Bits.CoreType;
} }
// //
@@ -240,7 +250,7 @@ CpuCacheInfoCollectCoreAndCacheData (
CacheData[CacheParamLeafIndex].DirectMappedCache = (UINT8)(CacheParamEdx.Bits.ComplexCacheIndexing == 0); CacheData[CacheParamLeafIndex].DirectMappedCache = (UINT8)(CacheParamEdx.Bits.ComplexCacheIndexing == 0);
CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors; CacheData[CacheParamLeafIndex].CacheShareBits = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) * CacheData[CacheParamLeafIndex].CacheSizeinKB = (CacheParamEbx.Bits.Ways + 1) *
(CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB; (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;
CacheParamLeafIndex++; CacheParamLeafIndex++;
} }
@@ -264,25 +274,25 @@ CpuCacheInfoCollectCoreAndCacheData (
**/ **/
EFI_STATUS EFI_STATUS
CpuCacheInfoCollectCpuCacheInfoData ( CpuCacheInfoCollectCpuCacheInfoData (
IN CPUID_CACHE_DATA *CacheData, IN CPUID_CACHE_DATA *CacheData,
IN CPUID_PROCESSOR_INFO *ProcessorInfo, IN CPUID_PROCESSOR_INFO *ProcessorInfo,
IN UINTN NumberOfProcessors, IN UINTN NumberOfProcessors,
IN OUT CPU_CACHE_INFO *CacheInfo, IN OUT CPU_CACHE_INFO *CacheInfo,
IN OUT UINTN *CacheInfoCount IN OUT UINTN *CacheInfoCount
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 NumberOfPackage; UINT32 NumberOfPackage;
UINT32 Package[MAX_NUM_OF_PACKAGE]; UINT32 Package[MAX_NUM_OF_PACKAGE];
UINTN PackageIndex; UINTN PackageIndex;
UINTN TotalNumberOfCoreType; UINTN TotalNumberOfCoreType;
UINTN MaxCacheInfoCount; UINTN MaxCacheInfoCount;
CPU_CACHE_INFO *LocalCacheInfo; CPU_CACHE_INFO *LocalCacheInfo;
UINTN CacheInfoIndex; UINTN CacheInfoIndex;
UINTN LocalCacheInfoCount; UINTN LocalCacheInfoCount;
UINTN Index; UINTN Index;
UINTN NextIndex; UINTN NextIndex;
CPU_CACHE_INFO SortBuffer; CPU_CACHE_INFO SortBuffer;
// //
// Get number of Packages and Package ID. // Get number of Packages and Package ID.
@@ -299,7 +309,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
} }
MaxCacheInfoCount = TotalNumberOfCoreType * MAX_NUM_OF_CACHE_PARAMS_LEAF; MaxCacheInfoCount = TotalNumberOfCoreType * MAX_NUM_OF_CACHE_PARAMS_LEAF;
LocalCacheInfo = AllocatePages (EFI_SIZE_TO_PAGES (MaxCacheInfoCount * sizeof (*LocalCacheInfo))); LocalCacheInfo = AllocatePages (EFI_SIZE_TO_PAGES (MaxCacheInfoCount * sizeof (*LocalCacheInfo)));
ASSERT (LocalCacheInfo != NULL); ASSERT (LocalCacheInfo != NULL);
if (LocalCacheInfo == NULL) { if (LocalCacheInfo == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
@@ -320,12 +330,13 @@ CpuCacheInfoCollectCpuCacheInfoData (
continue; continue;
} }
if (CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel && if ((CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel) &&
CacheData[Index].CacheType == CacheData[NextIndex].CacheType && (CacheData[Index].CacheType == CacheData[NextIndex].CacheType) &&
ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package && (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&
ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType && (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&
(ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) == ((ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) ==
(ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)) { (ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)))
{
CacheData[NextIndex].CacheSizeinKB = 0; // uses the sharing cache CacheData[NextIndex].CacheSizeinKB = 0; // uses the sharing cache
} }
} }
@@ -334,10 +345,11 @@ CpuCacheInfoCollectCpuCacheInfoData (
// For the cache that already exists in LocalCacheInfo, increase its CacheCount. // For the cache that already exists in LocalCacheInfo, increase its CacheCount.
// //
for (CacheInfoIndex = 0; CacheInfoIndex < LocalCacheInfoCount; CacheInfoIndex++) { for (CacheInfoIndex = 0; CacheInfoIndex < LocalCacheInfoCount; CacheInfoIndex++) {
if (LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package && if ((LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&
LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType && (LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&
LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel && (LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel) &&
LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType) { (LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType))
{
LocalCacheInfo[CacheInfoIndex].CacheCount++; LocalCacheInfo[CacheInfoIndex].CacheCount++;
break; break;
} }
@@ -370,11 +382,11 @@ CpuCacheInfoCollectCpuCacheInfoData (
// //
// Sort LocalCacheInfo array by CPU package ID, core type, cache level and cache type. // Sort LocalCacheInfo array by CPU package ID, core type, cache level and cache type.
// //
QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID*) &SortBuffer); QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID *)&SortBuffer);
CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheInfoCount); CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheInfoCount);
DEBUG_CODE ( DEBUG_CODE (
CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount); CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);
); );
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
} }
@@ -405,23 +417,23 @@ CpuCacheInfoCollectCpuCacheInfoData (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
GetCpuCacheInfo ( GetCpuCacheInfo (
IN OUT CPU_CACHE_INFO *CpuCacheInfo, IN OUT CPU_CACHE_INFO *CpuCacheInfo,
IN OUT UINTN *CpuCacheInfoCount IN OUT UINTN *CpuCacheInfoCount
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINT32 CpuidMaxInput; UINT32 CpuidMaxInput;
UINT32 NumberOfProcessors; UINT32 NumberOfProcessors;
UINTN CacheDataCount; UINTN CacheDataCount;
UINTN ProcessorIndex; UINTN ProcessorIndex;
EFI_PROCESSOR_INFORMATION ProcessorInfo; EFI_PROCESSOR_INFORMATION ProcessorInfo;
COLLECT_CPUID_CACHE_DATA_CONTEXT Context; COLLECT_CPUID_CACHE_DATA_CONTEXT Context;
if (CpuCacheInfoCount == NULL) { if (CpuCacheInfoCount == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (*CpuCacheInfoCount != 0 && CpuCacheInfo == NULL) { if ((*CpuCacheInfoCount != 0) && (CpuCacheInfo == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -445,13 +457,14 @@ GetCpuCacheInfo (
if (Context.ProcessorInfo == NULL) { if (Context.ProcessorInfo == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
// //
// Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CacheData. // Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CacheData.
// CacheData array consists of CPUID_CACHE_DATA data structure for each Cpuid Cache Parameter Leaf // CacheData array consists of CPUID_CACHE_DATA data structure for each Cpuid Cache Parameter Leaf
// per logical processor. The array begin with data of each Cache Parameter Leaf of processor 0, followed // per logical processor. The array begin with data of each Cache Parameter Leaf of processor 0, followed
// by data of each Cache Parameter Leaf of processor 1 ... // by data of each Cache Parameter Leaf of processor 1 ...
// //
CacheDataCount = NumberOfProcessors * MAX_NUM_OF_CACHE_PARAMS_LEAF; CacheDataCount = NumberOfProcessors * MAX_NUM_OF_CACHE_PARAMS_LEAF;
Context.CacheData = AllocatePages (EFI_SIZE_TO_PAGES (CacheDataCount * sizeof (*Context.CacheData))); Context.CacheData = AllocatePages (EFI_SIZE_TO_PAGES (CacheDataCount * sizeof (*Context.CacheData)));
ASSERT (Context.CacheData != NULL); ASSERT (Context.CacheData != NULL);
if (Context.CacheData == NULL) { if (Context.CacheData == NULL) {
@@ -467,7 +480,7 @@ GetCpuCacheInfo (
for (ProcessorIndex = 0; ProcessorIndex < NumberOfProcessors; ProcessorIndex++) { for (ProcessorIndex = 0; ProcessorIndex < NumberOfProcessors; ProcessorIndex++) {
CpuCacheInfoGetProcessorInfo (Context.MpServices, ProcessorIndex, &ProcessorInfo); CpuCacheInfoGetProcessorInfo (Context.MpServices, ProcessorIndex, &ProcessorInfo);
Context.ProcessorInfo[ProcessorIndex].Package = ProcessorInfo.Location.Package; Context.ProcessorInfo[ProcessorIndex].Package = ProcessorInfo.Location.Package;
Context.ProcessorInfo[ProcessorIndex].ApicId = (UINT32) ProcessorInfo.ProcessorId; Context.ProcessorInfo[ProcessorIndex].ApicId = (UINT32)ProcessorInfo.ProcessorId;
} }
// //

35
UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c
View File

@@ -23,10 +23,10 @@
**/ **/
EFI_STATUS EFI_STATUS
CpuCacheInfoGetMpServices ( CpuCacheInfoGetMpServices (
OUT MP_SERVICES *MpServices OUT MP_SERVICES *MpServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices->Protocol); Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices->Protocol);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -43,12 +43,12 @@ CpuCacheInfoGetMpServices (
**/ **/
VOID VOID
CpuCacheInfoStartupAllCPUs ( CpuCacheInfoStartupAllCPUs (
IN MP_SERVICES MpServices, IN MP_SERVICES MpServices,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN VOID *ProcedureArgument IN VOID *ProcedureArgument
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = MpServices.Protocol->StartupAllAPs (MpServices.Protocol, Procedure, FALSE, NULL, 0, ProcedureArgument, NULL); Status = MpServices.Protocol->StartupAllAPs (MpServices.Protocol, Procedure, FALSE, NULL, 0, ProcedureArgument, NULL);
if (Status == EFI_NOT_STARTED) { if (Status == EFI_NOT_STARTED) {
@@ -58,6 +58,7 @@ CpuCacheInfoStartupAllCPUs (
// //
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
} }
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
Procedure (ProcedureArgument); Procedure (ProcedureArgument);
@@ -72,12 +73,12 @@ CpuCacheInfoStartupAllCPUs (
**/ **/
VOID VOID
CpuCacheInfoGetProcessorInfo ( CpuCacheInfoGetProcessorInfo (
IN MP_SERVICES MpServices, IN MP_SERVICES MpServices,
IN UINTN ProcessorNum, IN UINTN ProcessorNum,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = MpServices.Protocol->GetProcessorInfo (MpServices.Protocol, ProcessorNum, ProcessorInfo); Status = MpServices.Protocol->GetProcessorInfo (MpServices.Protocol, ProcessorNum, ProcessorInfo);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -92,11 +93,11 @@ CpuCacheInfoGetProcessorInfo (
**/ **/
UINT32 UINT32
CpuCacheInfoWhoAmI ( CpuCacheInfoWhoAmI (
IN MP_SERVICES MpServices IN MP_SERVICES MpServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN ProcessorNum; UINTN ProcessorNum;
Status = MpServices.Protocol->WhoAmI (MpServices.Protocol, &ProcessorNum); Status = MpServices.Protocol->WhoAmI (MpServices.Protocol, &ProcessorNum);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -113,12 +114,12 @@ CpuCacheInfoWhoAmI (
**/ **/
UINT32 UINT32
CpuCacheInfoGetNumberOfProcessors ( CpuCacheInfoGetNumberOfProcessors (
IN MP_SERVICES MpServices IN MP_SERVICES MpServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN NumberOfProcessor; UINTN NumberOfProcessor;
UINTN NumberOfEnabledProcessor; UINTN NumberOfEnabledProcessor;
Status = MpServices.Protocol->GetNumberOfProcessors (MpServices.Protocol, &NumberOfProcessor, &NumberOfEnabledProcessor); Status = MpServices.Protocol->GetNumberOfProcessors (MpServices.Protocol, &NumberOfProcessor, &NumberOfEnabledProcessor);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

64
UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
View File

@@ -25,24 +25,24 @@ typedef union {
// Type of the cache that this package's this type of logical processor corresponds to. // Type of the cache that this package's this type of logical processor corresponds to.
// Value = CPUID.04h:EAX[04:00] // Value = CPUID.04h:EAX[04:00]
// //
UINT32 CacheType : 5; UINT32 CacheType : 5;
// //
// Level of the cache that this package's this type of logical processor corresponds to. // Level of the cache that this package's this type of logical processor corresponds to.
// Value = CPUID.04h:EAX[07:05] // Value = CPUID.04h:EAX[07:05]
// //
UINT32 CacheLevel : 3; UINT32 CacheLevel : 3;
// //
// Core type of logical processor. // Core type of logical processor.
// Value = CPUID.1Ah:EAX[31:24] // Value = CPUID.1Ah:EAX[31:24]
// //
UINT32 CoreType : 8; UINT32 CoreType : 8;
UINT32 Reserved : 16; UINT32 Reserved : 16;
// //
// Package number. // Package number.
// //
UINT32 Package; UINT32 Package;
} Bits; } Bits;
UINT64 Uint64; UINT64 Uint64;
} CPU_CACHE_INFO_COMPARATOR; } CPU_CACHE_INFO_COMPARATOR;
typedef struct { typedef struct {
@@ -50,17 +50,17 @@ typedef struct {
// Package ID, the information comes from // Package ID, the information comes from
// EFI_CPU_PHYSICAL_LOCATION.Package // EFI_CPU_PHYSICAL_LOCATION.Package
// //
UINT32 Package; UINT32 Package;
// //
// APIC ID, the information comes from // APIC ID, the information comes from
// EFI_PROCESSOR_INFORMATION.ProcessorId // EFI_PROCESSOR_INFORMATION.ProcessorId
// //
UINT32 ApicId; UINT32 ApicId;
// //
// Core type of logical processor. // Core type of logical processor.
// Value = CPUID.1Ah:EAX[31:24] // Value = CPUID.1Ah:EAX[31:24]
// //
UINT8 CoreType; UINT8 CoreType;
} CPUID_PROCESSOR_INFO; } CPUID_PROCESSOR_INFO;
typedef struct { typedef struct {
@@ -68,39 +68,39 @@ typedef struct {
// Level of the cache. // Level of the cache.
// Value = CPUID.04h:EAX[07:05] // Value = CPUID.04h:EAX[07:05]
// //
UINT8 CacheLevel : 3; UINT8 CacheLevel : 3;
// //
// Type of the cache. // Type of the cache.
// Value = CPUID.04h:EAX[04:00] // Value = CPUID.04h:EAX[04:00]
// //
UINT8 CacheType : 5; UINT8 CacheType : 5;
// //
// Ways of associativity. // Ways of associativity.
// Value = CPUID.04h:EBX[31:22] // Value = CPUID.04h:EBX[31:22]
// //
UINT16 CacheWays : 10; UINT16 CacheWays : 10;
// //
// Fully associative cache. // Fully associative cache.
// Value = CPUID.04h:EAX[09] // Value = CPUID.04h:EAX[09]
// //
UINT16 FullyAssociativeCache : 1; UINT16 FullyAssociativeCache : 1;
// //
// Direct mapped cache. // Direct mapped cache.
// Value = CPUID.04h:EDX[02] // Value = CPUID.04h:EDX[02]
// //
UINT16 DirectMappedCache : 1; UINT16 DirectMappedCache : 1;
UINT16 Reserved : 4; UINT16 Reserved : 4;
// //
// Cache share bits. // Cache share bits.
// Value = CPUID.04h:EAX[25:14] // Value = CPUID.04h:EAX[25:14]
// //
UINT16 CacheShareBits; UINT16 CacheShareBits;
// //
// Size of single cache. // Size of single cache.
// Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) * // Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *
// (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1) // (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1)
// //
UINT32 CacheSizeinKB; UINT32 CacheSizeinKB;
} CPUID_CACHE_DATA; } CPUID_CACHE_DATA;
typedef union { typedef union {
@@ -109,24 +109,23 @@ typedef union {
} MP_SERVICES; } MP_SERVICES;
typedef struct { typedef struct {
MP_SERVICES MpServices; MP_SERVICES MpServices;
CPUID_PROCESSOR_INFO *ProcessorInfo; CPUID_PROCESSOR_INFO *ProcessorInfo;
CPUID_CACHE_DATA *CacheData; CPUID_CACHE_DATA *CacheData;
} COLLECT_CPUID_CACHE_DATA_CONTEXT; } COLLECT_CPUID_CACHE_DATA_CONTEXT;
/* /*
Defines the maximum count of Deterministic Cache Parameters Leaf of all APs and BSP. Defines the maximum count of Deterministic Cache Parameters Leaf of all APs and BSP.
To save boot time, skip starting up all APs to calculate each AP's count of Deterministic To save boot time, skip starting up all APs to calculate each AP's count of Deterministic
Cache Parameters Leaf, so use a definition instead. Cache Parameters Leaf, so use a definition instead.
Anyway, definition value will be checked in CpuCacheInfoCollectCoreAndCacheData function. Anyway, definition value will be checked in CpuCacheInfoCollectCoreAndCacheData function.
*/ */
#define MAX_NUM_OF_CACHE_PARAMS_LEAF 6 #define MAX_NUM_OF_CACHE_PARAMS_LEAF 6
/* /*
Defines the maximum count of packages. Defines the maximum count of packages.
*/ */
#define MAX_NUM_OF_PACKAGE 100 #define MAX_NUM_OF_PACKAGE 100
/** /**
Get EDKII_PEI_MP_SERVICES2_PPI or EFI_MP_SERVICES_PROTOCOL pointer. Get EDKII_PEI_MP_SERVICES2_PPI or EFI_MP_SERVICES_PROTOCOL pointer.
@@ -139,7 +138,7 @@ typedef struct {
**/ **/
EFI_STATUS EFI_STATUS
CpuCacheInfoGetMpServices ( CpuCacheInfoGetMpServices (
OUT MP_SERVICES *MpServices OUT MP_SERVICES *MpServices
); );
/** /**
@@ -151,9 +150,9 @@ CpuCacheInfoGetMpServices (
**/ **/
VOID VOID
CpuCacheInfoStartupAllCPUs ( CpuCacheInfoStartupAllCPUs (
IN MP_SERVICES MpServices, IN MP_SERVICES MpServices,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN VOID *ProcedureArgument IN VOID *ProcedureArgument
); );
/** /**
@@ -165,9 +164,9 @@ CpuCacheInfoStartupAllCPUs (
**/ **/
VOID VOID
CpuCacheInfoGetProcessorInfo ( CpuCacheInfoGetProcessorInfo (
IN MP_SERVICES MpServices, IN MP_SERVICES MpServices,
IN UINTN ProcessorNum, IN UINTN ProcessorNum,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
); );
/** /**
@@ -179,7 +178,7 @@ CpuCacheInfoGetProcessorInfo (
**/ **/
UINT32 UINT32
CpuCacheInfoWhoAmI ( CpuCacheInfoWhoAmI (
IN MP_SERVICES MpServices IN MP_SERVICES MpServices
); );
/** /**
@@ -191,6 +190,7 @@ CpuCacheInfoWhoAmI (
**/ **/
UINT32 UINT32
CpuCacheInfoGetNumberOfProcessors ( CpuCacheInfoGetNumberOfProcessors (
IN MP_SERVICES MpServices IN MP_SERVICES MpServices
); );
#endif #endif

34
UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c
View File

@@ -24,10 +24,10 @@
**/ **/
EFI_STATUS EFI_STATUS
CpuCacheInfoGetMpServices ( CpuCacheInfoGetMpServices (
OUT MP_SERVICES *MpServices OUT MP_SERVICES *MpServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = PeiServicesLocatePpi (&gEdkiiPeiMpServices2PpiGuid, 0, NULL, (VOID **)&MpServices->Ppi); Status = PeiServicesLocatePpi (&gEdkiiPeiMpServices2PpiGuid, 0, NULL, (VOID **)&MpServices->Ppi);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -44,12 +44,12 @@ CpuCacheInfoGetMpServices (
**/ **/
VOID VOID
CpuCacheInfoStartupAllCPUs ( CpuCacheInfoStartupAllCPUs (
IN MP_SERVICES MpServices, IN MP_SERVICES MpServices,
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN VOID *ProcedureArgument IN VOID *ProcedureArgument
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = MpServices.Ppi->StartupAllCPUs (MpServices.Ppi, Procedure, 0, ProcedureArgument); Status = MpServices.Ppi->StartupAllCPUs (MpServices.Ppi, Procedure, 0, ProcedureArgument);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -64,12 +64,12 @@ CpuCacheInfoStartupAllCPUs (
**/ **/
VOID VOID
CpuCacheInfoGetProcessorInfo ( CpuCacheInfoGetProcessorInfo (
IN MP_SERVICES MpServices, IN MP_SERVICES MpServices,
IN UINTN ProcessorNum, IN UINTN ProcessorNum,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = MpServices.Ppi->GetProcessorInfo (MpServices.Ppi, ProcessorNum, ProcessorInfo); Status = MpServices.Ppi->GetProcessorInfo (MpServices.Ppi, ProcessorNum, ProcessorInfo);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -84,11 +84,11 @@ CpuCacheInfoGetProcessorInfo (
**/ **/
UINT32 UINT32
CpuCacheInfoWhoAmI ( CpuCacheInfoWhoAmI (
IN MP_SERVICES MpServices IN MP_SERVICES MpServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN ProcessorNum; UINTN ProcessorNum;
Status = MpServices.Ppi->WhoAmI (MpServices.Ppi, &ProcessorNum); Status = MpServices.Ppi->WhoAmI (MpServices.Ppi, &ProcessorNum);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
@@ -105,12 +105,12 @@ CpuCacheInfoWhoAmI (
**/ **/
UINT32 UINT32
CpuCacheInfoGetNumberOfProcessors ( CpuCacheInfoGetNumberOfProcessors (
IN MP_SERVICES MpServices IN MP_SERVICES MpServices
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN NumberOfProcessor; UINTN NumberOfProcessor;
UINTN NumberOfEnabledProcessor; UINTN NumberOfEnabledProcessor;
Status = MpServices.Ppi->GetNumberOfProcessors (MpServices.Ppi, &NumberOfProcessor, &NumberOfEnabledProcessor); Status = MpServices.Ppi->GetNumberOfProcessors (MpServices.Ppi, &NumberOfProcessor, &NumberOfEnabledProcessor);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

12
UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
View File

@@ -23,7 +23,7 @@ AesniGetConfigData (
IN UINTN NumberOfProcessors IN UINTN NumberOfProcessors
) )
{ {
UINT64 *ConfigData; UINT64 *ConfigData;
ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors); ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
@@ -54,14 +54,15 @@ AesniSupport (
IN VOID *ConfigData OPTIONAL IN VOID *ConfigData OPTIONAL
) )
{ {
MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) { if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {
MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData; MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
ASSERT (MsrFeatureConfig != NULL); ASSERT (MsrFeatureConfig != NULL);
MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG); MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
return TRUE; return TRUE;
} }
return FALSE; return FALSE;
} }
@@ -91,7 +92,7 @@ AesniInitialize (
IN BOOLEAN State IN BOOLEAN State
) )
{ {
MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig; MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *MsrFeatureConfig;
// //
// SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index, // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,
@@ -102,7 +103,7 @@ AesniInitialize (
// programming it. // programming it.
// //
if (CpuInfo->ProcessorInfo.Location.Thread == 0) { if (CpuInfo->ProcessorInfo.Location.Thread == 0) {
MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData; MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;
ASSERT (MsrFeatureConfig != NULL); ASSERT (MsrFeatureConfig != NULL);
if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) { if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {
CPU_REGISTER_TABLE_WRITE_FIELD ( CPU_REGISTER_TABLE_WRITE_FIELD (
@@ -115,5 +116,6 @@ AesniInitialize (
); );
} }
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

2
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
View File

@@ -66,7 +66,7 @@ C1eInitialize (
// MSR_NEHALEM_POWER_CTL once for each package. // MSR_NEHALEM_POWER_CTL once for each package.
// //
if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) { if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
CPU_REGISTER_TABLE_WRITE_FIELD ( CPU_REGISTER_TABLE_WRITE_FIELD (

19
UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
View File

@@ -9,8 +9,8 @@
#include "CpuCommonFeatures.h" #include "CpuCommonFeatures.h"
typedef struct { typedef struct {
CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax; CPUID_THERMAL_POWER_MANAGEMENT_EAX ThermalPowerManagementEax;
MSR_IA32_CLOCK_MODULATION_REGISTER ClockModulation; MSR_IA32_CLOCK_MODULATION_REGISTER ClockModulation;
} CLOCK_MODULATION_CONFIG_DATA; } CLOCK_MODULATION_CONFIG_DATA;
/** /**
@@ -28,7 +28,7 @@ ClockModulationGetConfigData (
IN UINTN NumberOfProcessors IN UINTN NumberOfProcessors
) )
{ {
UINT32 *ConfigData; UINT32 *ConfigData;
ConfigData = AllocateZeroPool (sizeof (CLOCK_MODULATION_CONFIG_DATA) * NumberOfProcessors); ConfigData = AllocateZeroPool (sizeof (CLOCK_MODULATION_CONFIG_DATA) * NumberOfProcessors);
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
@@ -59,10 +59,10 @@ ClockModulationSupport (
IN VOID *ConfigData OPTIONAL IN VOID *ConfigData OPTIONAL
) )
{ {
CLOCK_MODULATION_CONFIG_DATA *CmConfigData; CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) { if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) {
CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData; CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;
ASSERT (CmConfigData != NULL); ASSERT (CmConfigData != NULL);
AsmCpuid ( AsmCpuid (
CPUID_THERMAL_POWER_MANAGEMENT, CPUID_THERMAL_POWER_MANAGEMENT,
@@ -74,6 +74,7 @@ ClockModulationSupport (
CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION); CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
return TRUE; return TRUE;
} }
return FALSE; return FALSE;
} }
@@ -103,15 +104,15 @@ ClockModulationInitialize (
IN BOOLEAN State IN BOOLEAN State
) )
{ {
CLOCK_MODULATION_CONFIG_DATA *CmConfigData; CLOCK_MODULATION_CONFIG_DATA *CmConfigData;
MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation; MSR_IA32_CLOCK_MODULATION_REGISTER *ClockModulation;
CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData; CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;
ASSERT (CmConfigData != NULL); ASSERT (CmConfigData != NULL);
ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation; ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation;
if (State) { if (State) {
ClockModulation->Bits.OnDemandClockModulationEnable = 1; ClockModulation->Bits.OnDemandClockModulationEnable = 1;
ClockModulation->Bits.OnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1; ClockModulation->Bits.OnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1;
if (CmConfigData[ProcessorNumber].ThermalPowerManagementEax.Bits.ECMD == 1) { if (CmConfigData[ProcessorNumber].ThermalPowerManagementEax.Bits.ECMD == 1) {
ClockModulation->Bits.ExtendedOnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0; ClockModulation->Bits.ExtendedOnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0;

2
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
View File

@@ -860,7 +860,7 @@ X2ApicInitialize (
VOID * VOID *
EFIAPI EFIAPI
PpinGetConfigData ( PpinGetConfigData (
IN UINTN NumberOfProcessors IN UINTN NumberOfProcessors
); );
/** /**

22
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
View File

@@ -20,7 +20,7 @@ CpuCommonFeaturesLibConstructor (
VOID VOID
) )
{ {
RETURN_STATUS Status; RETURN_STATUS Status;
if (IsCpuFeatureSupported (CPU_FEATURE_AESNI)) { if (IsCpuFeatureSupported (CPU_FEATURE_AESNI)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
@@ -33,6 +33,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) { if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"MWAIT", "MWAIT",
@@ -44,6 +45,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) { if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"ACPI", "ACPI",
@@ -55,6 +57,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) { if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"EIST", "EIST",
@@ -66,6 +69,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) { if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"FastStrings", "FastStrings",
@@ -77,6 +81,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) { if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Lock Feature Control Register", "Lock Feature Control Register",
@@ -88,6 +93,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) { if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"SMX", "SMX",
@@ -100,6 +106,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) { if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"VMX", "VMX",
@@ -112,6 +119,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) { if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Limit CpuId Maximum Value", "Limit CpuId Maximum Value",
@@ -123,6 +131,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) { if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Machine Check Enable", "Machine Check Enable",
@@ -134,6 +143,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) { if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Machine Check Architect", "Machine Check Architect",
@@ -145,6 +155,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) { if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"MCG_CTL", "MCG_CTL",
@@ -156,6 +167,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) { if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Pending Break", "Pending Break",
@@ -167,6 +179,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) { if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"C1E", "C1E",
@@ -178,6 +191,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) { if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"X2Apic", "X2Apic",
@@ -189,6 +203,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) { if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"PPIN", "PPIN",
@@ -200,6 +215,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"LMCE", "LMCE",
@@ -212,6 +228,7 @@ CpuCommonFeaturesLibConstructor (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) { if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) {
Status = RegisterCpuFeature ( Status = RegisterCpuFeature (
"Proc Trace", "Proc Trace",
@@ -226,6 +243,3 @@ CpuCommonFeaturesLibConstructor (
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
View File

@@ -69,7 +69,8 @@ EistInitialize (
// //
if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
View File

@@ -40,7 +40,8 @@ FastStringsInitialize (
// //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

15
UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
View File

@@ -68,7 +68,8 @@ VmxInitialize (
// //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -146,7 +147,8 @@ LockFeatureControlRegisterInitialize (
// //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -218,7 +220,7 @@ SmxInitialize (
IN BOOLEAN State IN BOOLEAN State
) )
{ {
RETURN_STATUS Status; RETURN_STATUS Status;
// //
// The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for
@@ -226,7 +228,8 @@ SmxInitialize (
// core. // core.
// //
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -236,7 +239,7 @@ SmxInitialize (
if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) { if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) {
DEBUG ((DEBUG_WARN, "Warning :: Can't enable SMX feature when VMX feature not enabled, disable it.\n")); DEBUG ((DEBUG_WARN, "Warning :: Can't enable SMX feature when VMX feature not enabled, disable it.\n"));
State = FALSE; State = FALSE;
Status = RETURN_UNSUPPORTED; Status = RETURN_UNSUPPORTED;
} }
@@ -247,7 +250,7 @@ SmxInitialize (
IA32_CR4, IA32_CR4,
Bits.SMXE, Bits.SMXE,
(State) ? 1 : 0 (State) ? 1 : 0
) )
CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (
ProcessorNumber, ProcessorNumber,

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
View File

@@ -72,7 +72,8 @@ LimitCpuidMaxvalInitialize (
IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

21
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
View File

@@ -102,6 +102,7 @@ McaSupport (
if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) { if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE; return FALSE;
} }
return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1); return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);
} }
@@ -144,7 +145,8 @@ McaInitialize (
IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -162,7 +164,7 @@ McaInitialize (
if (State) { if (State) {
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) { for (BankIndex = 0; BankIndex < (UINT32)McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -172,7 +174,7 @@ McaInitialize (
} }
if (PcdGetBool (PcdIsPowerOnReset)) { if (PcdGetBool (PcdIsPowerOnReset)) {
for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) { for (BankIndex = 0; BankIndex < (UINTN)McgCap.Bits.Count; BankIndex++) {
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -215,6 +217,7 @@ McgCtlSupport (
if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) { if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE; return FALSE;
} }
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
return (McgCap.Bits.MCG_CTL_P == 1); return (McgCap.Bits.MCG_CTL_P == 1);
} }
@@ -249,7 +252,7 @@ McgCtlInitialize (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
MSR_IA32_MCG_CTL, MSR_IA32_MCG_CTL,
(State)? MAX_UINT64 : 0 (State) ? MAX_UINT64 : 0
); );
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
@@ -279,7 +282,7 @@ LmceSupport (
IN VOID *ConfigData OPTIONAL IN VOID *ConfigData OPTIONAL
) )
{ {
MSR_IA32_MCG_CAP_REGISTER McgCap; MSR_IA32_MCG_CAP_REGISTER McgCap;
if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) { if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE; return FALSE;
@@ -287,9 +290,10 @@ LmceSupport (
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP); McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
if (ProcessorNumber == 0) { if (ProcessorNumber == 0) {
DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0))); DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0)));
} }
return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0);
return (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0);
} }
/** /**
@@ -325,7 +329,8 @@ LmceInitialize (
// //
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
View File

@@ -70,7 +70,8 @@ MonitorMwaitInitialize (
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

4
UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
View File

@@ -36,9 +36,11 @@ PendingBreakSupport (
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1); return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1);
} }
return FALSE; return FALSE;
} }

21
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
View File

@@ -20,10 +20,10 @@
VOID * VOID *
EFIAPI EFIAPI
PpinGetConfigData ( PpinGetConfigData (
IN UINTN NumberOfProcessors IN UINTN NumberOfProcessors
) )
{ {
VOID *ConfigData; VOID *ConfigData;
ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors); ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
@@ -55,8 +55,8 @@ PpinSupport (
IN VOID *ConfigData OPTIONAL IN VOID *ConfigData OPTIONAL
) )
{ {
MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo; MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo;
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
if ((CpuInfo->DisplayFamily == 0x06) && if ((CpuInfo->DisplayFamily == 0x06) &&
((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2 ((CpuInfo->DisplayModel == 0x3E) || // Xeon E5 V2
@@ -65,13 +65,14 @@ PpinSupport (
(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable (CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series. (CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor (CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
)) { ))
{
// //
// Check whether platform support this feature. // Check whether platform support this feature.
// //
PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1); PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
if (PlatformInfo.Bits.PPIN_CAP != 0) { if (PlatformInfo.Bits.PPIN_CAP != 0) {
MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
ASSERT (MsrPpinCtrl != NULL); ASSERT (MsrPpinCtrl != NULL);
MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
return TRUE; return TRUE;
@@ -112,9 +113,9 @@ PpinInitialize (
IN BOOLEAN State IN BOOLEAN State
) )
{ {
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl;
MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;
ASSERT (MsrPpinCtrl != NULL); ASSERT (MsrPpinCtrl != NULL);
// //
@@ -143,14 +144,14 @@ PpinInitialize (
// According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP. // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.
// //
MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1; MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;
MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0; MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;
} else { } else {
// //
// Disable and Lock. // Disable and Lock.
// According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear. // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.
// //
MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0; MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;
MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1; MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;
} }
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (

181
UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
View File

@@ -17,8 +17,7 @@
/// be terminated by an entry with the END bit set to 1, so 2 /// be terminated by an entry with the END bit set to 1, so 2
/// entries are required to use a single valid entry. /// entries are required to use a single valid entry.
/// ///
#define MAX_TOPA_ENTRY_COUNT 2 #define MAX_TOPA_ENTRY_COUNT 2
/// ///
/// Processor trace output scheme selection. /// Processor trace output scheme selection.
@@ -29,25 +28,25 @@ typedef enum {
} RTIT_OUTPUT_SCHEME; } RTIT_OUTPUT_SCHEME;
typedef struct { typedef struct {
BOOLEAN TopaSupported; BOOLEAN TopaSupported;
BOOLEAN SingleRangeSupported; BOOLEAN SingleRangeSupported;
MSR_IA32_RTIT_CTL_REGISTER RtitCtrl; MSR_IA32_RTIT_CTL_REGISTER RtitCtrl;
MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase; MSR_IA32_RTIT_OUTPUT_BASE_REGISTER RtitOutputBase;
MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs; MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER RtitOutputMaskPtrs;
} PROC_TRACE_PROCESSOR_DATA; } PROC_TRACE_PROCESSOR_DATA;
typedef struct { typedef struct {
UINT32 NumberOfProcessors; UINT32 NumberOfProcessors;
UINT8 ProcTraceOutputScheme; UINT8 ProcTraceOutputScheme;
UINT32 ProcTraceMemSize; UINT32 ProcTraceMemSize;
UINTN *ThreadMemRegionTable; UINTN *ThreadMemRegionTable;
UINTN AllocatedThreads; UINTN AllocatedThreads;
UINTN *TopaMemArray; UINTN *TopaMemArray;
PROC_TRACE_PROCESSOR_DATA *ProcessorData; PROC_TRACE_PROCESSOR_DATA *ProcessorData;
} PROC_TRACE_DATA; } PROC_TRACE_DATA;
typedef struct { typedef struct {
@@ -73,10 +72,10 @@ ProcTraceGetConfigData (
ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors); ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA)); ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *)((UINT8 *)ConfigData + sizeof (PROC_TRACE_DATA));
ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors; ConfigData->NumberOfProcessors = (UINT32)NumberOfProcessors;
ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize); ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);
ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme); ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);
return ConfigData; return ConfigData;
@@ -107,17 +106,18 @@ ProcTraceSupport (
IN VOID *ConfigData OPTIONAL IN VOID *ConfigData OPTIONAL
) )
{ {
PROC_TRACE_DATA *ProcTraceData; PROC_TRACE_DATA *ProcTraceData;
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;
// //
// Check if ProcTraceMemorySize option is enabled (0xFF means disable by user) // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)
// //
ProcTraceData = (PROC_TRACE_DATA *) ConfigData; ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
ASSERT (ProcTraceData != NULL); ASSERT (ProcTraceData != NULL);
if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) || if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||
(ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) { (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA))
{
return FALSE; return FALSE;
} }
@@ -130,12 +130,13 @@ ProcTraceSupport (
} }
AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL); AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);
ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1); ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN)(Ecx.Bits.RTIT == 1);
ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1); ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1);
if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) || if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||
(ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) { (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)))
ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL); {
ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE); ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS); ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
return TRUE; return TRUE;
} }
@@ -170,36 +171,37 @@ ProcTraceInitialize (
IN BOOLEAN State IN BOOLEAN State
) )
{ {
UINT32 MemRegionSize; UINT32 MemRegionSize;
UINTN Pages; UINTN Pages;
UINTN Alignment; UINTN Alignment;
UINTN MemRegionBaseAddr; UINTN MemRegionBaseAddr;
UINTN *ThreadMemRegionTable; UINTN *ThreadMemRegionTable;
UINTN Index; UINTN Index;
UINTN TopaTableBaseAddr; UINTN TopaTableBaseAddr;
UINTN AlignedAddress; UINTN AlignedAddress;
UINTN *TopaMemArray; UINTN *TopaMemArray;
PROC_TRACE_TOPA_TABLE *TopaTable; PROC_TRACE_TOPA_TABLE *TopaTable;
PROC_TRACE_DATA *ProcTraceData; PROC_TRACE_DATA *ProcTraceData;
BOOLEAN FirstIn; BOOLEAN FirstIn;
MSR_IA32_RTIT_CTL_REGISTER CtrlReg; MSR_IA32_RTIT_CTL_REGISTER CtrlReg;
MSR_IA32_RTIT_STATUS_REGISTER StatusReg; MSR_IA32_RTIT_STATUS_REGISTER StatusReg;
MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg; MSR_IA32_RTIT_OUTPUT_BASE_REGISTER OutputBaseReg;
MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg; MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER OutputMaskPtrsReg;
RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr; RTIT_TOPA_TABLE_ENTRY *TopaEntryPtr;
// //
// The scope of the MSR_IA32_RTIT_* is core for below processor type, only program // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program
// MSR_IA32_RTIT_* for thread 0 in each core. // MSR_IA32_RTIT_* for thread 0 in each core.
// //
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) || if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) { IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) { if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
} }
ProcTraceData = (PROC_TRACE_DATA *) ConfigData; ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
ASSERT (ProcTraceData != NULL); ASSERT (ProcTraceData != NULL);
// //
@@ -235,7 +237,7 @@ ProcTraceInitialize (
} }
MemRegionBaseAddr = 0; MemRegionBaseAddr = 0;
FirstIn = FALSE; FirstIn = FALSE;
if (ProcTraceData->ThreadMemRegionTable == NULL) { if (ProcTraceData->ThreadMemRegionTable == NULL) {
FirstIn = TRUE; FirstIn = TRUE;
@@ -245,7 +247,7 @@ ProcTraceInitialize (
/// ///
/// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding
/// ///
MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12)); MemRegionSize = (UINT32)(1 << (ProcTraceData->ProcTraceMemSize + 12));
if (FirstIn) { if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize)); DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));
} }
@@ -258,32 +260,34 @@ ProcTraceInitialize (
// address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be // address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be
// aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared. // aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared.
// //
ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *)); ThreadMemRegionTable = (UINTN *)AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));
if (ThreadMemRegionTable == NULL) { if (ThreadMemRegionTable == NULL) {
DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n")); DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable; ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) { for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
Pages = EFI_SIZE_TO_PAGES (MemRegionSize); Pages = EFI_SIZE_TO_PAGES (MemRegionSize);
Alignment = MemRegionSize; Alignment = MemRegionSize;
AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment); AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);
if (AlignedAddress == 0) { if (AlignedAddress == 0) {
DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads)); DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));
if (Index == 0) { if (Index == 0) {
// //
// Could not allocate for BSP even // Could not allocate for BSP even
// //
FreePool ((VOID *) ThreadMemRegionTable); FreePool ((VOID *)ThreadMemRegionTable);
ThreadMemRegionTable = NULL; ThreadMemRegionTable = NULL;
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
break; break;
} }
ThreadMemRegionTable[Index] = AlignedAddress; ThreadMemRegionTable[Index] = AlignedAddress;
DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index])); DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64)ThreadMemRegionTable[Index]));
} }
DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads)); DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));
@@ -303,7 +307,8 @@ ProcTraceInitialize (
// Single Range output scheme // Single Range output scheme
// //
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) { (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))
{
if (FirstIn) { if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n")); DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
} }
@@ -322,9 +327,9 @@ ProcTraceInitialize (
// //
// Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region
// //
OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64; OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF; OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;
OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF; OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -335,9 +340,9 @@ ProcTraceInitialize (
// //
// Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h) // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)
// //
OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64; OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF; OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;
OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF; OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -350,7 +355,8 @@ ProcTraceInitialize (
// ToPA(Table of physical address) scheme // ToPA(Table of physical address) scheme
// //
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) { (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA))
{
// //
// Create ToPA structure aligned at 4KB for each logical thread // Create ToPA structure aligned at 4KB for each logical thread
// with at least 2 entries by 8 bytes size each. The first entry // with at least 2 entries by 8 bytes size each. The first entry
@@ -364,35 +370,38 @@ ProcTraceInitialize (
// //
// Let BSP allocate ToPA table mem for all threads // Let BSP allocate ToPA table mem for all threads
// //
TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *)); TopaMemArray = (UINTN *)AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));
if (TopaMemArray == NULL) { if (TopaMemArray == NULL) {
DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n")); DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
ProcTraceData->TopaMemArray = TopaMemArray; ProcTraceData->TopaMemArray = TopaMemArray;
for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) { for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE)); Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));
Alignment = 0x1000; Alignment = 0x1000;
AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment); AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);
if (AlignedAddress == 0) { if (AlignedAddress == 0) {
if (Index < ProcTraceData->AllocatedThreads) { if (Index < ProcTraceData->AllocatedThreads) {
ProcTraceData->AllocatedThreads = Index; ProcTraceData->AllocatedThreads = Index;
} }
DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads)); DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
if (Index == 0) { if (Index == 0) {
// //
// Could not allocate for BSP even // Could not allocate for BSP even
// //
FreePool ((VOID *) TopaMemArray); FreePool ((VOID *)TopaMemArray);
TopaMemArray = NULL; TopaMemArray = NULL;
return RETURN_OUT_OF_RESOURCES; return RETURN_OUT_OF_RESOURCES;
} }
break; break;
} }
TopaMemArray[Index] = AlignedAddress; TopaMemArray[Index] = AlignedAddress;
DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index])); DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64)TopaMemArray[Index]));
} }
DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads)); DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));
@@ -404,26 +413,26 @@ ProcTraceInitialize (
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }
TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr; TopaTable = (PROC_TRACE_TOPA_TABLE *)TopaTableBaseAddr;
TopaEntryPtr = &TopaTable->TopaEntry[0]; TopaEntryPtr = &TopaTable->TopaEntry[0];
TopaEntryPtr->Uint64 = 0; TopaEntryPtr->Uint64 = 0;
TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF; TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;
TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF; TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;
TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize; TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;
TopaEntryPtr->Bits.END = 0; TopaEntryPtr->Bits.END = 0;
TopaEntryPtr = &TopaTable->TopaEntry[1]; TopaEntryPtr = &TopaTable->TopaEntry[1];
TopaEntryPtr->Uint64 = 0; TopaEntryPtr->Uint64 = 0;
TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF; TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;
TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF; TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;
TopaEntryPtr->Bits.END = 1; TopaEntryPtr->Bits.END = 1;
// //
// Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base
// //
OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64; OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;
OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF; OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;
OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF; OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -434,9 +443,9 @@ ProcTraceInitialize (
// //
// Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0 // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0
// //
OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64; OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;
OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0; OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;
OutputMaskPtrsReg.Bits.OutputOffset = 0; OutputMaskPtrsReg.Bits.OutputOffset = 0;
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,
@@ -458,10 +467,10 @@ ProcTraceInitialize (
/// ///
/// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h) /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)
/// ///
CtrlReg.Bits.OS = 1; CtrlReg.Bits.OS = 1;
CtrlReg.Bits.User = 1; CtrlReg.Bits.User = 1;
CtrlReg.Bits.BranchEn = 1; CtrlReg.Bits.BranchEn = 1;
CtrlReg.Bits.TraceEn = 1; CtrlReg.Bits.TraceEn = 1;
CPU_REGISTER_TABLE_WRITE64 ( CPU_REGISTER_TABLE_WRITE64 (
ProcessorNumber, ProcessorNumber,
Msr, Msr,

11
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
View File

@@ -23,7 +23,7 @@ X2ApicGetConfigData (
IN UINTN NumberOfProcessors IN UINTN NumberOfProcessors
) )
{ {
BOOLEAN *ConfigData; BOOLEAN *ConfigData;
ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors); ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
@@ -56,10 +56,10 @@ X2ApicSupport (
IN VOID *ConfigData OPTIONAL IN VOID *ConfigData OPTIONAL
) )
{ {
BOOLEAN *X2ApicEnabled; BOOLEAN *X2ApicEnabled;
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
X2ApicEnabled = (BOOLEAN *) ConfigData; X2ApicEnabled = (BOOLEAN *)ConfigData;
// //
// *ConfigData indicates if X2APIC enabled on current processor // *ConfigData indicates if X2APIC enabled on current processor
// //
@@ -94,7 +94,7 @@ X2ApicInitialize (
IN BOOLEAN State IN BOOLEAN State
) )
{ {
BOOLEAN *X2ApicEnabled; BOOLEAN *X2ApicEnabled;
// //
// The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program // The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program
@@ -107,7 +107,7 @@ X2ApicInitialize (
} }
ASSERT (ConfigData != NULL); ASSERT (ConfigData != NULL);
X2ApicEnabled = (BOOLEAN *) ConfigData; X2ApicEnabled = (BOOLEAN *)ConfigData;
if (X2ApicEnabled[ProcessorNumber]) { if (X2ApicEnabled[ProcessorNumber]) {
PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD ( PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber, ProcessorNumber,
@@ -133,5 +133,6 @@ X2ApicInitialize (
); );
} }
} }
return RETURN_SUCCESS; return RETURN_SUCCESS;
} }

41
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
View File

@@ -14,15 +14,15 @@
// //
// 1 means an error code will be pushed, otherwise 0 // 1 means an error code will be pushed, otherwise 0
// //
CONST UINT32 mErrorCodeFlag = 0x20227d00; CONST UINT32 mErrorCodeFlag = 0x20227d00;
// //
// Define the maximum message length // Define the maximum message length
// //
#define MAX_DEBUG_MESSAGE_LENGTH 0x100 #define MAX_DEBUG_MESSAGE_LENGTH 0x100
CONST CHAR8 mExceptionReservedStr[] = "Reserved"; CONST CHAR8 mExceptionReservedStr[] = "Reserved";
CONST CHAR8 *mExceptionNameStr[] = { CONST CHAR8 *mExceptionNameStr[] = {
"#DE - Divide Error", "#DE - Divide Error",
"#DB - Debug", "#DB - Debug",
"NMI Interrupt", "NMI Interrupt",
@@ -66,10 +66,10 @@ CONST CHAR8 *mExceptionNameStr[] = {
**/ **/
CONST CHAR8 * CONST CHAR8 *
GetExceptionNameStr ( GetExceptionNameStr (
IN EFI_EXCEPTION_TYPE ExceptionType IN EFI_EXCEPTION_TYPE ExceptionType
) )
{ {
if ((UINTN) ExceptionType < EXCEPTION_KNOWN_NAME_NUM) { if ((UINTN)ExceptionType < EXCEPTION_KNOWN_NAME_NUM) {
return mExceptionNameStr[ExceptionType]; return mExceptionNameStr[ExceptionType];
} else { } else {
return mExceptionReservedStr; return mExceptionReservedStr;
@@ -115,13 +115,13 @@ InternalPrintMessage (
**/ **/
VOID VOID
DumpModuleImageInfo ( DumpModuleImageInfo (
IN UINTN CurrentEip IN UINTN CurrentEip
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Pe32Data; UINTN Pe32Data;
VOID *PdbPointer; VOID *PdbPointer;
VOID *EntryPoint; VOID *EntryPoint;
Pe32Data = PeCoffSearchImageBase (CurrentEip); Pe32Data = PeCoffSearchImageBase (CurrentEip);
if (Pe32Data == 0) { if (Pe32Data == 0) {
@@ -130,20 +130,22 @@ DumpModuleImageInfo (
// //
// Find Image Base entry point // Find Image Base entry point
// //
Status = PeCoffLoaderGetEntryPoint ((VOID *) Pe32Data, &EntryPoint); Status = PeCoffLoaderGetEntryPoint ((VOID *)Pe32Data, &EntryPoint);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
EntryPoint = NULL; EntryPoint = NULL;
} }
InternalPrintMessage ("!!!! Find image based on IP(0x%x) ", CurrentEip); InternalPrintMessage ("!!!! Find image based on IP(0x%x) ", CurrentEip);
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data); PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);
if (PdbPointer != NULL) { if (PdbPointer != NULL) {
InternalPrintMessage ("%a", PdbPointer); InternalPrintMessage ("%a", PdbPointer);
} else { } else {
InternalPrintMessage ("(No PDB) " ); InternalPrintMessage ("(No PDB) ");
} }
InternalPrintMessage ( InternalPrintMessage (
" (ImageBase=%016lp, EntryPoint=%016p) !!!!\n", " (ImageBase=%016lp, EntryPoint=%016p) !!!!\n",
(VOID *) Pe32Data, (VOID *)Pe32Data,
EntryPoint EntryPoint
); );
} }
@@ -162,9 +164,9 @@ DumpModuleImageInfo (
**/ **/
EFI_STATUS EFI_STATUS
ReadAndVerifyVectorInfo ( ReadAndVerifyVectorInfo (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo,
OUT RESERVED_VECTORS_DATA *ReservedVector, OUT RESERVED_VECTORS_DATA *ReservedVector,
IN UINTN VectorCount IN UINTN VectorCount
) )
{ {
while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) { while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {
@@ -174,10 +176,13 @@ ReadAndVerifyVectorInfo (
// //
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (VectorInfo->VectorNumber < VectorCount) { if (VectorInfo->VectorNumber < VectorCount) {
ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute; ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute;
} }
VectorInfo ++;
VectorInfo++;
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }

101
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
View File

@@ -20,21 +20,21 @@
#include <Library/SynchronizationLib.h> #include <Library/SynchronizationLib.h>
#include <Library/CpuExceptionHandlerLib.h> #include <Library/CpuExceptionHandlerLib.h>
#define CPU_EXCEPTION_NUM 32 #define CPU_EXCEPTION_NUM 32
#define CPU_INTERRUPT_NUM 256 #define CPU_INTERRUPT_NUM 256
#define HOOKAFTER_STUB_SIZE 16 #define HOOKAFTER_STUB_SIZE 16
// //
// Exception Error Code of Page-Fault Exception // Exception Error Code of Page-Fault Exception
// //
#define IA32_PF_EC_P BIT0 #define IA32_PF_EC_P BIT0
#define IA32_PF_EC_WR BIT1 #define IA32_PF_EC_WR BIT1
#define IA32_PF_EC_US BIT2 #define IA32_PF_EC_US BIT2
#define IA32_PF_EC_RSVD BIT3 #define IA32_PF_EC_RSVD BIT3
#define IA32_PF_EC_ID BIT4 #define IA32_PF_EC_ID BIT4
#define IA32_PF_EC_PK BIT5 #define IA32_PF_EC_PK BIT5
#define IA32_PF_EC_SS BIT6 #define IA32_PF_EC_SS BIT6
#define IA32_PF_EC_SGX BIT15 #define IA32_PF_EC_SGX BIT15
#include "ArchInterruptDefs.h" #include "ArchInterruptDefs.h"
@@ -47,26 +47,26 @@
#define CPU_KNOWN_GOOD_STACK_SIZE \ #define CPU_KNOWN_GOOD_STACK_SIZE \
FixedPcdGet32 (PcdCpuKnownGoodStackSize) FixedPcdGet32 (PcdCpuKnownGoodStackSize)
#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) #define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)
// //
// Record exception handler information // Record exception handler information
// //
typedef struct { typedef struct {
UINTN ExceptionStart; UINTN ExceptionStart;
UINTN ExceptionStubHeaderSize; UINTN ExceptionStubHeaderSize;
UINTN HookAfterStubHeaderStart; UINTN HookAfterStubHeaderStart;
} EXCEPTION_HANDLER_TEMPLATE_MAP; } EXCEPTION_HANDLER_TEMPLATE_MAP;
typedef struct { typedef struct {
UINTN IdtEntryCount; UINTN IdtEntryCount;
SPIN_LOCK DisplayMessageSpinLock; SPIN_LOCK DisplayMessageSpinLock;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
} EXCEPTION_HANDLER_DATA; } EXCEPTION_HANDLER_DATA;
extern CONST UINT32 mErrorCodeFlag; extern CONST UINT32 mErrorCodeFlag;
extern CONST UINTN mDoFarReturnFlag; extern CONST UINTN mDoFarReturnFlag;
/** /**
Return address map of exception handler template so that C code can generate Return address map of exception handler template so that C code can generate
@@ -77,7 +77,7 @@ extern CONST UINTN mDoFarReturnFlag;
VOID VOID
EFIAPI EFIAPI
AsmGetTemplateAddressMap ( AsmGetTemplateAddressMap (
OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap
); );
/** /**
@@ -90,8 +90,8 @@ AsmGetTemplateAddressMap (
**/ **/
VOID VOID
ArchUpdateIdtEntry ( ArchUpdateIdtEntry (
OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
IN UINTN InterruptHandler IN UINTN InterruptHandler
); );
/** /**
@@ -102,7 +102,7 @@ ArchUpdateIdtEntry (
**/ **/
UINTN UINTN
ArchGetIdtHandler ( ArchGetIdtHandler (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
); );
/** /**
@@ -128,7 +128,7 @@ InternalPrintMessage (
**/ **/
VOID VOID
DumpModuleImageInfo ( DumpModuleImageInfo (
IN UINTN CurrentEip IN UINTN CurrentEip
); );
/** /**
@@ -139,8 +139,8 @@ DumpModuleImageInfo (
**/ **/
VOID VOID
DumpImageAndCpuContent ( DumpImageAndCpuContent (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
); );
/** /**
@@ -157,8 +157,8 @@ DumpImageAndCpuContent (
**/ **/
EFI_STATUS EFI_STATUS
InitializeCpuExceptionHandlersWorker ( InitializeCpuExceptionHandlersWorker (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData
); );
/** /**
@@ -180,9 +180,9 @@ InitializeCpuExceptionHandlersWorker (
**/ **/
EFI_STATUS EFI_STATUS
RegisterCpuInterruptHandlerWorker ( RegisterCpuInterruptHandlerWorker (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
); );
/** /**
@@ -210,9 +210,9 @@ UpdateIdtTable (
**/ **/
VOID VOID
ArchSaveExceptionContext ( ArchSaveExceptionContext (
IN UINTN ExceptionType, IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext, IN EFI_SYSTEM_CONTEXT SystemContext,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
); );
/** /**
@@ -224,9 +224,9 @@ ArchSaveExceptionContext (
**/ **/
VOID VOID
ArchRestoreExceptionContext ( ArchRestoreExceptionContext (
IN UINTN ExceptionType, IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext, IN EFI_SYSTEM_CONTEXT SystemContext,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
); );
/** /**
@@ -240,9 +240,9 @@ ArchRestoreExceptionContext (
VOID VOID
EFIAPI EFIAPI
AsmVectorNumFixup ( AsmVectorNumFixup (
IN VOID *NewVectorAddr, IN VOID *NewVectorAddr,
IN UINT8 VectorNum, IN UINT8 VectorNum,
IN VOID *OldVectorAddr IN VOID *OldVectorAddr
); );
/** /**
@@ -258,9 +258,9 @@ AsmVectorNumFixup (
**/ **/
EFI_STATUS EFI_STATUS
ReadAndVerifyVectorInfo ( ReadAndVerifyVectorInfo (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo,
OUT RESERVED_VECTORS_DATA *ReservedVector, OUT RESERVED_VECTORS_DATA *ReservedVector,
IN UINTN VectorCount IN UINTN VectorCount
); );
/** /**
@@ -272,7 +272,7 @@ ReadAndVerifyVectorInfo (
**/ **/
CONST CHAR8 * CONST CHAR8 *
GetExceptionNameStr ( GetExceptionNameStr (
IN EFI_EXCEPTION_TYPE ExceptionType IN EFI_EXCEPTION_TYPE ExceptionType
); );
/** /**
@@ -284,9 +284,9 @@ GetExceptionNameStr (
**/ **/
VOID VOID
CommonExceptionHandlerWorker ( CommonExceptionHandlerWorker (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext, IN EFI_SYSTEM_CONTEXT SystemContext,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
); );
/** /**
@@ -301,7 +301,7 @@ CommonExceptionHandlerWorker (
**/ **/
EFI_STATUS EFI_STATUS
ArchSetupExceptionStack ( ArchSetupExceptionStack (
IN CPU_EXCEPTION_INIT_DATA *StackSwitchData IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
); );
/** /**
@@ -318,4 +318,3 @@ AsmGetTssTemplateMap (
); );
#endif #endif

110
UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
View File

@@ -12,17 +12,17 @@
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
CONST UINTN mDoFarReturnFlag = 0; CONST UINTN mDoFarReturnFlag = 0;
RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM]; RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM]; EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
UINTN mEnabledInterruptNum = 0; UINTN mEnabledInterruptNum = 0;
EXCEPTION_HANDLER_DATA mExceptionHandlerData; EXCEPTION_HANDLER_DATA mExceptionHandlerData;
UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER * UINT8 mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *
CPU_KNOWN_GOOD_STACK_SIZE]; CPU_KNOWN_GOOD_STACK_SIZE];
UINT8 mNewGdt[CPU_TSS_GDT_SIZE]; UINT8 mNewGdt[CPU_TSS_GDT_SIZE];
/** /**
Common exception handler. Common exception handler.
@@ -33,8 +33,8 @@ UINT8 mNewGdt[CPU_TSS_GDT_SIZE];
VOID VOID
EFIAPI EFIAPI
CommonExceptionHandler ( CommonExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData); CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData);
@@ -59,7 +59,7 @@ CommonExceptionHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlers ( InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
mExceptionHandlerData.ReservedVectors = mReservedVectorsData; mExceptionHandlerData.ReservedVectors = mReservedVectorsData;
@@ -87,19 +87,19 @@ InitializeCpuExceptionHandlers (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuInterruptHandlers ( InitializeCpuInterruptHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
IA32_IDT_GATE_DESCRIPTOR *IdtTable; IA32_IDT_GATE_DESCRIPTOR *IdtTable;
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
UINTN IdtEntryCount; UINTN IdtEntryCount;
EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
UINTN Index; UINTN Index;
UINTN InterruptEntry; UINTN InterruptEntry;
UINT8 *InterruptEntryCode; UINT8 *InterruptEntryCode;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
Status = gBS->AllocatePool ( Status = gBS->AllocatePool (
EfiBootServicesCode, EfiBootServicesCode,
@@ -107,7 +107,7 @@ InitializeCpuInterruptHandlers (
(VOID **)&ReservedVectors (VOID **)&ReservedVectors
); );
ASSERT (!EFI_ERROR (Status) && ReservedVectors != NULL); ASSERT (!EFI_ERROR (Status) && ReservedVectors != NULL);
SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff); SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff);
if (VectorInfo != NULL) { if (VectorInfo != NULL) {
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_INTERRUPT_NUM); Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_INTERRUPT_NUM);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@@ -127,6 +127,7 @@ InitializeCpuInterruptHandlers (
if (IdtEntryCount > CPU_INTERRUPT_NUM) { if (IdtEntryCount > CPU_INTERRUPT_NUM) {
IdtEntryCount = CPU_INTERRUPT_NUM; IdtEntryCount = CPU_INTERRUPT_NUM;
} }
// //
// Create Interrupt Descriptor Table and Copy the old IDT table in // Create Interrupt Descriptor Table and Copy the old IDT table in
// //
@@ -144,18 +145,18 @@ InitializeCpuInterruptHandlers (
); );
ASSERT (!EFI_ERROR (Status) && InterruptEntryCode != NULL); ASSERT (!EFI_ERROR (Status) && InterruptEntryCode != NULL);
InterruptEntry = (UINTN) InterruptEntryCode; InterruptEntry = (UINTN)InterruptEntryCode;
for (Index = 0; Index < CPU_INTERRUPT_NUM; Index ++) { for (Index = 0; Index < CPU_INTERRUPT_NUM; Index++) {
CopyMem ( CopyMem (
(VOID *) InterruptEntry, (VOID *)InterruptEntry,
(VOID *) TemplateMap.ExceptionStart, (VOID *)TemplateMap.ExceptionStart,
TemplateMap.ExceptionStubHeaderSize TemplateMap.ExceptionStubHeaderSize
); );
AsmVectorNumFixup ((VOID *) InterruptEntry, (UINT8) Index, (VOID *) TemplateMap.ExceptionStart); AsmVectorNumFixup ((VOID *)InterruptEntry, (UINT8)Index, (VOID *)TemplateMap.ExceptionStart);
InterruptEntry += TemplateMap.ExceptionStubHeaderSize; InterruptEntry += TemplateMap.ExceptionStubHeaderSize;
} }
TemplateMap.ExceptionStart = (UINTN) InterruptEntryCode; TemplateMap.ExceptionStart = (UINTN)InterruptEntryCode;
mExceptionHandlerData.IdtEntryCount = CPU_INTERRUPT_NUM; mExceptionHandlerData.IdtEntryCount = CPU_INTERRUPT_NUM;
mExceptionHandlerData.ReservedVectors = ReservedVectors; mExceptionHandlerData.ReservedVectors = ReservedVectors;
mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler; mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler;
@@ -166,9 +167,9 @@ InitializeCpuInterruptHandlers (
// //
// Load Interrupt Descriptor Table // Load Interrupt Descriptor Table
// //
IdtDescriptor.Base = (UINTN) IdtTable; IdtDescriptor.Base = (UINTN)IdtTable;
IdtDescriptor.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1); IdtDescriptor.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1);
AsmWriteIdtr ((IA32_DESCRIPTOR *) &IdtDescriptor); AsmWriteIdtr ((IA32_DESCRIPTOR *)&IdtDescriptor);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -199,8 +200,8 @@ InitializeCpuInterruptHandlers (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
RegisterCpuInterruptHandler ( RegisterCpuInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
) )
{ {
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData); return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);
@@ -230,14 +231,14 @@ RegisterCpuInterruptHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlersEx ( InitializeCpuExceptionHandlersEx (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
CPU_EXCEPTION_INIT_DATA EssData; CPU_EXCEPTION_INIT_DATA EssData;
IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Idtr;
IA32_DESCRIPTOR Gdtr; IA32_DESCRIPTOR Gdtr;
// //
// To avoid repeat initialization of default handlers, the caller should pass // To avoid repeat initialization of default handlers, the caller should pass
@@ -246,7 +247,7 @@ InitializeCpuExceptionHandlersEx (
// version instead; or this method must be implemented as a simple wrapper of // version instead; or this method must be implemented as a simple wrapper of
// non-ex version of it, if this version has to be called. // non-ex version of it, if this version has to be called.
// //
if (InitData == NULL || InitData->X64.InitDefaultHandlers) { if ((InitData == NULL) || InitData->X64.InitDefaultHandlers) {
Status = InitializeCpuExceptionHandlers (VectorInfo); Status = InitializeCpuExceptionHandlers (VectorInfo);
} else { } else {
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@@ -263,25 +264,26 @@ InitializeCpuExceptionHandlersEx (
AsmReadIdtr (&Idtr); AsmReadIdtr (&Idtr);
AsmReadGdtr (&Gdtr); AsmReadGdtr (&Gdtr);
EssData.X64.Revision = CPU_EXCEPTION_INIT_DATA_REV; EssData.X64.Revision = CPU_EXCEPTION_INIT_DATA_REV;
EssData.X64.KnownGoodStackTop = (UINTN)mNewStack + sizeof (mNewStack); EssData.X64.KnownGoodStackTop = (UINTN)mNewStack + sizeof (mNewStack);
EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE; EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE;
EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST; EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;
EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER; EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;
EssData.X64.IdtTable = (VOID *)Idtr.Base; EssData.X64.IdtTable = (VOID *)Idtr.Base;
EssData.X64.IdtTableSize = Idtr.Limit + 1; EssData.X64.IdtTableSize = Idtr.Limit + 1;
EssData.X64.GdtTable = mNewGdt; EssData.X64.GdtTable = mNewGdt;
EssData.X64.GdtTableSize = sizeof (mNewGdt); EssData.X64.GdtTableSize = sizeof (mNewGdt);
EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1; EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1;
EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE; EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE;
EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE; EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;
EssData.X64.ExceptionTssSize = CPU_TSS_SIZE; EssData.X64.ExceptionTssSize = CPU_TSS_SIZE;
InitData = &EssData; InitData = &EssData;
} }
Status = ArchSetupExceptionStack (InitData); Status = ArchSetupExceptionStack (InitData);
} }
} }
return Status; return Status;
} }

140
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
View File

@@ -18,13 +18,13 @@
**/ **/
VOID VOID
ArchUpdateIdtEntry ( ArchUpdateIdtEntry (
OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
IN UINTN InterruptHandler IN UINTN InterruptHandler
) )
{ {
IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler; IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16); IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);
IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32; IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
} }
/** /**
@@ -35,7 +35,7 @@ ArchUpdateIdtEntry (
**/ **/
UINTN UINTN
ArchGetIdtHandler ( ArchGetIdtHandler (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
) )
{ {
return (UINTN)IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16); return (UINTN)IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16);
@@ -50,13 +50,13 @@ ArchGetIdtHandler (
**/ **/
VOID VOID
ArchSaveExceptionContext ( ArchSaveExceptionContext (
IN UINTN ExceptionType, IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext, IN EFI_SYSTEM_CONTEXT SystemContext,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
IA32_EFLAGS32 Eflags; IA32_EFLAGS32 Eflags;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
// //
@@ -71,13 +71,13 @@ ArchSaveExceptionContext (
// //
// Clear IF flag to avoid old IDT handler enable interrupt by IRET // Clear IF flag to avoid old IDT handler enable interrupt by IRET
// //
Eflags.UintN = SystemContext.SystemContextIa32->Eflags; Eflags.UintN = SystemContext.SystemContextIa32->Eflags;
Eflags.Bits.IF = 0; Eflags.Bits.IF = 0;
SystemContext.SystemContextIa32->Eflags = Eflags.UintN; SystemContext.SystemContextIa32->Eflags = Eflags.UintN;
// //
// Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin. // Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin.
// //
SystemContext.SystemContextIa32->Eip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode; SystemContext.SystemContextIa32->Eip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode;
} }
/** /**
@@ -89,14 +89,14 @@ ArchSaveExceptionContext (
**/ **/
VOID VOID
ArchRestoreExceptionContext ( ArchRestoreExceptionContext (
IN UINTN ExceptionType, IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext, IN EFI_SYSTEM_CONTEXT SystemContext,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
SystemContext.SystemContextIa32->Eflags = ReservedVectors[ExceptionType].OldFlags; SystemContext.SystemContextIa32->Eflags = ReservedVectors[ExceptionType].OldFlags;
SystemContext.SystemContextIa32->Cs = ReservedVectors[ExceptionType].OldCs; SystemContext.SystemContextIa32->Cs = ReservedVectors[ExceptionType].OldCs;
SystemContext.SystemContextIa32->Eip = ReservedVectors[ExceptionType].OldIp; SystemContext.SystemContextIa32->Eip = ReservedVectors[ExceptionType].OldIp;
@@ -116,32 +116,33 @@ ArchRestoreExceptionContext (
**/ **/
EFI_STATUS EFI_STATUS
ArchSetupExceptionStack ( ArchSetupExceptionStack (
IN CPU_EXCEPTION_INIT_DATA *StackSwitchData IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
) )
{ {
IA32_DESCRIPTOR Gdtr; IA32_DESCRIPTOR Gdtr;
IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Idtr;
IA32_IDT_GATE_DESCRIPTOR *IdtTable; IA32_IDT_GATE_DESCRIPTOR *IdtTable;
IA32_TSS_DESCRIPTOR *TssDesc; IA32_TSS_DESCRIPTOR *TssDesc;
IA32_TASK_STATE_SEGMENT *Tss; IA32_TASK_STATE_SEGMENT *Tss;
UINTN StackTop; UINTN StackTop;
UINTN Index; UINTN Index;
UINTN Vector; UINTN Vector;
UINTN TssBase; UINTN TssBase;
UINTN GdtSize; UINTN GdtSize;
EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
if (StackSwitchData == NULL || if ((StackSwitchData == NULL) ||
StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV || (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
StackSwitchData->Ia32.KnownGoodStackTop == 0 || (StackSwitchData->Ia32.KnownGoodStackTop == 0) ||
StackSwitchData->Ia32.KnownGoodStackSize == 0 || (StackSwitchData->Ia32.KnownGoodStackSize == 0) ||
StackSwitchData->Ia32.StackSwitchExceptions == NULL || (StackSwitchData->Ia32.StackSwitchExceptions == NULL) ||
StackSwitchData->Ia32.StackSwitchExceptionNumber == 0 || (StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) ||
StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM || (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
StackSwitchData->Ia32.GdtTable == NULL || (StackSwitchData->Ia32.GdtTable == NULL) ||
StackSwitchData->Ia32.IdtTable == NULL || (StackSwitchData->Ia32.IdtTable == NULL) ||
StackSwitchData->Ia32.ExceptionTssDesc == NULL || (StackSwitchData->Ia32.ExceptionTssDesc == NULL) ||
StackSwitchData->Ia32.ExceptionTss == NULL) { (StackSwitchData->Ia32.ExceptionTss == NULL))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -159,7 +160,8 @@ ArchSetupExceptionStack (
} }
if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize > if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize >
((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) { ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -168,11 +170,14 @@ ArchSetupExceptionStack (
// specified. // specified.
// //
if (StackSwitchData->Ia32.ExceptionTssDescSize < if (StackSwitchData->Ia32.ExceptionTssDescSize <
sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) { sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (StackSwitchData->Ia32.ExceptionTssSize < if (StackSwitchData->Ia32.ExceptionTssSize <
sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) { sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -191,13 +196,14 @@ ArchSetupExceptionStack (
(UINTN)(StackSwitchData->Ia32.GdtTable); (UINTN)(StackSwitchData->Ia32.GdtTable);
if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) { if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) {
CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable; Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable;
Gdtr.Limit = (UINT16)GdtSize - 1; Gdtr.Limit = (UINT16)GdtSize - 1;
} }
if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) { if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) {
Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable; Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable;
} }
if (StackSwitchData->Ia32.IdtTableSize > 0) { if (StackSwitchData->Ia32.IdtTableSize > 0) {
Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1); Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1);
} }
@@ -208,14 +214,14 @@ ArchSetupExceptionStack (
// //
TssBase = (UINTN)Tss; TssBase = (UINTN)Tss;
TssDesc->Uint64 = 0; TssDesc->Uint64 = 0;
TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
TssDesc->Bits.P = 1; TssDesc->Bits.P = 1;
TssDesc->Bits.LimitHigh = 0; TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24); TssDesc->Bits.BaseHigh = (UINT8)(TssBase >> 24);
// //
// Fixup exception task descriptor and task-state segment // Fixup exception task descriptor and task-state segment
@@ -234,7 +240,7 @@ ArchSetupExceptionStack (
TssBase = (UINTN)Tss; TssBase = (UINTN)Tss;
TssDesc->Uint64 = 0; TssDesc->Uint64 = 0;
TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMid = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
@@ -246,14 +252,15 @@ ArchSetupExceptionStack (
// Fixup TSS // Fixup TSS
// //
Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index]; Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index];
if (Vector >= CPU_EXCEPTION_NUM || if ((Vector >= CPU_EXCEPTION_NUM) ||
Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) { (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
{
continue; continue;
} }
ZeroMem (Tss, sizeof (*Tss)); ZeroMem (Tss, sizeof (*Tss));
Tss->EIP = (UINT32)(TemplateMap.ExceptionStart Tss->EIP = (UINT32)(TemplateMap.ExceptionStart
+ Vector * TemplateMap.ExceptionStubHeaderSize); + Vector * TemplateMap.ExceptionStubHeaderSize);
Tss->EFLAGS = 0x2; Tss->EFLAGS = 0x2;
Tss->ESP = StackTop; Tss->ESP = StackTop;
Tss->CR3 = AsmReadCr3 (); Tss->CR3 = AsmReadCr3 ();
@@ -264,7 +271,7 @@ ArchSetupExceptionStack (
Tss->FS = AsmReadFs (); Tss->FS = AsmReadFs ();
Tss->GS = AsmReadGs (); Tss->GS = AsmReadGs ();
StackTop -= StackSwitchData->Ia32.KnownGoodStackSize; StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;
// //
// Update IDT to use Task Gate for given exception // Update IDT to use Task Gate for given exception
@@ -303,8 +310,8 @@ ArchSetupExceptionStack (
VOID VOID
EFIAPI EFIAPI
DumpCpuContext ( DumpCpuContext (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
InternalPrintMessage ( InternalPrintMessage (
@@ -331,8 +338,10 @@ DumpCpuContext (
(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0 (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0
); );
} }
InternalPrintMessage ("\n"); InternalPrintMessage ("\n");
} }
InternalPrintMessage ( InternalPrintMessage (
"EIP - %08x, CS - %08x, EFLAGS - %08x\n", "EIP - %08x, CS - %08x, EFLAGS - %08x\n",
SystemContext.SystemContextIa32->Eip, SystemContext.SystemContextIa32->Eip,
@@ -406,8 +415,8 @@ DumpCpuContext (
**/ **/
VOID VOID
DumpImageAndCpuContent ( DumpImageAndCpuContent (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
DumpCpuContext (ExceptionType, SystemContext); DumpCpuContext (ExceptionType, SystemContext);
@@ -415,7 +424,8 @@ DumpImageAndCpuContent (
// Dump module image base and module entry point by EIP // Dump module image base and module entry point by EIP
// //
if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) && if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&
((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)) { ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0))
{
// //
// The EIP in SystemContext could not be used // The EIP in SystemContext could not be used
// if it is page fault with I/D set. // if it is page fault with I/D set.

28
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
View File

@@ -10,29 +10,29 @@
#define _ARCH_CPU_INTERRUPT_DEFS_H_ #define _ARCH_CPU_INTERRUPT_DEFS_H_
typedef struct { typedef struct {
EFI_SYSTEM_CONTEXT_IA32 SystemContext; EFI_SYSTEM_CONTEXT_IA32 SystemContext;
BOOLEAN ExceptionDataFlag; BOOLEAN ExceptionDataFlag;
UINTN OldIdtHandler; UINTN OldIdtHandler;
} EXCEPTION_HANDLER_CONTEXT; } EXCEPTION_HANDLER_CONTEXT;
// //
// Register Structure Definitions // Register Structure Definitions
// //
typedef struct { typedef struct {
EFI_STATUS_CODE_DATA Header; EFI_STATUS_CODE_DATA Header;
EFI_SYSTEM_CONTEXT_IA32 SystemContext; EFI_SYSTEM_CONTEXT_IA32 SystemContext;
} CPU_STATUS_CODE_TEMPLATE; } CPU_STATUS_CODE_TEMPLATE;
typedef struct { typedef struct {
SPIN_LOCK SpinLock; SPIN_LOCK SpinLock;
UINT32 ApicId; UINT32 ApicId;
UINT32 Attribute; UINT32 Attribute;
UINTN ExceptonHandler; UINTN ExceptonHandler;
UINTN OldFlags; UINTN OldFlags;
UINTN OldCs; UINTN OldCs;
UINTN OldIp; UINTN OldIp;
UINTN ExceptionData; UINTN ExceptionData;
UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE]; UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
} RESERVED_VECTORS_DATA; } RESERVED_VECTORS_DATA;
#define CPU_TSS_DESC_SIZE \ #define CPU_TSS_DESC_SIZE \

51
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
View File

@@ -13,11 +13,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
CONST UINTN mDoFarReturnFlag = 0; CONST UINTN mDoFarReturnFlag = 0;
typedef struct { typedef struct {
UINT8 ExceptionStubHeader[HOOKAFTER_STUB_SIZE]; UINT8 ExceptionStubHeader[HOOKAFTER_STUB_SIZE];
EXCEPTION_HANDLER_DATA *ExceptionHandlerData; EXCEPTION_HANDLER_DATA *ExceptionHandlerData;
} EXCEPTION0_STUB_HEADER; } EXCEPTION0_STUB_HEADER;
/** /**
@@ -34,9 +34,9 @@ GetExceptionHandlerData (
VOID VOID
) )
{ {
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
IA32_IDT_GATE_DESCRIPTOR *IdtTable; IA32_IDT_GATE_DESCRIPTOR *IdtTable;
EXCEPTION0_STUB_HEADER *Exception0StubHeader; EXCEPTION0_STUB_HEADER *Exception0StubHeader;
AsmReadIdtr (&IdtDescriptor); AsmReadIdtr (&IdtDescriptor);
IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base; IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
@@ -56,12 +56,13 @@ GetExceptionHandlerData (
**/ **/
VOID VOID
SetExceptionHandlerData ( SetExceptionHandlerData (
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
EXCEPTION0_STUB_HEADER *Exception0StubHeader; EXCEPTION0_STUB_HEADER *Exception0StubHeader;
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
IA32_IDT_GATE_DESCRIPTOR *IdtTable; IA32_IDT_GATE_DESCRIPTOR *IdtTable;
// //
// Duplicate the exception #0 stub header in pool and cache the ExceptionHandlerData just after the stub header. // Duplicate the exception #0 stub header in pool and cache the ExceptionHandlerData just after the stub header.
// So AP can get the ExceptionHandlerData by reading the IDT[0]. // So AP can get the ExceptionHandlerData by reading the IDT[0].
@@ -89,8 +90,8 @@ SetExceptionHandlerData (
VOID VOID
EFIAPI EFIAPI
CommonExceptionHandler ( CommonExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
EXCEPTION_HANDLER_DATA *ExceptionHandlerData; EXCEPTION_HANDLER_DATA *ExceptionHandlerData;
@@ -120,12 +121,12 @@ CommonExceptionHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlers ( InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EXCEPTION_HANDLER_DATA *ExceptionHandlerData; EXCEPTION_HANDLER_DATA *ExceptionHandlerData;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = AllocatePool (sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM); ReservedVectors = AllocatePool (sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM);
ASSERT (ReservedVectors != NULL); ASSERT (ReservedVectors != NULL);
@@ -166,7 +167,7 @@ InitializeCpuExceptionHandlers (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuInterruptHandlers ( InitializeCpuInterruptHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@@ -198,8 +199,8 @@ InitializeCpuInterruptHandlers (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
RegisterCpuInterruptHandler ( RegisterCpuInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@@ -230,11 +231,11 @@ RegisterCpuInterruptHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlersEx ( InitializeCpuExceptionHandlersEx (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
// //
// To avoid repeat initialization of default handlers, the caller should pass // To avoid repeat initialization of default handlers, the caller should pass
@@ -243,7 +244,7 @@ InitializeCpuExceptionHandlersEx (
// version instead; or this method must be implemented as a simple wrapper of // version instead; or this method must be implemented as a simple wrapper of
// non-ex version of it, if this version has to be called. // non-ex version of it, if this version has to be called.
// //
if (InitData == NULL || InitData->Ia32.InitDefaultHandlers) { if ((InitData == NULL) || InitData->Ia32.InitDefaultHandlers) {
Status = InitializeCpuExceptionHandlers (VectorInfo); Status = InitializeCpuExceptionHandlers (VectorInfo);
} else { } else {
Status = EFI_SUCCESS; Status = EFI_SUCCESS;
@@ -253,10 +254,10 @@ InitializeCpuExceptionHandlersEx (
// //
// Initializing stack switch is only necessary for Stack Guard functionality. // Initializing stack switch is only necessary for Stack Guard functionality.
// //
if (PcdGetBool (PcdCpuStackGuard) && InitData != NULL) { if (PcdGetBool (PcdCpuStackGuard) && (InitData != NULL)) {
Status = ArchSetupExceptionStack (InitData); Status = ArchSetupExceptionStack (InitData);
} }
} }
return Status; return Status;
} }

225
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
View File

@@ -19,14 +19,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
VOID VOID
CommonExceptionHandlerWorker ( CommonExceptionHandlerWorker (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext, IN EFI_SYSTEM_CONTEXT SystemContext,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
EXCEPTION_HANDLER_CONTEXT *ExceptionHandlerContext; EXCEPTION_HANDLER_CONTEXT *ExceptionHandlerContext;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
if (ExceptionType == VC_EXCEPTION) { if (ExceptionType == VC_EXCEPTION) {
EFI_STATUS Status; EFI_STATUS Status;
@@ -45,68 +45,72 @@ CommonExceptionHandlerWorker (
} }
} }
ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (SystemContext.SystemContextIa32); ExceptionHandlerContext = (EXCEPTION_HANDLER_CONTEXT *)(UINTN)(SystemContext.SystemContextIa32);
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler; ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;
switch (ReservedVectors[ExceptionType].Attribute) { switch (ReservedVectors[ExceptionType].Attribute) {
case EFI_VECTOR_HANDOFF_HOOK_BEFORE: case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
//
// The new exception handler registered by RegisterCpuInterruptHandler() is executed BEFORE original handler.
// Save the original handler to stack so the assembly code can jump to it instead of returning from handler.
//
ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
break;
case EFI_VECTOR_HANDOFF_HOOK_AFTER:
while (TRUE) {
// //
// If spin-lock can be acquired, it's the first time entering here. // The new exception handler registered by RegisterCpuInterruptHandler() is executed BEFORE original handler.
// Save the original handler to stack so the assembly code can jump to it instead of returning from handler.
// //
if (AcquireSpinLockOrFail (&ReservedVectors[ExceptionType].SpinLock)) { ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
break;
case EFI_VECTOR_HANDOFF_HOOK_AFTER:
while (TRUE) {
// //
// The new exception handler registered by RegisterCpuInterruptHandler() is executed AFTER original handler. // If spin-lock can be acquired, it's the first time entering here.
// Save the original handler to stack but skip running the new handler so the original handler is executed
// firstly.
// //
ReservedVectors[ExceptionType].ApicId = GetApicId (); if (AcquireSpinLockOrFail (&ReservedVectors[ExceptionType].SpinLock)) {
ArchSaveExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData); //
ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE; // The new exception handler registered by RegisterCpuInterruptHandler() is executed AFTER original handler.
ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler; // Save the original handler to stack but skip running the new handler so the original handler is executed
return; // firstly.
//
ReservedVectors[ExceptionType].ApicId = GetApicId ();
ArchSaveExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);
ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;
ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
return;
}
//
// If spin-lock cannot be acquired, it's the second time entering here.
// 'break' instead of 'return' is used so the new exception handler can be executed.
//
if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) {
//
// Old IDT handler has been executed, then restore CPU exception content to
// run new exception handler.
//
ArchRestoreExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);
//
// Release spin lock for ApicId
//
ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock);
break;
}
CpuPause ();
} }
break;
case 0xffffffff:
break;
default:
// //
// If spin-lock cannot be acquired, it's the second time entering here. // It should never reach here
// 'break' instead of 'return' is used so the new exception handler can be executed.
// //
if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) { CpuDeadLoop ();
// break;
// Old IDT handler has been executed, then restore CPU exception content to
// run new exception handler.
//
ArchRestoreExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);
//
// Release spin lock for ApicId
//
ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock);
break;
}
CpuPause ();
}
break;
case 0xffffffff:
break;
default:
//
// It should never reach here
//
CpuDeadLoop ();
break;
} }
if (ExternalInterruptHandler != NULL && if ((ExternalInterruptHandler != NULL) &&
ExternalInterruptHandler[ExceptionType] != NULL) { (ExternalInterruptHandler[ExceptionType] != NULL))
(ExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext); {
(ExternalInterruptHandler[ExceptionType])(ExceptionType, SystemContext);
} else if (ExceptionType < CPU_EXCEPTION_NUM) { } else if (ExceptionType < CPU_EXCEPTION_NUM) {
// //
// Get Spinlock to display CPU information // Get Spinlock to display CPU information
@@ -114,6 +118,7 @@ CommonExceptionHandlerWorker (
while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) { while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) {
CpuPause (); CpuPause ();
} }
// //
// Initialize the serial port before dumping. // Initialize the serial port before dumping.
// //
@@ -151,10 +156,10 @@ UpdateIdtTable (
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
UINT16 CodeSegment; UINT16 CodeSegment;
UINTN Index; UINTN Index;
UINTN InterruptHandler; UINTN InterruptHandler;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
// //
@@ -162,47 +167,47 @@ UpdateIdtTable (
// //
CodeSegment = AsmReadCs (); CodeSegment = AsmReadCs ();
for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index ++) { for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index++) {
IdtTable[Index].Bits.Selector = CodeSegment; IdtTable[Index].Bits.Selector = CodeSegment;
// //
// Check reserved vectors attributes // Check reserved vectors attributes
// //
switch (ReservedVectors[Index].Attribute) { switch (ReservedVectors[Index].Attribute) {
case EFI_VECTOR_HANDOFF_DO_NOT_HOOK: case EFI_VECTOR_HANDOFF_DO_NOT_HOOK:
// //
// Keep original IDT entry // Keep original IDT entry
// //
continue; continue;
case EFI_VECTOR_HANDOFF_HOOK_AFTER: case EFI_VECTOR_HANDOFF_HOOK_AFTER:
InitializeSpinLock (&ReservedVectors[Index].SpinLock); InitializeSpinLock (&ReservedVectors[Index].SpinLock);
CopyMem ( CopyMem (
(VOID *) ReservedVectors[Index].HookAfterStubHeaderCode, (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode,
(VOID *) TemplateMap->HookAfterStubHeaderStart, (VOID *)TemplateMap->HookAfterStubHeaderStart,
TemplateMap->ExceptionStubHeaderSize TemplateMap->ExceptionStubHeaderSize
); );
AsmVectorNumFixup ( AsmVectorNumFixup (
(VOID *) ReservedVectors[Index].HookAfterStubHeaderCode, (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode,
(UINT8) Index, (UINT8)Index,
(VOID *) TemplateMap->HookAfterStubHeaderStart (VOID *)TemplateMap->HookAfterStubHeaderStart
); );
// //
// Go on the following code // Go on the following code
// //
case EFI_VECTOR_HANDOFF_HOOK_BEFORE: case EFI_VECTOR_HANDOFF_HOOK_BEFORE:
// //
// Save original IDT handler address // Save original IDT handler address
// //
ReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]); ReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]);
// //
// Go on the following code // Go on the following code
// //
default: default:
// //
// Update new IDT entry // Update new IDT entry
// //
InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize; InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize;
ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler); ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
break; break;
} }
} }
} }
@@ -221,19 +226,19 @@ UpdateIdtTable (
**/ **/
EFI_STATUS EFI_STATUS
InitializeCpuExceptionHandlersWorker ( InitializeCpuExceptionHandlersWorker (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
UINTN IdtEntryCount; UINTN IdtEntryCount;
EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
IA32_IDT_GATE_DESCRIPTOR *IdtTable; IA32_IDT_GATE_DESCRIPTOR *IdtTable;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff); SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
if (VectorInfo != NULL) { if (VectorInfo != NULL) {
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_EXCEPTION_NUM); Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_EXCEPTION_NUM);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@@ -253,7 +258,7 @@ InitializeCpuExceptionHandlersWorker (
IdtEntryCount = CPU_EXCEPTION_NUM; IdtEntryCount = CPU_EXCEPTION_NUM;
} }
IdtTable = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base; IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
AsmGetTemplateAddressMap (&TemplateMap); AsmGetTemplateAddressMap (&TemplateMap);
ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE); ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);
@@ -282,33 +287,33 @@ InitializeCpuExceptionHandlersWorker (
**/ **/
EFI_STATUS EFI_STATUS
RegisterCpuInterruptHandlerWorker ( RegisterCpuInterruptHandlerWorker (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
UINTN EnabledInterruptNum; UINTN EnabledInterruptNum;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler;
EnabledInterruptNum = ExceptionHandlerData->IdtEntryCount; EnabledInterruptNum = ExceptionHandlerData->IdtEntryCount;
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler; ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;
if (InterruptType < 0 || InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum || if ((InterruptType < 0) || (InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum) ||
ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) { (ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK))
{
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (InterruptHandler == NULL && ExternalInterruptHandler[InterruptType] == NULL) { if ((InterruptHandler == NULL) && (ExternalInterruptHandler[InterruptType] == NULL)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (InterruptHandler != NULL && ExternalInterruptHandler[InterruptType] != NULL) { if ((InterruptHandler != NULL) && (ExternalInterruptHandler[InterruptType] != NULL)) {
return EFI_ALREADY_STARTED; return EFI_ALREADY_STARTED;
} }
ExternalInterruptHandler[InterruptType] = InterruptHandler; ExternalInterruptHandler[InterruptType] = InterruptHandler;
return EFI_SUCCESS; return EFI_SUCCESS;
} }

44
UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
View File

@@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/VmgExitLib.h> #include <Library/VmgExitLib.h>
#include "CpuExceptionCommon.h" #include "CpuExceptionCommon.h"
CONST UINTN mDoFarReturnFlag = 0; CONST UINTN mDoFarReturnFlag = 0;
/** /**
Common exception handler. Common exception handler.
@@ -21,8 +21,8 @@ CONST UINTN mDoFarReturnFlag = 0;
VOID VOID
EFIAPI EFIAPI
CommonExceptionHandler ( CommonExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
if (ExceptionType == VC_EXCEPTION) { if (ExceptionType == VC_EXCEPTION) {
@@ -79,26 +79,27 @@ CommonExceptionHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlers ( InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
RESERVED_VECTORS_DATA ReservedVectorData[CPU_EXCEPTION_NUM]; RESERVED_VECTORS_DATA ReservedVectorData[CPU_EXCEPTION_NUM];
IA32_DESCRIPTOR IdtDescriptor; IA32_DESCRIPTOR IdtDescriptor;
UINTN IdtEntryCount; UINTN IdtEntryCount;
UINT16 CodeSegment; UINT16 CodeSegment;
EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
IA32_IDT_GATE_DESCRIPTOR *IdtTable; IA32_IDT_GATE_DESCRIPTOR *IdtTable;
UINTN Index; UINTN Index;
UINTN InterruptHandler; UINTN InterruptHandler;
if (VectorInfo != NULL) { if (VectorInfo != NULL) {
SetMem ((VOID *) ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff); SetMem ((VOID *)ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);
Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectorData, CPU_EXCEPTION_NUM); Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectorData, CPU_EXCEPTION_NUM);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
} }
// //
// Read IDT descriptor and calculate IDT size // Read IDT descriptor and calculate IDT size
// //
@@ -110,6 +111,7 @@ InitializeCpuExceptionHandlers (
// //
IdtEntryCount = CPU_EXCEPTION_NUM; IdtEntryCount = CPU_EXCEPTION_NUM;
} }
// //
// Use current CS as the segment selector of interrupt gate in IDT // Use current CS as the segment selector of interrupt gate in IDT
// //
@@ -117,7 +119,7 @@ InitializeCpuExceptionHandlers (
AsmGetTemplateAddressMap (&TemplateMap); AsmGetTemplateAddressMap (&TemplateMap);
IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base; IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;
for (Index = 0; Index < IdtEntryCount; Index ++) { for (Index = 0; Index < IdtEntryCount; Index++) {
IdtTable[Index].Bits.Selector = CodeSegment; IdtTable[Index].Bits.Selector = CodeSegment;
// //
// Check reserved vectors attributes if has, only EFI_VECTOR_HANDOFF_DO_NOT_HOOK // Check reserved vectors attributes if has, only EFI_VECTOR_HANDOFF_DO_NOT_HOOK
@@ -128,12 +130,14 @@ InitializeCpuExceptionHandlers (
continue; continue;
} }
} }
// //
// Update IDT entry // Update IDT entry
// //
InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize; InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;
ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler); ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -156,7 +160,7 @@ InitializeCpuExceptionHandlers (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuInterruptHandlers ( InitializeCpuInterruptHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@@ -188,8 +192,8 @@ InitializeCpuInterruptHandlers (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
RegisterCpuInterruptHandler ( RegisterCpuInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@@ -220,8 +224,8 @@ RegisterCpuInterruptHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlersEx ( InitializeCpuExceptionHandlersEx (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
) )
{ {
return InitializeCpuExceptionHandlers (VectorInfo); return InitializeCpuExceptionHandlers (VectorInfo);

27
UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
View File

@@ -9,16 +9,17 @@
#include <PiSmm.h> #include <PiSmm.h>
#include "CpuExceptionCommon.h" #include "CpuExceptionCommon.h"
CONST UINTN mDoFarReturnFlag = 1; CONST UINTN mDoFarReturnFlag = 1;
// //
// Spin lock for CPU information display // Spin lock for CPU information display
// //
SPIN_LOCK mDisplayMessageSpinLock; SPIN_LOCK mDisplayMessageSpinLock;
RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
EXCEPTION_HANDLER_DATA mExceptionHandlerData;
RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
EXCEPTION_HANDLER_DATA mExceptionHandlerData;
/** /**
Common exception handler. Common exception handler.
@@ -28,8 +29,8 @@ EXCEPTION_HANDLER_DATA mExceptionHandlerData;
VOID VOID
EFIAPI EFIAPI
CommonExceptionHandler ( CommonExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData); CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData);
@@ -54,7 +55,7 @@ CommonExceptionHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlers ( InitializeCpuExceptionHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
mExceptionHandlerData.ReservedVectors = mReservedVectorsData; mExceptionHandlerData.ReservedVectors = mReservedVectorsData;
@@ -82,7 +83,7 @@ InitializeCpuExceptionHandlers (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuInterruptHandlers ( InitializeCpuInterruptHandlers (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@@ -114,8 +115,8 @@ InitializeCpuInterruptHandlers (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
RegisterCpuInterruptHandler ( RegisterCpuInterruptHandler (
IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
) )
{ {
return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData); return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);
@@ -146,8 +147,8 @@ RegisterCpuInterruptHandler (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
InitializeCpuExceptionHandlersEx ( InitializeCpuExceptionHandlersEx (
IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
) )
{ {
return InitializeCpuExceptionHandlers (VectorInfo); return InitializeCpuExceptionHandlers (VectorInfo);

129
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
View File

@@ -17,8 +17,8 @@
**/ **/
VOID VOID
ArchUpdateIdtEntry ( ArchUpdateIdtEntry (
OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry, OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
IN UINTN InterruptHandler IN UINTN InterruptHandler
) )
{ {
IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler; IdtEntry->Bits.OffsetLow = (UINT16)(UINTN)InterruptHandler;
@@ -35,11 +35,11 @@ ArchUpdateIdtEntry (
**/ **/
UINTN UINTN
ArchGetIdtHandler ( ArchGetIdtHandler (
IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry
) )
{ {
return IdtEntry->Bits.OffsetLow + (((UINTN) IdtEntry->Bits.OffsetHigh) << 16) + return IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16) +
(((UINTN) IdtEntry->Bits.OffsetUpper) << 32); (((UINTN)IdtEntry->Bits.OffsetUpper) << 32);
} }
/** /**
@@ -51,13 +51,13 @@ ArchGetIdtHandler (
**/ **/
VOID VOID
ArchSaveExceptionContext ( ArchSaveExceptionContext (
IN UINTN ExceptionType, IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext, IN EFI_SYSTEM_CONTEXT SystemContext,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
IA32_EFLAGS32 Eflags; IA32_EFLAGS32 Eflags;
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
// //
@@ -74,13 +74,13 @@ ArchSaveExceptionContext (
// //
// Clear IF flag to avoid old IDT handler enable interrupt by IRET // Clear IF flag to avoid old IDT handler enable interrupt by IRET
// //
Eflags.UintN = SystemContext.SystemContextX64->Rflags; Eflags.UintN = SystemContext.SystemContextX64->Rflags;
Eflags.Bits.IF = 0; Eflags.Bits.IF = 0;
SystemContext.SystemContextX64->Rflags = Eflags.UintN; SystemContext.SystemContextX64->Rflags = Eflags.UintN;
// //
// Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin. // Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin.
// //
SystemContext.SystemContextX64->Rip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode; SystemContext.SystemContextX64->Rip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode;
} }
/** /**
@@ -92,14 +92,14 @@ ArchSaveExceptionContext (
**/ **/
VOID VOID
ArchRestoreExceptionContext ( ArchRestoreExceptionContext (
IN UINTN ExceptionType, IN UINTN ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext, IN EFI_SYSTEM_CONTEXT SystemContext,
IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData
) )
{ {
RESERVED_VECTORS_DATA *ReservedVectors; RESERVED_VECTORS_DATA *ReservedVectors;
ReservedVectors = ExceptionHandlerData->ReservedVectors; ReservedVectors = ExceptionHandlerData->ReservedVectors;
SystemContext.SystemContextX64->Ss = ReservedVectors[ExceptionType].OldSs; SystemContext.SystemContextX64->Ss = ReservedVectors[ExceptionType].OldSs;
SystemContext.SystemContextX64->Rsp = ReservedVectors[ExceptionType].OldSp; SystemContext.SystemContextX64->Rsp = ReservedVectors[ExceptionType].OldSp;
SystemContext.SystemContextX64->Rflags = ReservedVectors[ExceptionType].OldFlags; SystemContext.SystemContextX64->Rflags = ReservedVectors[ExceptionType].OldFlags;
@@ -121,31 +121,32 @@ ArchRestoreExceptionContext (
**/ **/
EFI_STATUS EFI_STATUS
ArchSetupExceptionStack ( ArchSetupExceptionStack (
IN CPU_EXCEPTION_INIT_DATA *StackSwitchData IN CPU_EXCEPTION_INIT_DATA *StackSwitchData
) )
{ {
IA32_DESCRIPTOR Gdtr; IA32_DESCRIPTOR Gdtr;
IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Idtr;
IA32_IDT_GATE_DESCRIPTOR *IdtTable; IA32_IDT_GATE_DESCRIPTOR *IdtTable;
IA32_TSS_DESCRIPTOR *TssDesc; IA32_TSS_DESCRIPTOR *TssDesc;
IA32_TASK_STATE_SEGMENT *Tss; IA32_TASK_STATE_SEGMENT *Tss;
UINTN StackTop; UINTN StackTop;
UINTN Index; UINTN Index;
UINTN Vector; UINTN Vector;
UINTN TssBase; UINTN TssBase;
UINTN GdtSize; UINTN GdtSize;
if (StackSwitchData == NULL || if ((StackSwitchData == NULL) ||
StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV || (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
StackSwitchData->X64.KnownGoodStackTop == 0 || (StackSwitchData->X64.KnownGoodStackTop == 0) ||
StackSwitchData->X64.KnownGoodStackSize == 0 || (StackSwitchData->X64.KnownGoodStackSize == 0) ||
StackSwitchData->X64.StackSwitchExceptions == NULL || (StackSwitchData->X64.StackSwitchExceptions == NULL) ||
StackSwitchData->X64.StackSwitchExceptionNumber == 0 || (StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||
StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM || (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
StackSwitchData->X64.GdtTable == NULL || (StackSwitchData->X64.GdtTable == NULL) ||
StackSwitchData->X64.IdtTable == NULL || (StackSwitchData->X64.IdtTable == NULL) ||
StackSwitchData->X64.ExceptionTssDesc == NULL || (StackSwitchData->X64.ExceptionTssDesc == NULL) ||
StackSwitchData->X64.ExceptionTss == NULL) { (StackSwitchData->X64.ExceptionTss == NULL))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -163,7 +164,8 @@ ArchSetupExceptionStack (
} }
if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) > if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >
((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) { ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))
{
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -173,6 +175,7 @@ ArchSetupExceptionStack (
if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) { if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) { if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@@ -196,13 +199,14 @@ ArchSetupExceptionStack (
(UINTN)(StackSwitchData->X64.GdtTable); (UINTN)(StackSwitchData->X64.GdtTable);
if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) { if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {
CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);
Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable; Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable;
Gdtr.Limit = (UINT16)GdtSize - 1; Gdtr.Limit = (UINT16)GdtSize - 1;
} }
if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) { if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {
Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable; Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;
} }
if (StackSwitchData->X64.IdtTableSize > 0) { if (StackSwitchData->X64.IdtTableSize > 0) {
Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1); Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);
} }
@@ -213,16 +217,16 @@ ArchSetupExceptionStack (
// //
TssBase = (UINTN)Tss; TssBase = (UINTN)Tss;
TssDesc->Uint128.Uint64 = 0; TssDesc->Uint128.Uint64 = 0;
TssDesc->Uint128.Uint64_1= 0; TssDesc->Uint128.Uint64_1 = 0;
TssDesc->Bits.LimitLow = sizeof(IA32_TASK_STATE_SEGMENT) - 1; TssDesc->Bits.LimitLow = sizeof (IA32_TASK_STATE_SEGMENT) - 1;
TssDesc->Bits.BaseLow = (UINT16)TssBase; TssDesc->Bits.BaseLow = (UINT16)TssBase;
TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16); TssDesc->Bits.BaseMidl = (UINT8)(TssBase >> 16);
TssDesc->Bits.Type = IA32_GDT_TYPE_TSS; TssDesc->Bits.Type = IA32_GDT_TYPE_TSS;
TssDesc->Bits.P = 1; TssDesc->Bits.P = 1;
TssDesc->Bits.LimitHigh = 0; TssDesc->Bits.LimitHigh = 0;
TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24); TssDesc->Bits.BaseMidh = (UINT8)(TssBase >> 24);
TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32); TssDesc->Bits.BaseHigh = (UINT32)(TssBase >> 32);
// //
// Fixup exception task descriptor and task-state segment // Fixup exception task descriptor and task-state segment
@@ -236,16 +240,18 @@ ArchSetupExceptionStack (
// Fixup IST // Fixup IST
// //
Tss->IST[Index] = StackTop; Tss->IST[Index] = StackTop;
StackTop -= StackSwitchData->X64.KnownGoodStackSize; StackTop -= StackSwitchData->X64.KnownGoodStackSize;
// //
// Set the IST field to enable corresponding IST // Set the IST field to enable corresponding IST
// //
Vector = StackSwitchData->X64.StackSwitchExceptions[Index]; Vector = StackSwitchData->X64.StackSwitchExceptions[Index];
if (Vector >= CPU_EXCEPTION_NUM || if ((Vector >= CPU_EXCEPTION_NUM) ||
Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) { (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
{
continue; continue;
} }
IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1); IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);
} }
@@ -276,8 +282,8 @@ ArchSetupExceptionStack (
VOID VOID
EFIAPI EFIAPI
DumpCpuContext ( DumpCpuContext (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
InternalPrintMessage ( InternalPrintMessage (
@@ -304,8 +310,10 @@ DumpCpuContext (
(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0 (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0
); );
} }
InternalPrintMessage ("\n"); InternalPrintMessage ("\n");
} }
InternalPrintMessage ( InternalPrintMessage (
"RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n", "RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n",
SystemContext.SystemContextX64->Rip, SystemContext.SystemContextX64->Rip,
@@ -406,8 +414,8 @@ DumpCpuContext (
**/ **/
VOID VOID
DumpImageAndCpuContent ( DumpImageAndCpuContent (
IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_SYSTEM_CONTEXT SystemContext IN EFI_SYSTEM_CONTEXT SystemContext
) )
{ {
DumpCpuContext (ExceptionType, SystemContext); DumpCpuContext (ExceptionType, SystemContext);
@@ -415,7 +423,8 @@ DumpImageAndCpuContent (
// Dump module image base and module entry point by RIP // Dump module image base and module entry point by RIP
// //
if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) && if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&
((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0)) { ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0))
{
// //
// The RIP in SystemContext could not be used // The RIP in SystemContext could not be used
// if it is page fault with I/D set. // if it is page fault with I/D set.

32
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
View File

@@ -10,9 +10,9 @@
#define _ARCH_CPU_INTERRUPT_DEFS_H_ #define _ARCH_CPU_INTERRUPT_DEFS_H_
typedef struct { typedef struct {
EFI_SYSTEM_CONTEXT_X64 SystemContext; EFI_SYSTEM_CONTEXT_X64 SystemContext;
BOOLEAN ExceptionDataFlag; BOOLEAN ExceptionDataFlag;
UINTN OldIdtHandler; UINTN OldIdtHandler;
} EXCEPTION_HANDLER_CONTEXT; } EXCEPTION_HANDLER_CONTEXT;
// //
@@ -24,20 +24,20 @@ typedef struct {
} CPU_STATUS_CODE_TEMPLATE; } CPU_STATUS_CODE_TEMPLATE;
typedef struct { typedef struct {
SPIN_LOCK SpinLock; SPIN_LOCK SpinLock;
UINT32 ApicId; UINT32 ApicId;
UINT32 Attribute; UINT32 Attribute;
UINTN ExceptonHandler; UINTN ExceptonHandler;
UINTN OldSs; UINTN OldSs;
UINTN OldSp; UINTN OldSp;
UINTN OldFlags; UINTN OldFlags;
UINTN OldCs; UINTN OldCs;
UINTN OldIp; UINTN OldIp;
UINTN ExceptionData; UINTN ExceptionData;
UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE]; UINT8 HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];
} RESERVED_VECTORS_DATA; } RESERVED_VECTORS_DATA;
#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR) #define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)
#define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT) #define CPU_TSS_SIZE sizeof (IA32_TASK_STATE_SEGMENT)
#endif #endif

1
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
View File

@@ -38,4 +38,3 @@ InternalGetPerformanceCounterFrequency (
{ {
return CpuidCoreClockCalculateTscFrequency (); return CpuidCoreClockCalculateTscFrequency ();
} }

42
UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
View File

@@ -13,7 +13,9 @@
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Register/Cpuid.h> #include <Register/Cpuid.h>
GUID mCpuCrystalFrequencyHobGuid = { 0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a } }; GUID mCpuCrystalFrequencyHobGuid = {
0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a }
};
/** /**
Internal function to retrieves the 64-bit frequency in Hz. Internal function to retrieves the 64-bit frequency in Hz.
@@ -41,11 +43,11 @@ CpuidCoreClockCalculateTscFrequency (
VOID VOID
) )
{ {
UINT64 TscFrequency; UINT64 TscFrequency;
UINT64 CoreXtalFrequency; UINT64 CoreXtalFrequency;
UINT32 RegEax; UINT32 RegEax;
UINT32 RegEbx; UINT32 RegEbx;
UINT32 RegEcx; UINT32 RegEcx;
// //
// Use CPUID leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Information // Use CPUID leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Information
@@ -57,11 +59,12 @@ CpuidCoreClockCalculateTscFrequency (
// //
// If EAX or EBX returns 0, the XTAL ratio is not enumerated. // If EAX or EBX returns 0, the XTAL ratio is not enumerated.
// //
if (RegEax == 0 || RegEbx ==0 ) { if ((RegEax == 0) || (RegEbx == 0)) {
ASSERT (RegEax != 0); ASSERT (RegEax != 0);
ASSERT (RegEbx != 0); ASSERT (RegEbx != 0);
return 0; return 0;
} }
// //
// If ECX returns 0, the XTAL frequency is not enumerated. // If ECX returns 0, the XTAL frequency is not enumerated.
// And PcdCpuCoreCrystalClockFrequency defined should base on processor series. // And PcdCpuCoreCrystalClockFrequency defined should base on processor series.
@@ -69,7 +72,7 @@ CpuidCoreClockCalculateTscFrequency (
if (RegEcx == 0) { if (RegEcx == 0) {
CoreXtalFrequency = PcdGet64 (PcdCpuCoreCrystalClockFrequency); CoreXtalFrequency = PcdGet64 (PcdCpuCoreCrystalClockFrequency);
} else { } else {
CoreXtalFrequency = (UINT64) RegEcx; CoreXtalFrequency = (UINT64)RegEcx;
} }
// //
@@ -99,7 +102,7 @@ InternalCpuDelay (
// //
// The target timer count is calculated here // The target timer count is calculated here
// //
Ticks = AsmReadTsc() + Delay; Ticks = AsmReadTsc () + Delay;
// //
// Wait until time out // Wait until time out
@@ -107,8 +110,8 @@ InternalCpuDelay (
// Thus, this function must be called within 10 years of reset since // Thus, this function must be called within 10 years of reset since
// Intel guarantees a minimum of 10 years before the TSC wraps. // Intel guarantees a minimum of 10 years before the TSC wraps.
// //
while (AsmReadTsc() <= Ticks) { while (AsmReadTsc () <= Ticks) {
CpuPause(); CpuPause ();
} }
} }
@@ -128,7 +131,6 @@ MicroSecondDelay (
IN UINTN MicroSeconds IN UINTN MicroSeconds
) )
{ {
InternalCpuDelay ( InternalCpuDelay (
DivU64x32 ( DivU64x32 (
MultU64x64 ( MultU64x64 (
@@ -136,8 +138,8 @@ MicroSecondDelay (
InternalGetPerformanceCounterFrequency () InternalGetPerformanceCounterFrequency ()
), ),
1000000u 1000000u
) )
); );
return MicroSeconds; return MicroSeconds;
} }
@@ -158,7 +160,6 @@ NanoSecondDelay (
IN UINTN NanoSeconds IN UINTN NanoSeconds
) )
{ {
InternalCpuDelay ( InternalCpuDelay (
DivU64x32 ( DivU64x32 (
MultU64x64 ( MultU64x64 (
@@ -166,8 +167,8 @@ NanoSecondDelay (
InternalGetPerformanceCounterFrequency () InternalGetPerformanceCounterFrequency ()
), ),
1000000000u 1000000000u
) )
); );
return NanoSeconds; return NanoSeconds;
} }
@@ -230,6 +231,7 @@ GetPerformanceCounterProperties (
if (EndValue != NULL) { if (EndValue != NULL) {
*EndValue = 0xffffffffffffffffULL; *EndValue = 0xffffffffffffffffULL;
} }
return InternalGetPerformanceCounterFrequency (); return InternalGetPerformanceCounterFrequency ();
} }
@@ -269,9 +271,9 @@ GetTimeInNanoSecond (
// Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34, // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
// i.e. highest bit set in Remainder should <= 33. // i.e. highest bit set in Remainder should <= 33.
// //
Shift = MAX (0, HighBitSet64 (Remainder) - 33); Shift = MAX (0, HighBitSet64 (Remainder) - 33);
Remainder = RShiftU64 (Remainder, (UINTN) Shift); Remainder = RShiftU64 (Remainder, (UINTN)Shift);
Frequency = RShiftU64 (Frequency, (UINTN) Shift); Frequency = RShiftU64 (Frequency, (UINTN)Shift);
NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL); NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
return NanoSeconds; return NanoSeconds;

91
UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c
View File

@@ -25,7 +25,7 @@ GetProcessorMicrocodeSignature (
VOID VOID
) )
{ {
MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr; MSR_IA32_BIOS_SIGN_ID_REGISTER BiosSignIdMsr;
AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0); AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0);
AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL); AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL);
@@ -44,12 +44,12 @@ GetProcessorMicrocodeCpuId (
EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId
) )
{ {
MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr; MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;
ASSERT (MicrocodeCpuId != NULL); ASSERT (MicrocodeCpuId != NULL);
PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID); PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
MicrocodeCpuId->PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId; MicrocodeCpuId->PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId;
AsmCpuid (CPUID_VERSION_INFO, &MicrocodeCpuId->ProcessorSignature, NULL, NULL, NULL); AsmCpuid (CPUID_VERSION_INFO, &MicrocodeCpuId->ProcessorSignature, NULL, NULL, NULL);
} }
@@ -71,10 +71,10 @@ GetProcessorMicrocodeCpuId (
UINT32 UINT32
EFIAPI EFIAPI
GetMicrocodeLength ( GetMicrocodeLength (
IN CPU_MICROCODE_HEADER *Microcode IN CPU_MICROCODE_HEADER *Microcode
) )
{ {
UINT32 TotalSize; UINT32 TotalSize;
ASSERT (Microcode != NULL); ASSERT (Microcode != NULL);
@@ -82,6 +82,7 @@ GetMicrocodeLength (
if (Microcode->DataSize != 0) { if (Microcode->DataSize != 0) {
TotalSize = Microcode->TotalSize; TotalSize = Microcode->TotalSize;
} }
return TotalSize; return TotalSize;
} }
@@ -95,12 +96,12 @@ GetMicrocodeLength (
VOID VOID
EFIAPI EFIAPI
LoadMicrocode ( LoadMicrocode (
IN CPU_MICROCODE_HEADER *Microcode IN CPU_MICROCODE_HEADER *Microcode
) )
{ {
ASSERT (Microcode != NULL); ASSERT (Microcode != NULL);
AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64) (UINTN) (Microcode + 1)); AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64)(UINTN)(Microcode + 1));
} }
/** /**
@@ -119,13 +120,13 @@ LoadMicrocode (
**/ **/
BOOLEAN BOOLEAN
IsProcessorMatchedMicrocode ( IsProcessorMatchedMicrocode (
IN UINT32 ProcessorSignature, IN UINT32 ProcessorSignature,
IN UINT32 ProcessorFlags, IN UINT32 ProcessorFlags,
IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId,
IN UINTN MicrocodeCpuIdCount IN UINTN MicrocodeCpuIdCount
) )
{ {
UINTN Index; UINTN Index;
if (MicrocodeCpuIdCount == 0) { if (MicrocodeCpuIdCount == 0) {
return TRUE; return TRUE;
@@ -133,7 +134,8 @@ IsProcessorMatchedMicrocode (
for (Index = 0; Index < MicrocodeCpuIdCount; Index++) { for (Index = 0; Index < MicrocodeCpuIdCount; Index++) {
if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) && if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) &&
(ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0) { ((ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0))
{
return TRUE; return TRUE;
} }
} }
@@ -182,22 +184,22 @@ IsProcessorMatchedMicrocode (
BOOLEAN BOOLEAN
EFIAPI EFIAPI
IsValidMicrocode ( IsValidMicrocode (
IN CPU_MICROCODE_HEADER *Microcode, IN CPU_MICROCODE_HEADER *Microcode,
IN UINTN MicrocodeLength, IN UINTN MicrocodeLength,
IN UINT32 MinimumRevision, IN UINT32 MinimumRevision,
IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds, IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds,
IN UINTN MicrocodeCpuIdCount, IN UINTN MicrocodeCpuIdCount,
IN BOOLEAN VerifyChecksum IN BOOLEAN VerifyChecksum
) )
{ {
UINTN Index; UINTN Index;
UINT32 DataSize; UINT32 DataSize;
UINT32 TotalSize; UINT32 TotalSize;
CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;
CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;
UINT32 ExtendedTableLength; UINT32 ExtendedTableLength;
UINT32 Sum32; UINT32 Sum32;
BOOLEAN Match; BOOLEAN Match;
ASSERT (Microcode != NULL); ASSERT (Microcode != NULL);
@@ -206,7 +208,7 @@ IsValidMicrocode (
// the input microcode buffer is so small that even cannot contain the header. // the input microcode buffer is so small that even cannot contain the header.
// the input microcode buffer is so large that exceeds MAX_ADDRESS. // the input microcode buffer is so large that exceeds MAX_ADDRESS.
// //
if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN) Microcode))) { if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN)Microcode))) {
return FALSE; return FALSE;
} }
@@ -249,7 +251,7 @@ IsValidMicrocode (
// //
// The summation of all DWORDs in microcode should be zero. // The summation of all DWORDs in microcode should be zero.
// //
if (VerifyChecksum && (CalculateSum32 ((UINT32 *) Microcode, TotalSize) != 0)) { if (VerifyChecksum && (CalculateSum32 ((UINT32 *)Microcode, TotalSize) != 0)) {
return FALSE; return FALSE;
} }
@@ -272,29 +274,34 @@ IsValidMicrocode (
if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) || ((ExtendedTableLength % 4) != 0)) { if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) || ((ExtendedTableLength % 4) != 0)) {
return FALSE; return FALSE;
} }
// //
// Extended Table exist, check if the CPU in support list // Extended Table exist, check if the CPU in support list
// //
ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINTN) (Microcode + 1) + DataSize); ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *)((UINTN)(Microcode + 1) + DataSize);
if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (CPU_MICROCODE_EXTENDED_TABLE)) { if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (CPU_MICROCODE_EXTENDED_TABLE)) {
return FALSE; return FALSE;
} }
if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_EXTENDED_TABLE) if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_EXTENDED_TABLE)
> ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) { > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER))
return FALSE; {
}
//
// Check the extended table checksum
//
if (VerifyChecksum && (CalculateSum32 ((UINT32 *) ExtendedTableHeader, ExtendedTableLength) != 0)) {
return FALSE; return FALSE;
} }
ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1); //
for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index ++) { // Check the extended table checksum
//
if (VerifyChecksum && (CalculateSum32 ((UINT32 *)ExtendedTableHeader, ExtendedTableLength) != 0)) {
return FALSE;
}
ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *)(ExtendedTableHeader + 1);
for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index++) {
if (VerifyChecksum && if (VerifyChecksum &&
(ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[Index].ProcessorFlag (ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[Index].ProcessorFlag
+ ExtendedTable[Index].Checksum != Sum32)) { + ExtendedTable[Index].Checksum != Sum32))
{
// //
// The extended table entry is valid when the summation of Processor Signature, Processor Flags // The extended table entry is valid when the summation of Processor Signature, Processor Flags
// and Checksum equal to the coresponding summation from primary header. Because: // and Checksum equal to the coresponding summation from primary header. Because:
@@ -308,6 +315,7 @@ IsValidMicrocode (
// //
continue; continue;
} }
Match = IsProcessorMatchedMicrocode ( Match = IsProcessorMatchedMicrocode (
ExtendedTable[Index].ProcessorSignature.Uint32, ExtendedTable[Index].ProcessorSignature.Uint32,
ExtendedTable[Index].ProcessorFlag, ExtendedTable[Index].ProcessorFlag,
@@ -318,5 +326,6 @@ IsValidMicrocode (
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }

246
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
View File

@@ -18,21 +18,21 @@
#include <Protocol/Timer.h> #include <Protocol/Timer.h>
#define AP_SAFE_STACK_SIZE 128 #define AP_SAFE_STACK_SIZE 128
CPU_MP_DATA *mCpuMpData = NULL; CPU_MP_DATA *mCpuMpData = NULL;
EFI_EVENT mCheckAllApsEvent = NULL; EFI_EVENT mCheckAllApsEvent = NULL;
EFI_EVENT mMpInitExitBootServicesEvent = NULL; EFI_EVENT mMpInitExitBootServicesEvent = NULL;
EFI_EVENT mLegacyBootEvent = NULL; EFI_EVENT mLegacyBootEvent = NULL;
volatile BOOLEAN mStopCheckAllApsStatus = TRUE; volatile BOOLEAN mStopCheckAllApsStatus = TRUE;
VOID *mReservedApLoopFunc = NULL; VOID *mReservedApLoopFunc = NULL;
UINTN mReservedTopOfApStack; UINTN mReservedTopOfApStack;
volatile UINT32 mNumberToFinish = 0; volatile UINT32 mNumberToFinish = 0;
// //
// Begin wakeup buffer allocation below 0x88000 // Begin wakeup buffer allocation below 0x88000
// //
STATIC EFI_PHYSICAL_ADDRESS mSevEsDxeWakeupBuffer = 0x88000; STATIC EFI_PHYSICAL_ADDRESS mSevEsDxeWakeupBuffer = 0x88000;
/** /**
Enable Debug Agent to support source debugging on AP function. Enable Debug Agent to support source debugging on AP function.
@@ -70,7 +70,7 @@ GetCpuMpData (
**/ **/
VOID VOID
SaveCpuMpData ( SaveCpuMpData (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
) )
{ {
mCpuMpData = CpuMpData; mCpuMpData = CpuMpData;
@@ -86,12 +86,12 @@ SaveCpuMpData (
**/ **/
UINTN UINTN
GetWakeupBuffer ( GetWakeupBuffer (
IN UINTN WakeupBufferSize IN UINTN WakeupBufferSize
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS StartAddress; EFI_PHYSICAL_ADDRESS StartAddress;
EFI_MEMORY_TYPE MemoryType; EFI_MEMORY_TYPE MemoryType;
if (PcdGetBool (PcdSevEsIsEnabled)) { if (PcdGetBool (PcdSevEsIsEnabled)) {
MemoryType = EfiReservedMemoryType; MemoryType = EfiReservedMemoryType;
@@ -115,6 +115,7 @@ GetWakeupBuffer (
} else { } else {
StartAddress = 0x88000; StartAddress = 0x88000;
} }
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
MemoryType, MemoryType,
@@ -123,7 +124,7 @@ GetWakeupBuffer (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
StartAddress = (EFI_PHYSICAL_ADDRESS) -1; StartAddress = (EFI_PHYSICAL_ADDRESS)-1;
} else if (PcdGetBool (PcdSevEsIsEnabled)) { } else if (PcdGetBool (PcdSevEsIsEnabled)) {
// //
// Next SEV-ES wakeup buffer allocation must be below this allocation // Next SEV-ES wakeup buffer allocation must be below this allocation
@@ -131,10 +132,14 @@ GetWakeupBuffer (
mSevEsDxeWakeupBuffer = StartAddress; mSevEsDxeWakeupBuffer = StartAddress;
} }
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n", DEBUG ((
(UINTN) StartAddress, WakeupBufferSize)); DEBUG_INFO,
"WakeupBufferStart = %x, WakeupBufferSize = %x\n",
(UINTN)StartAddress,
WakeupBufferSize
));
return (UINTN) StartAddress; return (UINTN)StartAddress;
} }
/** /**
@@ -151,19 +156,19 @@ GetWakeupBuffer (
**/ **/
UINTN UINTN
GetModeTransitionBuffer ( GetModeTransitionBuffer (
IN UINTN BufferSize IN UINTN BufferSize
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS StartAddress; EFI_PHYSICAL_ADDRESS StartAddress;
StartAddress = BASE_4GB - 1; StartAddress = BASE_4GB - 1;
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
EfiBootServicesCode, EfiBootServicesCode,
EFI_SIZE_TO_PAGES (BufferSize), EFI_SIZE_TO_PAGES (BufferSize),
&StartAddress &StartAddress
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
StartAddress = 0; StartAddress = 0;
} }
@@ -194,27 +199,27 @@ GetSevEsAPMemory (
// Allocate 1 page for AP jump table page // Allocate 1 page for AP jump table page
// //
StartAddress = BASE_4GB - 1; StartAddress = BASE_4GB - 1;
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
EfiReservedMemoryType, EfiReservedMemoryType,
1, 1,
&StartAddress &StartAddress
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN) StartAddress)); DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN)StartAddress));
// //
// Save the SevEsAPMemory as the AP jump table. // Save the SevEsAPMemory as the AP jump table.
// //
Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB); Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);
Ghcb = Msr.Ghcb; Ghcb = Msr.Ghcb;
VmgInit (Ghcb, &InterruptState); VmgInit (Ghcb, &InterruptState);
VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64) (UINTN) StartAddress); VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64)(UINTN)StartAddress);
VmgDone (Ghcb, InterruptState); VmgDone (Ghcb, InterruptState);
return (UINTN) StartAddress; return (UINTN)StartAddress;
} }
/** /**
@@ -226,9 +231,9 @@ CheckAndUpdateApsStatus (
VOID VOID
) )
{ {
UINTN ProcessorNumber; UINTN ProcessorNumber;
EFI_STATUS Status; EFI_STATUS Status;
CPU_MP_DATA *CpuMpData; CPU_MP_DATA *CpuMpData;
CpuMpData = GetCpuMpData (); CpuMpData = GetCpuMpData ();
@@ -236,13 +241,12 @@ CheckAndUpdateApsStatus (
// First, check whether pending StartupAllAPs() exists. // First, check whether pending StartupAllAPs() exists.
// //
if (CpuMpData->WaitEvent != NULL) { if (CpuMpData->WaitEvent != NULL) {
Status = CheckAllAPs (); Status = CheckAllAPs ();
// //
// If all APs finish for StartupAllAPs(), signal the WaitEvent for it. // If all APs finish for StartupAllAPs(), signal the WaitEvent for it.
// //
if (Status != EFI_NOT_READY) { if (Status != EFI_NOT_READY) {
Status = gBS->SignalEvent (CpuMpData->WaitEvent); Status = gBS->SignalEvent (CpuMpData->WaitEvent);
CpuMpData->WaitEvent = NULL; CpuMpData->WaitEvent = NULL;
} }
} }
@@ -251,7 +255,6 @@ CheckAndUpdateApsStatus (
// Second, check whether pending StartupThisAPs() callings exist. // Second, check whether pending StartupThisAPs() callings exist.
// //
for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) { for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {
if (CpuMpData->CpuData[ProcessorNumber].WaitEvent == NULL) { if (CpuMpData->CpuData[ProcessorNumber].WaitEvent == NULL) {
continue; continue;
} }
@@ -260,7 +263,7 @@ CheckAndUpdateApsStatus (
if (Status != EFI_NOT_READY) { if (Status != EFI_NOT_READY) {
gBS->SignalEvent (CpuMpData->CpuData[ProcessorNumber].WaitEvent); gBS->SignalEvent (CpuMpData->CpuData[ProcessorNumber].WaitEvent);
CpuMpData->CpuData[ProcessorNumber].WaitEvent = NULL; CpuMpData->CpuData[ProcessorNumber].WaitEvent = NULL;
} }
} }
} }
@@ -279,8 +282,8 @@ CheckAndUpdateApsStatus (
VOID VOID
EFIAPI EFIAPI
CheckApsStatus ( CheckApsStatus (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
// //
@@ -307,18 +310,20 @@ GetProtectedMode16CS (
UINTN GdtEntryCount; UINTN GdtEntryCount;
UINT16 Index; UINT16 Index;
Index = (UINT16) -1; Index = (UINT16)-1;
AsmReadGdtr (&GdtrDesc); AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) { for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) { if (GdtEntry->Bits.L == 0) {
if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 0) { if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 0)) {
break; break;
} }
} }
GdtEntry++; GdtEntry++;
} }
ASSERT (Index != GdtEntryCount); ASSERT (Index != GdtEntryCount);
return Index * 8; return Index * 8;
} }
@@ -340,15 +345,17 @@ GetProtectedModeCS (
AsmReadGdtr (&GdtrDesc); AsmReadGdtr (&GdtrDesc);
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR); GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) { for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) { if (GdtEntry->Bits.L == 0) {
if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) { if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {
break; break;
} }
} }
GdtEntry++; GdtEntry++;
} }
ASSERT (Index != GdtEntryCount); ASSERT (Index != GdtEntryCount);
return Index * 8; return Index * 8;
} }
@@ -364,11 +371,11 @@ RelocateApLoop (
IN OUT VOID *Buffer IN OUT VOID *Buffer
) )
{ {
CPU_MP_DATA *CpuMpData; CPU_MP_DATA *CpuMpData;
BOOLEAN MwaitSupport; BOOLEAN MwaitSupport;
ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc;
UINTN ProcessorNumber; UINTN ProcessorNumber;
UINTN StackStart; UINTN StackStart;
MpInitLibWhoAmI (&ProcessorNumber); MpInitLibWhoAmI (&ProcessorNumber);
CpuMpData = GetCpuMpData (); CpuMpData = GetCpuMpData ();
@@ -378,13 +385,14 @@ RelocateApLoop (
} else { } else {
StackStart = mReservedTopOfApStack; StackStart = mReservedTopOfApStack;
} }
AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoopFunc;
AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFunc;
AsmRelocateApLoopFunc ( AsmRelocateApLoopFunc (
MwaitSupport, MwaitSupport,
CpuMpData->ApTargetCState, CpuMpData->ApTargetCState,
CpuMpData->PmCodeSegment, CpuMpData->PmCodeSegment,
StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE,
(UINTN) &mNumberToFinish, (UINTN)&mNumberToFinish,
CpuMpData->Pm16CodeSegment, CpuMpData->Pm16CodeSegment,
CpuMpData->SevEsAPBuffer, CpuMpData->SevEsAPBuffer,
CpuMpData->WakeupBuffer CpuMpData->WakeupBuffer
@@ -406,32 +414,32 @@ RelocateApLoop (
VOID VOID
EFIAPI EFIAPI
MpInitChangeApLoopCallback ( MpInitChangeApLoopCallback (
IN EFI_EVENT Event, IN EFI_EVENT Event,
IN VOID *Context IN VOID *Context
) )
{ {
CPU_MP_DATA *CpuMpData; CPU_MP_DATA *CpuMpData;
CpuMpData = GetCpuMpData (); CpuMpData = GetCpuMpData ();
CpuMpData->PmCodeSegment = GetProtectedModeCS (); CpuMpData->PmCodeSegment = GetProtectedModeCS ();
CpuMpData->Pm16CodeSegment = GetProtectedMode16CS (); CpuMpData->Pm16CodeSegment = GetProtectedMode16CS ();
CpuMpData->ApLoopMode = PcdGet8 (PcdCpuApLoopMode); CpuMpData->ApLoopMode = PcdGet8 (PcdCpuApLoopMode);
mNumberToFinish = CpuMpData->CpuCount - 1; mNumberToFinish = CpuMpData->CpuCount - 1;
WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE); WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE);
while (mNumberToFinish > 0) { while (mNumberToFinish > 0) {
CpuPause (); CpuPause ();
} }
if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN) -1)) { if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN)-1)) {
// //
// There are APs present. Re-use reserved memory area below 1MB from // There are APs present. Re-use reserved memory area below 1MB from
// WakeupBuffer as the area to be used for transitioning to 16-bit mode // WakeupBuffer as the area to be used for transitioning to 16-bit mode
// in support of booting of the AP by an OS. // in support of booting of the AP by an OS.
// //
CopyMem ( CopyMem (
(VOID *) CpuMpData->WakeupBuffer, (VOID *)CpuMpData->WakeupBuffer,
(VOID *) (CpuMpData->AddressMap.RendezvousFunnelAddress + (VOID *)(CpuMpData->AddressMap.RendezvousFunnelAddress +
CpuMpData->AddressMap.SwitchToRealPM16ModeOffset), CpuMpData->AddressMap.SwitchToRealPM16ModeOffset),
CpuMpData->AddressMap.SwitchToRealPM16ModeSize CpuMpData->AddressMap.SwitchToRealPM16ModeSize
); );
} }
@@ -446,16 +454,16 @@ MpInitChangeApLoopCallback (
**/ **/
VOID VOID
InitMpGlobalData ( InitMpGlobalData (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_PHYSICAL_ADDRESS Address; EFI_PHYSICAL_ADDRESS Address;
UINTN ApSafeBufferSize; UINTN ApSafeBufferSize;
UINTN Index; UINTN Index;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc; EFI_GCD_MEMORY_SPACE_DESCRIPTOR MemDesc;
UINTN StackBase; UINTN StackBase;
CPU_INFO_IN_HOB *CpuInfoInHob; CPU_INFO_IN_HOB *CpuInfoInHob;
SaveCpuMpData (CpuMpData); SaveCpuMpData (CpuMpData);
@@ -485,7 +493,7 @@ InitMpGlobalData (
// //
CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob; CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; ++Index) { for (Index = 0; Index < CpuMpData->CpuCount; ++Index) {
if (CpuInfoInHob != NULL && CpuInfoInHob[Index].ApTopOfStack != 0) { if ((CpuInfoInHob != NULL) && (CpuInfoInHob[Index].ApTopOfStack != 0)) {
StackBase = (UINTN)CpuInfoInHob[Index].ApTopOfStack - CpuMpData->CpuApStackSize; StackBase = (UINTN)CpuInfoInHob[Index].ApTopOfStack - CpuMpData->CpuApStackSize;
} else { } else {
StackBase = CpuMpData->Buffer + Index * CpuMpData->CpuApStackSize; StackBase = CpuMpData->Buffer + Index * CpuMpData->CpuApStackSize;
@@ -501,8 +509,12 @@ InitMpGlobalData (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n", DEBUG ((
(UINT64)StackBase, (UINT64)Index)); DEBUG_INFO,
"Stack Guard set at %lx [cpu%lu]!\n",
(UINT64)StackBase,
(UINT64)Index
));
} }
} }
@@ -514,9 +526,11 @@ InitMpGlobalData (
// Allocating it in advance since memory services are not available in // Allocating it in advance since memory services are not available in
// Exit Boot Services callback function. // Exit Boot Services callback function.
// //
ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES ( ApSafeBufferSize = EFI_PAGES_TO_SIZE (
CpuMpData->AddressMap.RelocateApLoopFuncSize EFI_SIZE_TO_PAGES (
)); CpuMpData->AddressMap.RelocateApLoopFuncSize
)
);
Address = BASE_4GB - 1; Address = BASE_4GB - 1;
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
@@ -526,7 +540,7 @@ InitMpGlobalData (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
mReservedApLoopFunc = (VOID *) (UINTN) Address; mReservedApLoopFunc = (VOID *)(UINTN)Address;
ASSERT (mReservedApLoopFunc != NULL); ASSERT (mReservedApLoopFunc != NULL);
// //
@@ -545,9 +559,11 @@ InitMpGlobalData (
); );
} }
ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES ( ApSafeBufferSize = EFI_PAGES_TO_SIZE (
CpuMpData->CpuCount * AP_SAFE_STACK_SIZE EFI_SIZE_TO_PAGES (
)); CpuMpData->CpuCount * AP_SAFE_STACK_SIZE
)
);
Address = BASE_4GB - 1; Address = BASE_4GB - 1;
Status = gBS->AllocatePages ( Status = gBS->AllocatePages (
AllocateMaxAddress, AllocateMaxAddress,
@@ -557,7 +573,7 @@ InitMpGlobalData (
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
mReservedTopOfApStack = (UINTN) Address + ApSafeBufferSize; mReservedTopOfApStack = (UINTN)Address + ApSafeBufferSize;
ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) == 0); ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) == 0);
CopyMem ( CopyMem (
mReservedApLoopFunc, mReservedApLoopFunc,
@@ -684,15 +700,15 @@ InitMpGlobalData (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupAllAPs ( MpInitLibStartupAllAPs (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT UINTN **FailedCpuList OPTIONAL OUT UINTN **FailedCpuList OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
// //
// Temporarily stop checkAllApsStatus for avoid resource dead-lock. // Temporarily stop checkAllApsStatus for avoid resource dead-lock.
@@ -791,15 +807,15 @@ MpInitLibStartupAllAPs (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupThisAP ( MpInitLibStartupThisAP (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT BOOLEAN *Finished OPTIONAL OUT BOOLEAN *Finished OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
// //
// temporarily stop checkAllApsStatus for avoid resource dead-lock. // temporarily stop checkAllApsStatus for avoid resource dead-lock.
@@ -849,19 +865,19 @@ MpInitLibStartupThisAP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibSwitchBSP ( MpInitLibSwitchBSP (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableOldBSP IN BOOLEAN EnableOldBSP
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_TIMER_ARCH_PROTOCOL *Timer; EFI_TIMER_ARCH_PROTOCOL *Timer;
UINT64 TimerPeriod; UINT64 TimerPeriod;
TimerPeriod = 0; TimerPeriod = 0;
// //
// Locate Timer Arch Protocol // Locate Timer Arch Protocol
// //
Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **) &Timer); Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **)&Timer);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
Timer = NULL; Timer = NULL;
} }
@@ -922,13 +938,13 @@ MpInitLibSwitchBSP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibEnableDisableAP ( MpInitLibEnableDisableAP (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL IN UINT32 *HealthFlag OPTIONAL
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
BOOLEAN TempStopCheckState; BOOLEAN TempStopCheckState;
TempStopCheckState = FALSE; TempStopCheckState = FALSE;
// //
@@ -961,7 +977,7 @@ MpInitLibEnableDisableAP (
**/ **/
EFI_STATUS EFI_STATUS
PlatformShadowMicrocode ( PlatformShadowMicrocode (
IN OUT CPU_MP_DATA *CpuMpData IN OUT CPU_MP_DATA *CpuMpData
) )
{ {
// //

134
UefiCpuPkg/Library/MpInitLib/Microcode.c
View File

@@ -18,17 +18,17 @@
**/ **/
VOID VOID
MicrocodeDetect ( MicrocodeDetect (
IN CPU_MP_DATA *CpuMpData, IN CPU_MP_DATA *CpuMpData,
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
) )
{ {
CPU_MICROCODE_HEADER *Microcode; CPU_MICROCODE_HEADER *Microcode;
UINTN MicrocodeEnd; UINTN MicrocodeEnd;
CPU_AP_DATA *BspData; CPU_AP_DATA *BspData;
UINT32 LatestRevision; UINT32 LatestRevision;
CPU_MICROCODE_HEADER *LatestMicrocode; CPU_MICROCODE_HEADER *LatestMicrocode;
UINT32 ThreadId; UINT32 ThreadId;
EDKII_PEI_MICROCODE_CPU_ID MicrocodeCpuId; EDKII_PEI_MICROCODE_CPU_ID MicrocodeCpuId;
if (CpuMpData->MicrocodePatchRegionSize == 0) { if (CpuMpData->MicrocodePatchRegionSize == 0) {
// //
@@ -47,7 +47,7 @@ MicrocodeDetect (
GetProcessorMicrocodeCpuId (&MicrocodeCpuId); GetProcessorMicrocodeCpuId (&MicrocodeCpuId);
if (ProcessorNumber != (UINTN) CpuMpData->BspNumber) { if (ProcessorNumber != (UINTN)CpuMpData->BspNumber) {
// //
// Direct use microcode of BSP if AP is the same as BSP. // Direct use microcode of BSP if AP is the same as BSP.
// Assume BSP calls this routine() before AP. // Assume BSP calls this routine() before AP.
@@ -55,8 +55,9 @@ MicrocodeDetect (
BspData = &(CpuMpData->CpuData[CpuMpData->BspNumber]); BspData = &(CpuMpData->CpuData[CpuMpData->BspNumber]);
if ((BspData->ProcessorSignature == MicrocodeCpuId.ProcessorSignature) && if ((BspData->ProcessorSignature == MicrocodeCpuId.ProcessorSignature) &&
(BspData->PlatformId == MicrocodeCpuId.PlatformId) && (BspData->PlatformId == MicrocodeCpuId.PlatformId) &&
(BspData->MicrocodeEntryAddr != 0)) { (BspData->MicrocodeEntryAddr != 0))
LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN) BspData->MicrocodeEntryAddr; {
LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN)BspData->MicrocodeEntryAddr;
LatestRevision = LatestMicrocode->UpdateRevision; LatestRevision = LatestMicrocode->UpdateRevision;
goto LoadMicrocode; goto LoadMicrocode;
} }
@@ -69,11 +70,11 @@ MicrocodeDetect (
// //
LatestRevision = 0; LatestRevision = 0;
LatestMicrocode = NULL; LatestMicrocode = NULL;
Microcode = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress; Microcode = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress;
MicrocodeEnd = (UINTN) Microcode + (UINTN) CpuMpData->MicrocodePatchRegionSize; MicrocodeEnd = (UINTN)Microcode + (UINTN)CpuMpData->MicrocodePatchRegionSize;
do { do {
if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN) Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) { if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN)Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) {
// //
// It is the padding data between the microcode patches for microcode patches alignment. // It is the padding data between the microcode patches for microcode patches alignment.
// Because the microcode patch is the multiple of 1-KByte, the padding data should not // Because the microcode patch is the multiple of 1-KByte, the padding data should not
@@ -81,14 +82,15 @@ MicrocodeDetect (
// alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to // alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to
// find the next possible microcode patch header. // find the next possible microcode patch header.
// //
Microcode = (CPU_MICROCODE_HEADER *) ((UINTN) Microcode + SIZE_1KB); Microcode = (CPU_MICROCODE_HEADER *)((UINTN)Microcode + SIZE_1KB);
continue; continue;
} }
LatestMicrocode = Microcode; LatestMicrocode = Microcode;
LatestRevision = LatestMicrocode->UpdateRevision; LatestRevision = LatestMicrocode->UpdateRevision;
Microcode = (CPU_MICROCODE_HEADER *) (((UINTN) Microcode) + GetMicrocodeLength (Microcode)); Microcode = (CPU_MICROCODE_HEADER *)(((UINTN)Microcode) + GetMicrocodeLength (Microcode));
} while ((UINTN) Microcode < MicrocodeEnd); } while ((UINTN)Microcode < MicrocodeEnd);
LoadMicrocode: LoadMicrocode:
if (LatestRevision != 0) { if (LatestRevision != 0) {
@@ -97,7 +99,7 @@ LoadMicrocode:
// patch header) for each processor even it's the same as the loaded one. // patch header) for each processor even it's the same as the loaded one.
// It will be used when building the microcode patch cache HOB. // It will be used when building the microcode patch cache HOB.
// //
CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN) LatestMicrocode; CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN)LatestMicrocode;
} }
if (LatestRevision > GetProcessorMicrocodeSignature ()) { if (LatestRevision > GetProcessorMicrocodeSignature ()) {
@@ -109,6 +111,7 @@ LoadMicrocode:
// //
LoadMicrocode (LatestMicrocode); LoadMicrocode (LatestMicrocode);
} }
// //
// It's possible that the microcode fails to load. Just capture the CPU microcode revision after loading. // It's possible that the microcode fails to load. Just capture the CPU microcode revision after loading.
// //
@@ -129,15 +132,15 @@ LoadMicrocode:
**/ **/
VOID VOID
ShadowMicrocodePatchWorker ( ShadowMicrocodePatchWorker (
IN OUT CPU_MP_DATA *CpuMpData, IN OUT CPU_MP_DATA *CpuMpData,
IN MICROCODE_PATCH_INFO *Patches, IN MICROCODE_PATCH_INFO *Patches,
IN UINTN PatchCount, IN UINTN PatchCount,
IN UINTN TotalLoadSize IN UINTN TotalLoadSize
) )
{ {
UINTN Index; UINTN Index;
VOID *MicrocodePatchInRam; VOID *MicrocodePatchInRam;
UINT8 *Walker; UINT8 *Walker;
ASSERT ((Patches != NULL) && (PatchCount != 0)); ASSERT ((Patches != NULL) && (PatchCount != 0));
@@ -152,7 +155,7 @@ ShadowMicrocodePatchWorker (
for (Walker = MicrocodePatchInRam, Index = 0; Index < PatchCount; Index++) { for (Walker = MicrocodePatchInRam, Index = 0; Index < PatchCount; Index++) {
CopyMem ( CopyMem (
Walker, Walker,
(VOID *) Patches[Index].Address, (VOID *)Patches[Index].Address,
Patches[Index].Size Patches[Index].Size
); );
Walker += Patches[Index].Size; Walker += Patches[Index].Size;
@@ -161,13 +164,15 @@ ShadowMicrocodePatchWorker (
// //
// Update the microcode patch related fields in CpuMpData // Update the microcode patch related fields in CpuMpData
// //
CpuMpData->MicrocodePatchAddress = (UINTN) MicrocodePatchInRam; CpuMpData->MicrocodePatchAddress = (UINTN)MicrocodePatchInRam;
CpuMpData->MicrocodePatchRegionSize = TotalLoadSize; CpuMpData->MicrocodePatchRegionSize = TotalLoadSize;
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n", "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
__FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize __FUNCTION__,
CpuMpData->MicrocodePatchAddress,
CpuMpData->MicrocodePatchRegionSize
)); ));
return; return;
@@ -181,19 +186,19 @@ ShadowMicrocodePatchWorker (
**/ **/
VOID VOID
ShadowMicrocodePatchByPcd ( ShadowMicrocodePatchByPcd (
IN OUT CPU_MP_DATA *CpuMpData IN OUT CPU_MP_DATA *CpuMpData
) )
{ {
UINTN Index; UINTN Index;
CPU_MICROCODE_HEADER *MicrocodeEntryPoint; CPU_MICROCODE_HEADER *MicrocodeEntryPoint;
UINTN MicrocodeEnd; UINTN MicrocodeEnd;
UINTN TotalSize; UINTN TotalSize;
MICROCODE_PATCH_INFO *PatchInfoBuffer; MICROCODE_PATCH_INFO *PatchInfoBuffer;
UINTN MaxPatchNumber; UINTN MaxPatchNumber;
UINTN PatchCount; UINTN PatchCount;
UINTN TotalLoadSize; UINTN TotalLoadSize;
EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds; EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds;
BOOLEAN Valid; BOOLEAN Valid;
// //
// Initialize the microcode patch related fields in CpuMpData as the values // Initialize the microcode patch related fields in CpuMpData as the values
@@ -203,10 +208,10 @@ ShadowMicrocodePatchByPcd (
CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress); CpuMpData->MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress);
CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize); CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);
MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress; MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress;
MicrocodeEnd = (UINTN) MicrocodeEntryPoint + MicrocodeEnd = (UINTN)MicrocodeEntryPoint +
(UINTN) CpuMpData->MicrocodePatchRegionSize; (UINTN)CpuMpData->MicrocodePatchRegionSize;
if ((MicrocodeEntryPoint == NULL) || ((UINTN) MicrocodeEntryPoint == MicrocodeEnd)) { if ((MicrocodeEntryPoint == NULL) || ((UINTN)MicrocodeEntryPoint == MicrocodeEnd)) {
// //
// There is no microcode patches // There is no microcode patches
// //
@@ -242,7 +247,7 @@ ShadowMicrocodePatchByPcd (
do { do {
Valid = IsValidMicrocode ( Valid = IsValidMicrocode (
MicrocodeEntryPoint, MicrocodeEntryPoint,
MicrocodeEnd - (UINTN) MicrocodeEntryPoint, MicrocodeEnd - (UINTN)MicrocodeEntryPoint,
0, 0,
MicrocodeCpuIds, MicrocodeCpuIds,
CpuMpData->CpuCount, CpuMpData->CpuCount,
@@ -252,7 +257,7 @@ ShadowMicrocodePatchByPcd (
// //
// Padding data between the microcode patches, skip 1KB to check next entry. // Padding data between the microcode patches, skip 1KB to check next entry.
// //
MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + SIZE_1KB); MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(((UINTN)MicrocodeEntryPoint) + SIZE_1KB);
continue; continue;
} }
@@ -277,6 +282,7 @@ ShadowMicrocodePatchByPcd (
if (PatchInfoBuffer == NULL) { if (PatchInfoBuffer == NULL) {
goto OnExit; goto OnExit;
} }
MaxPatchNumber = MaxPatchNumber * 2; MaxPatchNumber = MaxPatchNumber * 2;
} }
@@ -285,21 +291,23 @@ ShadowMicrocodePatchByPcd (
// //
// Store the information of this microcode patch // Store the information of this microcode patch
// //
PatchInfoBuffer[PatchCount - 1].Address = (UINTN) MicrocodeEntryPoint; PatchInfoBuffer[PatchCount - 1].Address = (UINTN)MicrocodeEntryPoint;
PatchInfoBuffer[PatchCount - 1].Size = TotalSize; PatchInfoBuffer[PatchCount - 1].Size = TotalSize;
TotalLoadSize += TotalSize; TotalLoadSize += TotalSize;
// //
// Process the next microcode patch // Process the next microcode patch
// //
MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) ((UINTN) MicrocodeEntryPoint + TotalSize); MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)((UINTN)MicrocodeEntryPoint + TotalSize);
} while ((UINTN) MicrocodeEntryPoint < MicrocodeEnd); } while ((UINTN)MicrocodeEntryPoint < MicrocodeEnd);
if (PatchCount != 0) { if (PatchCount != 0) {
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n", "%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n",
__FUNCTION__, PatchCount, TotalLoadSize __FUNCTION__,
PatchCount,
TotalLoadSize
)); ));
ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, TotalLoadSize); ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, TotalLoadSize);
@@ -309,6 +317,7 @@ OnExit:
if (PatchInfoBuffer != NULL) { if (PatchInfoBuffer != NULL) {
FreePool (PatchInfoBuffer); FreePool (PatchInfoBuffer);
} }
FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDKII_PEI_MICROCODE_CPU_ID))); FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDKII_PEI_MICROCODE_CPU_ID)));
} }
@@ -319,10 +328,10 @@ OnExit:
**/ **/
VOID VOID
ShadowMicrocodeUpdatePatch ( ShadowMicrocodeUpdatePatch (
IN OUT CPU_MP_DATA *CpuMpData IN OUT CPU_MP_DATA *CpuMpData
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
Status = PlatformShadowMicrocode (CpuMpData); Status = PlatformShadowMicrocode (CpuMpData);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@@ -347,16 +356,16 @@ ShadowMicrocodeUpdatePatch (
**/ **/
BOOLEAN BOOLEAN
GetMicrocodePatchInfoFromHob ( GetMicrocodePatchInfoFromHob (
UINT64 *Address, UINT64 *Address,
UINT64 *RegionSize UINT64 *RegionSize
) )
{ {
EFI_HOB_GUID_TYPE *GuidHob; EFI_HOB_GUID_TYPE *GuidHob;
EDKII_MICROCODE_PATCH_HOB *MicrocodePathHob; EDKII_MICROCODE_PATCH_HOB *MicrocodePathHob;
GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid); GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid);
if (GuidHob == NULL) { if (GuidHob == NULL) {
DEBUG((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__)); DEBUG ((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__));
return FALSE; return FALSE;
} }
@@ -365,9 +374,12 @@ GetMicrocodePatchInfoFromHob (
*Address = MicrocodePathHob->MicrocodePatchAddress; *Address = MicrocodePathHob->MicrocodePatchAddress;
*RegionSize = MicrocodePathHob->MicrocodePatchRegionSize; *RegionSize = MicrocodePathHob->MicrocodePatchRegionSize;
DEBUG(( DEBUG ((
DEBUG_INFO, "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n", DEBUG_INFO,
__FUNCTION__, *Address, *RegionSize "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n",
__FUNCTION__,
*Address,
*RegionSize
)); ));
return TRUE; return TRUE;

759
UefiCpuPkg/Library/MpInitLib/MpLib.c
View File

File diff suppressed because it is too large Load Diff

347
UefiCpuPkg/Library/MpInitLib/MpLib.h
View File

@@ -36,7 +36,7 @@
#include <Guid/MicrocodePatchHob.h> #include <Guid/MicrocodePatchHob.h>
#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P') #define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')
#define CPU_INIT_MP_LIB_HOB_GUID \ #define CPU_INIT_MP_LIB_HOB_GUID \
{ \ { \
@@ -46,14 +46,14 @@
// //
// The MP data for switch BSP // The MP data for switch BSP
// //
#define CPU_SWITCH_STATE_IDLE 0 #define CPU_SWITCH_STATE_IDLE 0
#define CPU_SWITCH_STATE_STORED 1 #define CPU_SWITCH_STATE_STORED 1
#define CPU_SWITCH_STATE_LOADED 2 #define CPU_SWITCH_STATE_LOADED 2
// //
// Default maximum number of entries to store the microcode patches information // Default maximum number of entries to store the microcode patches information
// //
#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8 #define DEFAULT_MAX_MICROCODE_PATCH_NUM 8
// //
// Data structure for microcode patch information // Data structure for microcode patch information
@@ -67,10 +67,10 @@ typedef struct {
// CPU exchange information for switch BSP // CPU exchange information for switch BSP
// //
typedef struct { typedef struct {
UINT8 State; // offset 0 UINT8 State; // offset 0
UINTN StackPointer; // offset 4 / 8 UINTN StackPointer; // offset 4 / 8
IA32_DESCRIPTOR Gdtr; // offset 8 / 16 IA32_DESCRIPTOR Gdtr; // offset 8 / 16
IA32_DESCRIPTOR Idtr; // offset 14 / 26 IA32_DESCRIPTOR Idtr; // offset 14 / 26
} CPU_EXCHANGE_ROLE_INFO; } CPU_EXCHANGE_ROLE_INFO;
// //
@@ -111,41 +111,41 @@ typedef enum {
// CPU volatile registers around INIT-SIPI-SIPI // CPU volatile registers around INIT-SIPI-SIPI
// //
typedef struct { typedef struct {
UINTN Cr0; UINTN Cr0;
UINTN Cr3; UINTN Cr3;
UINTN Cr4; UINTN Cr4;
UINTN Dr0; UINTN Dr0;
UINTN Dr1; UINTN Dr1;
UINTN Dr2; UINTN Dr2;
UINTN Dr3; UINTN Dr3;
UINTN Dr6; UINTN Dr6;
UINTN Dr7; UINTN Dr7;
IA32_DESCRIPTOR Gdtr; IA32_DESCRIPTOR Gdtr;
IA32_DESCRIPTOR Idtr; IA32_DESCRIPTOR Idtr;
UINT16 Tr; UINT16 Tr;
} CPU_VOLATILE_REGISTERS; } CPU_VOLATILE_REGISTERS;
// //
// AP related data // AP related data
// //
typedef struct { typedef struct {
SPIN_LOCK ApLock; SPIN_LOCK ApLock;
volatile UINT32 *StartupApSignal; volatile UINT32 *StartupApSignal;
volatile UINTN ApFunction; volatile UINTN ApFunction;
volatile UINTN ApFunctionArgument; volatile UINTN ApFunctionArgument;
BOOLEAN CpuHealthy; BOOLEAN CpuHealthy;
volatile CPU_STATE State; volatile CPU_STATE State;
CPU_VOLATILE_REGISTERS VolatileRegisters; CPU_VOLATILE_REGISTERS VolatileRegisters;
BOOLEAN Waiting; BOOLEAN Waiting;
BOOLEAN *Finished; BOOLEAN *Finished;
UINT64 ExpectedTime; UINT64 ExpectedTime;
UINT64 CurrentTime; UINT64 CurrentTime;
UINT64 TotalTime; UINT64 TotalTime;
EFI_EVENT WaitEvent; EFI_EVENT WaitEvent;
UINT32 ProcessorSignature; UINT32 ProcessorSignature;
UINT8 PlatformId; UINT8 PlatformId;
UINT64 MicrocodeEntryAddr; UINT64 MicrocodeEntryAddr;
UINT32 MicrocodeRevision; UINT32 MicrocodeRevision;
} CPU_AP_DATA; } CPU_AP_DATA;
// //
@@ -156,10 +156,10 @@ typedef struct {
// //
#pragma pack (1) #pragma pack (1)
typedef struct { typedef struct {
UINT32 InitialApicId; UINT32 InitialApicId;
UINT32 ApicId; UINT32 ApicId;
UINT32 Health; UINT32 Health;
UINT64 ApTopOfStack; UINT64 ApTopOfStack;
} CPU_INFO_IN_HOB; } CPU_INFO_IN_HOB;
#pragma pack () #pragma pack ()
@@ -169,20 +169,20 @@ typedef struct {
// It is natural aligned by design. // It is natural aligned by design.
// //
typedef struct { typedef struct {
UINT8 *RendezvousFunnelAddress; UINT8 *RendezvousFunnelAddress;
UINTN ModeEntryOffset; UINTN ModeEntryOffset;
UINTN RendezvousFunnelSize; UINTN RendezvousFunnelSize;
UINT8 *RelocateApLoopFuncAddress; UINT8 *RelocateApLoopFuncAddress;
UINTN RelocateApLoopFuncSize; UINTN RelocateApLoopFuncSize;
UINTN ModeTransitionOffset; UINTN ModeTransitionOffset;
UINTN SwitchToRealSize; UINTN SwitchToRealSize;
UINTN SwitchToRealOffset; UINTN SwitchToRealOffset;
UINTN SwitchToRealNoNxOffset; UINTN SwitchToRealNoNxOffset;
UINTN SwitchToRealPM16ModeOffset; UINTN SwitchToRealPM16ModeOffset;
UINTN SwitchToRealPM16ModeSize; UINTN SwitchToRealPM16ModeSize;
} MP_ASSEMBLY_ADDRESS_MAP; } MP_ASSEMBLY_ADDRESS_MAP;
typedef struct _CPU_MP_DATA CPU_MP_DATA; typedef struct _CPU_MP_DATA CPU_MP_DATA;
#pragma pack(1) #pragma pack(1)
@@ -192,33 +192,33 @@ typedef struct _CPU_MP_DATA CPU_MP_DATA;
// into this structure are used in assembly code in this module // into this structure are used in assembly code in this module
// //
typedef struct { typedef struct {
UINTN StackStart; UINTN StackStart;
UINTN StackSize; UINTN StackSize;
UINTN CFunction; UINTN CFunction;
IA32_DESCRIPTOR GdtrProfile; IA32_DESCRIPTOR GdtrProfile;
IA32_DESCRIPTOR IdtrProfile; IA32_DESCRIPTOR IdtrProfile;
UINTN BufferStart; UINTN BufferStart;
UINTN ModeOffset; UINTN ModeOffset;
UINTN ApIndex; UINTN ApIndex;
UINTN CodeSegment; UINTN CodeSegment;
UINTN DataSegment; UINTN DataSegment;
UINTN EnableExecuteDisable; UINTN EnableExecuteDisable;
UINTN Cr3; UINTN Cr3;
UINTN InitFlag; UINTN InitFlag;
CPU_INFO_IN_HOB *CpuInfo; CPU_INFO_IN_HOB *CpuInfo;
UINTN NumApsExecuting; UINTN NumApsExecuting;
CPU_MP_DATA *CpuMpData; CPU_MP_DATA *CpuMpData;
UINTN InitializeFloatingPointUnitsAddress; UINTN InitializeFloatingPointUnitsAddress;
UINT32 ModeTransitionMemory; UINT32 ModeTransitionMemory;
UINT16 ModeTransitionSegment; UINT16 ModeTransitionSegment;
UINT32 ModeHighMemory; UINT32 ModeHighMemory;
UINT16 ModeHighSegment; UINT16 ModeHighSegment;
// //
// Enable5LevelPaging indicates whether 5-level paging is enabled in long mode. // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.
// //
BOOLEAN Enable5LevelPaging; BOOLEAN Enable5LevelPaging;
BOOLEAN SevEsIsEnabled; BOOLEAN SevEsIsEnabled;
UINTN GhcbBase; UINTN GhcbBase;
} MP_CPU_EXCHANGE_INFO; } MP_CPU_EXCHANGE_INFO;
#pragma pack() #pragma pack()
@@ -227,55 +227,55 @@ typedef struct {
// CPU MP Data save in memory // CPU MP Data save in memory
// //
struct _CPU_MP_DATA { struct _CPU_MP_DATA {
UINT64 CpuInfoInHob; UINT64 CpuInfoInHob;
UINT32 CpuCount; UINT32 CpuCount;
UINT32 BspNumber; UINT32 BspNumber;
// //
// The above fields data will be passed from PEI to DXE // The above fields data will be passed from PEI to DXE
// Please make sure the fields offset same in the different // Please make sure the fields offset same in the different
// architecture. // architecture.
// //
SPIN_LOCK MpLock; SPIN_LOCK MpLock;
UINTN Buffer; UINTN Buffer;
UINTN CpuApStackSize; UINTN CpuApStackSize;
MP_ASSEMBLY_ADDRESS_MAP AddressMap; MP_ASSEMBLY_ADDRESS_MAP AddressMap;
UINTN WakeupBuffer; UINTN WakeupBuffer;
UINTN WakeupBufferHigh; UINTN WakeupBufferHigh;
UINTN BackupBuffer; UINTN BackupBuffer;
UINTN BackupBufferSize; UINTN BackupBufferSize;
volatile UINT32 FinishedCount; volatile UINT32 FinishedCount;
UINT32 RunningCount; UINT32 RunningCount;
BOOLEAN SingleThread; BOOLEAN SingleThread;
EFI_AP_PROCEDURE Procedure; EFI_AP_PROCEDURE Procedure;
VOID *ProcArguments; VOID *ProcArguments;
BOOLEAN *Finished; BOOLEAN *Finished;
UINT64 ExpectedTime; UINT64 ExpectedTime;
UINT64 CurrentTime; UINT64 CurrentTime;
UINT64 TotalTime; UINT64 TotalTime;
EFI_EVENT WaitEvent; EFI_EVENT WaitEvent;
UINTN **FailedCpuList; UINTN **FailedCpuList;
AP_INIT_STATE InitFlag; AP_INIT_STATE InitFlag;
BOOLEAN SwitchBspFlag; BOOLEAN SwitchBspFlag;
UINTN NewBspNumber; UINTN NewBspNumber;
CPU_EXCHANGE_ROLE_INFO BSPInfo; CPU_EXCHANGE_ROLE_INFO BSPInfo;
CPU_EXCHANGE_ROLE_INFO APInfo; CPU_EXCHANGE_ROLE_INFO APInfo;
MTRR_SETTINGS MtrrTable; MTRR_SETTINGS MtrrTable;
UINT8 ApLoopMode; UINT8 ApLoopMode;
UINT8 ApTargetCState; UINT8 ApTargetCState;
UINT16 PmCodeSegment; UINT16 PmCodeSegment;
UINT16 Pm16CodeSegment; UINT16 Pm16CodeSegment;
CPU_AP_DATA *CpuData; CPU_AP_DATA *CpuData;
volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo; volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo;
UINT32 CurrentTimerCount; UINT32 CurrentTimerCount;
UINTN DivideValue; UINTN DivideValue;
UINT8 Vector; UINT8 Vector;
BOOLEAN PeriodicMode; BOOLEAN PeriodicMode;
BOOLEAN TimerInterruptState; BOOLEAN TimerInterruptState;
UINT64 MicrocodePatchAddress; UINT64 MicrocodePatchAddress;
UINT64 MicrocodePatchRegionSize; UINT64 MicrocodePatchRegionSize;
// //
// Whether need to use Init-Sipi-Sipi to wake up the APs. // Whether need to use Init-Sipi-Sipi to wake up the APs.
@@ -284,25 +284,25 @@ struct _CPU_MP_DATA {
// will be hardcode change to HLT mode by PiSmmCpuDxeSmm // will be hardcode change to HLT mode by PiSmmCpuDxeSmm
// driver. // driver.
// //
BOOLEAN WakeUpByInitSipiSipi; BOOLEAN WakeUpByInitSipiSipi;
BOOLEAN SevEsIsEnabled; BOOLEAN SevEsIsEnabled;
UINTN SevEsAPBuffer; UINTN SevEsAPBuffer;
UINTN SevEsAPResetStackStart; UINTN SevEsAPResetStackStart;
CPU_MP_DATA *NewCpuMpData; CPU_MP_DATA *NewCpuMpData;
UINT64 GhcbBase; UINT64 GhcbBase;
}; };
#define AP_SAFE_STACK_SIZE 128 #define AP_SAFE_STACK_SIZE 128
#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE #define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE
#pragma pack(1) #pragma pack(1)
typedef struct { typedef struct {
UINT8 InsnBuffer[8]; UINT8 InsnBuffer[8];
UINT16 Rip; UINT16 Rip;
UINT16 Segment; UINT16 Segment;
} SEV_ES_AP_JMP_FAR; } SEV_ES_AP_JMP_FAR;
#pragma pack() #pragma pack()
@@ -322,14 +322,14 @@ typedef struct {
**/ **/
typedef typedef
VOID VOID
(EFIAPI AP_RESET) ( (EFIAPI AP_RESET)(
IN UINTN BufferStart, IN UINTN BufferStart,
IN UINT16 Code16, IN UINT16 Code16,
IN UINT16 Code32, IN UINT16 Code32,
IN UINTN StackStart IN UINTN StackStart
); );
extern EFI_GUID mCpuInitMpLibHobGuid; extern EFI_GUID mCpuInitMpLibHobGuid;
/** /**
Assembly code to place AP into safe loop mode. Assembly code to place AP into safe loop mode.
@@ -347,7 +347,7 @@ extern EFI_GUID mCpuInitMpLibHobGuid;
**/ **/
typedef typedef
VOID VOID
(EFIAPI * ASM_RELOCATE_AP_LOOP) ( (EFIAPI *ASM_RELOCATE_AP_LOOP)(
IN BOOLEAN MwaitSupport, IN BOOLEAN MwaitSupport,
IN UINTN ApTargetCState, IN UINTN ApTargetCState,
IN UINTN PmCodeSegment, IN UINTN PmCodeSegment,
@@ -367,7 +367,7 @@ VOID
VOID VOID
EFIAPI EFIAPI
AsmGetAddressMap ( AsmGetAddressMap (
OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap
); );
/** /**
@@ -382,8 +382,8 @@ AsmGetAddressMap (
VOID VOID
EFIAPI EFIAPI
AsmExchangeRole ( AsmExchangeRole (
IN CPU_EXCHANGE_ROLE_INFO *MyInfo, IN CPU_EXCHANGE_ROLE_INFO *MyInfo,
IN CPU_EXCHANGE_ROLE_INFO *OthersInfo IN CPU_EXCHANGE_ROLE_INFO *OthersInfo
); );
/** /**
@@ -403,10 +403,9 @@ GetCpuMpData (
**/ **/
VOID VOID
SaveCpuMpData ( SaveCpuMpData (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
); );
/** /**
Get available system memory below 1MB by specified size. Get available system memory below 1MB by specified size.
@@ -417,7 +416,7 @@ SaveCpuMpData (
**/ **/
UINTN UINTN
GetWakeupBuffer ( GetWakeupBuffer (
IN UINTN WakeupBufferSize IN UINTN WakeupBufferSize
); );
/** /**
@@ -434,7 +433,7 @@ GetWakeupBuffer (
**/ **/
UINTN UINTN
GetModeTransitionBuffer ( GetModeTransitionBuffer (
IN UINTN BufferSize IN UINTN BufferSize
); );
/** /**
@@ -463,12 +462,12 @@ GetSevEsAPMemory (
**/ **/
VOID VOID
WakeUpAP ( WakeUpAP (
IN CPU_MP_DATA *CpuMpData, IN CPU_MP_DATA *CpuMpData,
IN BOOLEAN Broadcast, IN BOOLEAN Broadcast,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN EFI_AP_PROCEDURE Procedure OPTIONAL, IN EFI_AP_PROCEDURE Procedure OPTIONAL,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
IN BOOLEAN WakeUpDisabledAps OPTIONAL IN BOOLEAN WakeUpDisabledAps OPTIONAL
); );
/** /**
@@ -478,7 +477,7 @@ WakeUpAP (
**/ **/
VOID VOID
InitMpGlobalData ( InitMpGlobalData (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
); );
/** /**
@@ -515,13 +514,13 @@ InitMpGlobalData (
**/ **/
EFI_STATUS EFI_STATUS
StartupAllCPUsWorker ( StartupAllCPUsWorker (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
IN BOOLEAN ExcludeBsp, IN BOOLEAN ExcludeBsp,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT UINTN **FailedCpuList OPTIONAL OUT UINTN **FailedCpuList OPTIONAL
); );
/** /**
@@ -549,12 +548,12 @@ StartupAllCPUsWorker (
**/ **/
EFI_STATUS EFI_STATUS
StartupThisAPWorker ( StartupThisAPWorker (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT BOOLEAN *Finished OPTIONAL OUT BOOLEAN *Finished OPTIONAL
); );
/** /**
@@ -570,8 +569,8 @@ StartupThisAPWorker (
**/ **/
EFI_STATUS EFI_STATUS
SwitchBSPWorker ( SwitchBSPWorker (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableOldBSP IN BOOLEAN EnableOldBSP
); );
/** /**
@@ -590,9 +589,9 @@ SwitchBSPWorker (
**/ **/
EFI_STATUS EFI_STATUS
EnableDisableApWorker ( EnableDisableApWorker (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL IN UINT32 *HealthFlag OPTIONAL
); );
/** /**
@@ -618,7 +617,7 @@ GetCpuMpDataFromGuidedHob (
**/ **/
EFI_STATUS EFI_STATUS
CheckThisAP ( CheckThisAP (
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
); );
/** /**
@@ -655,8 +654,8 @@ CheckAndUpdateApsStatus (
**/ **/
VOID VOID
MicrocodeDetect ( MicrocodeDetect (
IN CPU_MP_DATA *CpuMpData, IN CPU_MP_DATA *CpuMpData,
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
); );
/** /**
@@ -666,7 +665,7 @@ MicrocodeDetect (
**/ **/
VOID VOID
ShadowMicrocodeUpdatePatch ( ShadowMicrocodeUpdatePatch (
IN OUT CPU_MP_DATA *CpuMpData IN OUT CPU_MP_DATA *CpuMpData
); );
/** /**
@@ -686,8 +685,8 @@ ShadowMicrocodeUpdatePatch (
**/ **/
BOOLEAN BOOLEAN
GetMicrocodePatchInfoFromHob ( GetMicrocodePatchInfoFromHob (
UINT64 *Address, UINT64 *Address,
UINT64 *RegionSize UINT64 *RegionSize
); );
/** /**
@@ -721,8 +720,8 @@ EnableDebugAgent (
**/ **/
EFI_STATUS EFI_STATUS
GetProcessorNumber ( GetProcessorNumber (
IN CPU_MP_DATA *CpuMpData, IN CPU_MP_DATA *CpuMpData,
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
); );
/** /**
@@ -738,7 +737,7 @@ GetProcessorNumber (
**/ **/
EFI_STATUS EFI_STATUS
PlatformShadowMicrocode ( PlatformShadowMicrocode (
IN OUT CPU_MP_DATA *CpuMpData IN OUT CPU_MP_DATA *CpuMpData
); );
#endif #endif

166
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
View File

@@ -11,7 +11,7 @@
#include <Guid/S3SmmInitDone.h> #include <Guid/S3SmmInitDone.h>
#include <Ppi/ShadowMicrocode.h> #include <Ppi/ShadowMicrocode.h>
STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB; STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB;
/** /**
S3 SMM Init Done notification function. S3 SMM Init Done notification function.
@@ -26,16 +26,15 @@ STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB;
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NotifyOnS3SmmInitDonePpi ( NotifyOnS3SmmInitDonePpi (
IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
IN VOID *InvokePpi IN VOID *InvokePpi
); );
// //
// Global function // Global function
// //
EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = { EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = {
EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEdkiiS3SmmInitDoneGuid, &gEdkiiS3SmmInitDoneGuid,
NotifyOnS3SmmInitDonePpi NotifyOnS3SmmInitDonePpi
@@ -54,12 +53,12 @@ EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc = {
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
NotifyOnS3SmmInitDonePpi ( NotifyOnS3SmmInitDonePpi (
IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
IN VOID *InvokePpi IN VOID *InvokePpi
) )
{ {
CPU_MP_DATA *CpuMpData; CPU_MP_DATA *CpuMpData;
CpuMpData = GetCpuMpData (); CpuMpData = GetCpuMpData ();
@@ -76,7 +75,6 @@ NotifyOnS3SmmInitDonePpi (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
/** /**
Enable Debug Agent to support source debugging on AP function. Enable Debug Agent to support source debugging on AP function.
@@ -110,8 +108,9 @@ GetCpuMpData (
ASSERT (CpuMpData != NULL); ASSERT (CpuMpData != NULL);
} else { } else {
AsmReadIdtr (&Idtr); AsmReadIdtr (&Idtr);
CpuMpData = (CPU_MP_DATA *) (Idtr.Base + Idtr.Limit + 1); CpuMpData = (CPU_MP_DATA *)(Idtr.Base + Idtr.Limit + 1);
} }
return CpuMpData; return CpuMpData;
} }
@@ -122,17 +121,18 @@ GetCpuMpData (
**/ **/
VOID VOID
SaveCpuMpData ( SaveCpuMpData (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
) )
{ {
UINT64 Data64; UINT64 Data64;
// //
// Build location of CPU MP DATA buffer in HOB // Build location of CPU MP DATA buffer in HOB
// //
Data64 = (UINT64) (UINTN) CpuMpData; Data64 = (UINT64)(UINTN)CpuMpData;
BuildGuidDataHob ( BuildGuidDataHob (
&mCpuInitMpLibHobGuid, &mCpuInitMpLibHobGuid,
(VOID *) &Data64, (VOID *)&Data64,
sizeof (UINT64) sizeof (UINT64)
); );
} }
@@ -148,15 +148,15 @@ SaveCpuMpData (
**/ **/
BOOLEAN BOOLEAN
CheckOverlapWithAllocatedBuffer ( CheckOverlapWithAllocatedBuffer (
IN UINT64 WakeupBufferStart, IN UINT64 WakeupBufferStart,
IN UINT64 WakeupBufferEnd IN UINT64 WakeupBufferEnd
) )
{ {
EFI_PEI_HOB_POINTERS Hob; EFI_PEI_HOB_POINTERS Hob;
EFI_HOB_MEMORY_ALLOCATION *MemoryHob; EFI_HOB_MEMORY_ALLOCATION *MemoryHob;
BOOLEAN Overlapped; BOOLEAN Overlapped;
UINT64 MemoryStart; UINT64 MemoryStart;
UINT64 MemoryEnd; UINT64 MemoryEnd;
Overlapped = FALSE; Overlapped = FALSE;
// //
@@ -176,8 +176,10 @@ CheckOverlapWithAllocatedBuffer (
break; break;
} }
} }
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
} }
return Overlapped; return Overlapped;
} }
@@ -191,12 +193,12 @@ CheckOverlapWithAllocatedBuffer (
**/ **/
UINTN UINTN
GetWakeupBuffer ( GetWakeupBuffer (
IN UINTN WakeupBufferSize IN UINTN WakeupBufferSize
) )
{ {
EFI_PEI_HOB_POINTERS Hob; EFI_PEI_HOB_POINTERS Hob;
UINT64 WakeupBufferStart; UINT64 WakeupBufferStart;
UINT64 WakeupBufferEnd; UINT64 WakeupBufferEnd;
WakeupBufferSize = (WakeupBufferSize + SIZE_4KB - 1) & ~(SIZE_4KB - 1); WakeupBufferSize = (WakeupBufferSize + SIZE_4KB - 1) & ~(SIZE_4KB - 1);
@@ -216,14 +218,16 @@ GetWakeupBuffer (
(EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED | (EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED |
EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED | EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED |
EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED
)) == 0) )) == 0)
) { )
{
// //
// Need memory under 1MB to be collected here // Need memory under 1MB to be collected here
// //
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength; WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
if (PcdGetBool (PcdSevEsIsEnabled) && if (PcdGetBool (PcdSevEsIsEnabled) &&
WakeupBufferEnd > mSevEsPeiWakeupBuffer) { (WakeupBufferEnd > mSevEsPeiWakeupBuffer))
{
// //
// SEV-ES Wakeup buffer should be under 1MB and under any previous one // SEV-ES Wakeup buffer should be under 1MB and under any previous one
// //
@@ -234,6 +238,7 @@ GetWakeupBuffer (
// //
WakeupBufferEnd = BASE_1MB; WakeupBufferEnd = BASE_1MB;
} }
while (WakeupBufferEnd > WakeupBufferSize) { while (WakeupBufferEnd > WakeupBufferSize) {
// //
// Wakeup buffer should be aligned on 4KB // Wakeup buffer should be aligned on 4KB
@@ -242,6 +247,7 @@ GetWakeupBuffer (
if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) { if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) {
break; break;
} }
if (CheckOverlapWithAllocatedBuffer (WakeupBufferStart, WakeupBufferEnd)) { if (CheckOverlapWithAllocatedBuffer (WakeupBufferStart, WakeupBufferEnd)) {
// //
// If this range is overlapped with existing allocated buffer, skip it // If this range is overlapped with existing allocated buffer, skip it
@@ -250,8 +256,13 @@ GetWakeupBuffer (
WakeupBufferEnd -= WakeupBufferSize; WakeupBufferEnd -= WakeupBufferSize;
continue; continue;
} }
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart, WakeupBufferSize)); DEBUG ((
DEBUG_INFO,
"WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart,
WakeupBufferSize
));
if (PcdGetBool (PcdSevEsIsEnabled)) { if (PcdGetBool (PcdSevEsIsEnabled)) {
// //
@@ -265,13 +276,14 @@ GetWakeupBuffer (
} }
} }
} }
// //
// Find the next HOB // Find the next HOB
// //
Hob.Raw = GET_NEXT_HOB (Hob); Hob.Raw = GET_NEXT_HOB (Hob);
} }
return (UINTN) -1; return (UINTN)-1;
} }
/** /**
@@ -288,7 +300,7 @@ GetWakeupBuffer (
**/ **/
UINTN UINTN
GetModeTransitionBuffer ( GetModeTransitionBuffer (
IN UINTN BufferSize IN UINTN BufferSize
) )
{ {
// //
@@ -336,17 +348,17 @@ CheckAndUpdateApsStatus (
**/ **/
VOID VOID
BuildMicrocodeCacheHob ( BuildMicrocodeCacheHob (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
) )
{ {
EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; EDKII_MICROCODE_PATCH_HOB *MicrocodeHob;
UINTN HobDataLength; UINTN HobDataLength;
UINT32 Index; UINT32 Index;
HobDataLength = sizeof (EDKII_MICROCODE_PATCH_HOB) + HobDataLength = sizeof (EDKII_MICROCODE_PATCH_HOB) +
sizeof (UINT64) * CpuMpData->CpuCount; sizeof (UINT64) * CpuMpData->CpuCount;
MicrocodeHob = AllocatePool (HobDataLength); MicrocodeHob = AllocatePool (HobDataLength);
if (MicrocodeHob == NULL) { if (MicrocodeHob == NULL) {
ASSERT (FALSE); ASSERT (FALSE);
return; return;
@@ -387,7 +399,7 @@ BuildMicrocodeCacheHob (
**/ **/
VOID VOID
InitMpGlobalData ( InitMpGlobalData (
IN CPU_MP_DATA *CpuMpData IN CPU_MP_DATA *CpuMpData
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
@@ -480,12 +492,12 @@ InitMpGlobalData (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupAllAPs ( MpInitLibStartupAllAPs (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT UINTN **FailedCpuList OPTIONAL OUT UINTN **FailedCpuList OPTIONAL
) )
{ {
if (WaitEvent != NULL) { if (WaitEvent != NULL) {
@@ -577,12 +589,12 @@ MpInitLibStartupAllAPs (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupThisAP ( MpInitLibStartupThisAP (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT BOOLEAN *Finished OPTIONAL OUT BOOLEAN *Finished OPTIONAL
) )
{ {
if (WaitEvent != NULL) { if (WaitEvent != NULL) {
@@ -628,8 +640,8 @@ MpInitLibStartupThisAP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibSwitchBSP ( MpInitLibSwitchBSP (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableOldBSP IN BOOLEAN EnableOldBSP
) )
{ {
return SwitchBSPWorker (ProcessorNumber, EnableOldBSP); return SwitchBSPWorker (ProcessorNumber, EnableOldBSP);
@@ -668,9 +680,9 @@ MpInitLibSwitchBSP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibEnableDisableAP ( MpInitLibEnableDisableAP (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL IN UINT32 *HealthFlag OPTIONAL
) )
{ {
return EnableDisableApWorker (ProcessorNumber, EnableAP, HealthFlag); return EnableDisableApWorker (ProcessorNumber, EnableAP, HealthFlag);
@@ -689,29 +701,29 @@ MpInitLibEnableDisableAP (
**/ **/
EFI_STATUS EFI_STATUS
PlatformShadowMicrocode ( PlatformShadowMicrocode (
IN OUT CPU_MP_DATA *CpuMpData IN OUT CPU_MP_DATA *CpuMpData
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EDKII_PEI_SHADOW_MICROCODE_PPI *ShadowMicrocodePpi; EDKII_PEI_SHADOW_MICROCODE_PPI *ShadowMicrocodePpi;
UINTN CpuCount; UINTN CpuCount;
EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId; EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId;
UINTN Index; UINTN Index;
UINTN BufferSize; UINTN BufferSize;
VOID *Buffer; VOID *Buffer;
Status = PeiServicesLocatePpi ( Status = PeiServicesLocatePpi (
&gEdkiiPeiShadowMicrocodePpiGuid, &gEdkiiPeiShadowMicrocodePpiGuid,
0, 0,
NULL, NULL,
(VOID **) &ShadowMicrocodePpi (VOID **)&ShadowMicrocodePpi
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
CpuCount = CpuMpData->CpuCount; CpuCount = CpuMpData->CpuCount;
MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *) AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount); MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *)AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount);
if (MicrocodeCpuId == NULL) { if (MicrocodeCpuId == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
@@ -722,24 +734,26 @@ PlatformShadowMicrocode (
} }
Status = ShadowMicrocodePpi->ShadowMicrocode ( Status = ShadowMicrocodePpi->ShadowMicrocode (
ShadowMicrocodePpi, ShadowMicrocodePpi,
CpuCount, CpuCount,
MicrocodeCpuId, MicrocodeCpuId,
&BufferSize, &BufferSize,
&Buffer &Buffer
); );
FreePool (MicrocodeCpuId); FreePool (MicrocodeCpuId);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
CpuMpData->MicrocodePatchAddress = (UINTN) Buffer; CpuMpData->MicrocodePatchAddress = (UINTN)Buffer;
CpuMpData->MicrocodePatchRegionSize = BufferSize; CpuMpData->MicrocodePatchRegionSize = BufferSize;
DEBUG (( DEBUG ((
DEBUG_INFO, DEBUG_INFO,
"%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n", "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
__FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize __FUNCTION__,
CpuMpData->MicrocodePatchAddress,
CpuMpData->MicrocodePatchRegionSize
)); ));
return EFI_SUCCESS; return EFI_SUCCESS;

60
UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
View File

@@ -63,8 +63,8 @@ MpInitLibInitialize (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibGetNumberOfProcessors ( MpInitLibGetNumberOfProcessors (
OUT UINTN *NumberOfProcessors OPTIONAL, OUT UINTN *NumberOfProcessors OPTIONAL,
OUT UINTN *NumberOfEnabledProcessors OPTIONAL OUT UINTN *NumberOfEnabledProcessors OPTIONAL
) )
{ {
*NumberOfProcessors = 1; *NumberOfProcessors = 1;
@@ -103,13 +103,15 @@ MpInitLibGetProcessorInfo (
if (ProcessorInfoBuffer == NULL) { if (ProcessorInfoBuffer == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (ProcessorNumber != 0) { if (ProcessorNumber != 0) {
return EFI_NOT_FOUND; return EFI_NOT_FOUND;
} }
ProcessorInfoBuffer->ProcessorId = 0;
ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT | ProcessorInfoBuffer->ProcessorId = 0;
PROCESSOR_ENABLED_BIT | ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT |
PROCESSOR_HEALTH_STATUS_BIT; PROCESSOR_ENABLED_BIT |
PROCESSOR_HEALTH_STATUS_BIT;
ProcessorInfoBuffer->Location.Package = 0; ProcessorInfoBuffer->Location.Package = 0;
ProcessorInfoBuffer->Location.Core = 0; ProcessorInfoBuffer->Location.Core = 0;
ProcessorInfoBuffer->Location.Thread = 0; ProcessorInfoBuffer->Location.Thread = 0;
@@ -117,12 +119,13 @@ MpInitLibGetProcessorInfo (
GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid); GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
if (GuidHob != NULL) { if (GuidHob != NULL) {
SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob); SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob);
HealthData->Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32; HealthData->Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32;
} else { } else {
DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n")); DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n"));
HealthData->Uint32 = 0; HealthData->Uint32 = 0;
} }
} }
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -204,12 +207,12 @@ MpInitLibGetProcessorInfo (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupAllAPs ( MpInitLibStartupAllAPs (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN BOOLEAN SingleThread, IN BOOLEAN SingleThread,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT UINTN **FailedCpuList OPTIONAL OUT UINTN **FailedCpuList OPTIONAL
) )
{ {
return EFI_NOT_STARTED; return EFI_NOT_STARTED;
@@ -289,12 +292,12 @@ MpInitLibStartupAllAPs (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupThisAP ( MpInitLibStartupThisAP (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN EFI_EVENT WaitEvent OPTIONAL, IN EFI_EVENT WaitEvent OPTIONAL,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL, IN VOID *ProcedureArgument OPTIONAL,
OUT BOOLEAN *Finished OPTIONAL OUT BOOLEAN *Finished OPTIONAL
) )
{ {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
@@ -329,8 +332,8 @@ MpInitLibStartupThisAP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibSwitchBSP ( MpInitLibSwitchBSP (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableOldBSP IN BOOLEAN EnableOldBSP
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@@ -369,9 +372,9 @@ MpInitLibSwitchBSP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibEnableDisableAP ( MpInitLibEnableDisableAP (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
IN BOOLEAN EnableAP, IN BOOLEAN EnableAP,
IN UINT32 *HealthFlag OPTIONAL IN UINT32 *HealthFlag OPTIONAL
) )
{ {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
@@ -396,12 +399,13 @@ MpInitLibEnableDisableAP (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibWhoAmI ( MpInitLibWhoAmI (
OUT UINTN *ProcessorNumber OUT UINTN *ProcessorNumber
) )
{ {
if (ProcessorNumber == NULL) { if (ProcessorNumber == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
*ProcessorNumber = 0; *ProcessorNumber = 0;
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@@ -427,9 +431,9 @@ MpInitLibWhoAmI (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
MpInitLibStartupAllCPUs ( MpInitLibStartupAllCPUs (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN UINTN TimeoutInMicroseconds, IN UINTN TimeoutInMicroseconds,
IN VOID *ProcedureArgument OPTIONAL IN VOID *ProcedureArgument OPTIONAL
) )
{ {
if (Procedure == NULL) { if (Procedure == NULL) {

1233
UefiCpuPkg/Library/MtrrLib/MtrrLib.c
View File

File diff suppressed because it is too large Load Diff

433
UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
View File

@@ -8,11 +8,11 @@
#include "MtrrLibUnitTest.h" #include "MtrrLibUnitTest.h"
STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = { STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = {
42, TRUE, TRUE, CacheUncacheable, 12 42, TRUE, TRUE, CacheUncacheable, 12
}; };
STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = { STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = {
{ 38, TRUE, TRUE, CacheUncacheable, 12 }, { 38, TRUE, TRUE, CacheUncacheable, 12 },
{ 38, TRUE, TRUE, CacheWriteBack, 12 }, { 38, TRUE, TRUE, CacheWriteBack, 12 },
{ 38, TRUE, TRUE, CacheWriteThrough, 12 }, { 38, TRUE, TRUE, CacheWriteThrough, 12 },
@@ -32,7 +32,7 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = {
{ 48, TRUE, TRUE, CacheWriteCombining, 12 }, { 48, TRUE, TRUE, CacheWriteCombining, 12 },
}; };
UINT32 mFixedMtrrsIndex[] = { UINT32 mFixedMtrrsIndex[] = {
MSR_IA32_MTRR_FIX64K_00000, MSR_IA32_MTRR_FIX64K_00000,
MSR_IA32_MTRR_FIX16K_80000, MSR_IA32_MTRR_FIX16K_80000,
MSR_IA32_MTRR_FIX16K_A0000, MSR_IA32_MTRR_FIX16K_A0000,
@@ -54,18 +54,18 @@ STATIC_ASSERT (
// Context structure to be used for most of the test cases. // Context structure to be used for most of the test cases.
// //
typedef struct { typedef struct {
CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
} MTRR_LIB_TEST_CONTEXT; } MTRR_LIB_TEST_CONTEXT;
// //
// Context structure to be used for GetFirmwareVariableMtrrCount() test. // Context structure to be used for GetFirmwareVariableMtrrCount() test.
// //
typedef struct { typedef struct {
UINT32 NumberOfReservedVariableMtrrs; UINT32 NumberOfReservedVariableMtrrs;
CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
} MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT; } MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT;
STATIC CHAR8 *mCacheDescription[] = { "UC", "WC", "N/A", "N/A", "WT", "WP", "WB" }; STATIC CHAR8 *mCacheDescription[] = { "UC", "WC", "N/A", "N/A", "WT", "WP", "WB" };
/** /**
Compare the actual memory ranges against expected memory ranges and return PASS when they match. Compare the actual memory ranges against expected memory ranges and return PASS when they match.
@@ -87,6 +87,7 @@ VerifyMemoryRanges (
) )
{ {
UINTN Index; UINTN Index;
UT_ASSERT_EQUAL (ExpectedMemoryRangeCount, ActualRangeCount); UT_ASSERT_EQUAL (ExpectedMemoryRangeCount, ActualRangeCount);
for (Index = 0; Index < ExpectedMemoryRangeCount; Index++) { for (Index = 0; Index < ExpectedMemoryRangeCount; Index++) {
UT_ASSERT_EQUAL (ExpectedMemoryRanges[Index].BaseAddress, ActualRanges[Index].BaseAddress); UT_ASSERT_EQUAL (ExpectedMemoryRanges[Index].BaseAddress, ActualRanges[Index].BaseAddress);
@@ -105,11 +106,12 @@ VerifyMemoryRanges (
**/ **/
VOID VOID
DumpMemoryRanges ( DumpMemoryRanges (
MTRR_MEMORY_RANGE *Ranges, MTRR_MEMORY_RANGE *Ranges,
UINTN RangeCount UINTN RangeCount
) )
{ {
UINTN Index; UINTN Index;
for (Index = 0; Index < RangeCount; Index++) { for (Index = 0; Index < RangeCount; Index++) {
UT_LOG_INFO ("\t{ 0x%016llx, 0x%016llx, %a },\n", Ranges[Index].BaseAddress, Ranges[Index].Length, mCacheDescription[Ranges[Index].Type]); UT_LOG_INFO ("\t{ 0x%016llx, 0x%016llx, %a },\n", Ranges[Index].BaseAddress, Ranges[Index].Length, mCacheDescription[Ranges[Index].Type]);
} }
@@ -130,17 +132,17 @@ DumpMemoryRanges (
**/ **/
VOID VOID
GenerateRandomMemoryTypeCombination ( GenerateRandomMemoryTypeCombination (
IN UINT32 TotalCount, IN UINT32 TotalCount,
OUT UINT32 *UcCount, OUT UINT32 *UcCount,
OUT UINT32 *WtCount, OUT UINT32 *WtCount,
OUT UINT32 *WbCount, OUT UINT32 *WbCount,
OUT UINT32 *WpCount, OUT UINT32 *WpCount,
OUT UINT32 *WcCount OUT UINT32 *WcCount
) )
{ {
UINTN Index; UINTN Index;
UINT32 TotalMtrrCount; UINT32 TotalMtrrCount;
UINT32 *CountPerType[5]; UINT32 *CountPerType[5];
CountPerType[0] = UcCount; CountPerType[0] = UcCount;
CountPerType[1] = WtCount; CountPerType[1] = WtCount;
@@ -183,38 +185,47 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
RETURN_STATUS Status; RETURN_STATUS Status;
UINT32 UcCount; UINT32 UcCount;
UINT32 WtCount; UINT32 WtCount;
UINT32 WbCount; UINT32 WbCount;
UINT32 WpCount; UINT32 WpCount;
UINT32 WcCount; UINT32 WcCount;
UINT32 MtrrIndex; UINT32 MtrrIndex;
UINT8 *Scratch; UINT8 *Scratch;
UINTN ScratchSize; UINTN ScratchSize;
MTRR_SETTINGS LocalMtrrs; MTRR_SETTINGS LocalMtrrs;
MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR]; MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];
MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
UINT32 ExpectedVariableMtrrUsage; UINT32 ExpectedVariableMtrrUsage;
UINTN ExpectedMemoryRangesCount; UINTN ExpectedMemoryRangesCount;
MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
UINT32 ActualVariableMtrrUsage; UINT32 ActualVariableMtrrUsage;
UINTN ActualMemoryRangesCount; UINTN ActualMemoryRangesCount;
MTRR_SETTINGS *Mtrrs[2]; MTRR_SETTINGS *Mtrrs[2];
SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
GenerateRandomMemoryTypeCombination ( GenerateRandomMemoryTypeCombination (
SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs), SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),
&UcCount, &WtCount, &WbCount, &WpCount, &WcCount &UcCount,
&WtCount,
&WbCount,
&WpCount,
&WcCount
); );
GenerateValidAndConfigurableMtrrPairs ( GenerateValidAndConfigurableMtrrPairs (
SystemParameter->PhysicalAddressBits, RawMtrrRange, SystemParameter->PhysicalAddressBits,
UcCount, WtCount, WbCount, WpCount, WcCount RawMtrrRange,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
); );
ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount; ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;
@@ -222,13 +233,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
GetEffectiveMemoryRanges ( GetEffectiveMemoryRanges (
SystemParameter->DefaultCacheType, SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits, SystemParameter->PhysicalAddressBits,
RawMtrrRange, ExpectedVariableMtrrUsage, RawMtrrRange,
ExpectedMemoryRanges, &ExpectedMemoryRangesCount ExpectedVariableMtrrUsage,
ExpectedMemoryRanges,
&ExpectedMemoryRangesCount
); );
UT_LOG_INFO ( UT_LOG_INFO (
"Total MTRR [%d]: UC=%d, WT=%d, WB=%d, WP=%d, WC=%d\n", "Total MTRR [%d]: UC=%d, WT=%d, WB=%d, WP=%d, WC=%d\n",
ExpectedVariableMtrrUsage, UcCount, WtCount, WbCount, WpCount, WcCount ExpectedVariableMtrrUsage,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
); );
UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount); UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);
DumpMemoryRanges (ExpectedMemoryRanges, ExpectedMemoryRangesCount); DumpMemoryRanges (ExpectedMemoryRanges, ExpectedMemoryRangesCount);
@@ -244,21 +262,28 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
for (MtrrIndex = 0; MtrrIndex < ARRAY_SIZE (Mtrrs); MtrrIndex++) { for (MtrrIndex = 0; MtrrIndex < ARRAY_SIZE (Mtrrs); MtrrIndex++) {
Scratch = calloc (ScratchSize, sizeof (UINT8)); Scratch = calloc (ScratchSize, sizeof (UINT8));
Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount); Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);
if (Status == RETURN_BUFFER_TOO_SMALL) { if (Status == RETURN_BUFFER_TOO_SMALL) {
Scratch = realloc (Scratch, ScratchSize); Scratch = realloc (Scratch, ScratchSize);
Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount); Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);
} }
UT_ASSERT_STATUS_EQUAL (Status, RETURN_SUCCESS); UT_ASSERT_STATUS_EQUAL (Status, RETURN_SUCCESS);
if (Mtrrs[MtrrIndex] == NULL) { if (Mtrrs[MtrrIndex] == NULL) {
ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs)); ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));
MtrrGetAllMtrrs (&LocalMtrrs); MtrrGetAllMtrrs (&LocalMtrrs);
} }
ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges); ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
CollectTestResult ( CollectTestResult (
SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount, SystemParameter->DefaultCacheType,
&LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage SystemParameter->PhysicalAddressBits,
SystemParameter->VariableMtrrCount,
&LocalMtrrs,
ActualMemoryRanges,
&ActualMemoryRangesCount,
&ActualVariableMtrrUsage
); );
UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount); UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);
@@ -284,20 +309,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
UNIT_TEST_STATUS UNIT_TEST_STATUS
EFIAPI EFIAPI
UnitTestInvalidMemoryLayouts ( UnitTestInvalidMemoryLayouts (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 1]; MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 1];
UINTN RangeCount; UINTN RangeCount;
UINT64 MaxAddress; UINT64 MaxAddress;
UINT32 Index; UINT32 Index;
UINT64 BaseAddress; UINT64 BaseAddress;
UINT64 Length; UINT64 Length;
RETURN_STATUS Status; RETURN_STATUS Status;
UINTN ScratchSize; UINTN ScratchSize;
SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
RangeCount = Random32 (1, ARRAY_SIZE (Ranges)); RangeCount = Random32 (1, ARRAY_SIZE (Ranges));
MaxAddress = 1ull << SystemParameter->PhysicalAddressBits; MaxAddress = 1ull << SystemParameter->PhysicalAddressBits;
@@ -313,13 +338,15 @@ UnitTestInvalidMemoryLayouts (
Ranges[Index].Type = GenerateRandomCacheType (); Ranges[Index].Type = GenerateRandomCacheType ();
Status = MtrrSetMemoryAttribute ( Status = MtrrSetMemoryAttribute (
Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type Ranges[Index].BaseAddress,
); Ranges[Index].Length,
Ranges[Index].Type
);
UT_ASSERT_TRUE (RETURN_ERROR (Status)); UT_ASSERT_TRUE (RETURN_ERROR (Status));
} }
ScratchSize = 0; ScratchSize = 0;
Status = MtrrSetMemoryAttributesInMtrrSettings (NULL, NULL, &ScratchSize, Ranges, RangeCount); Status = MtrrSetMemoryAttributesInMtrrSettings (NULL, NULL, &ScratchSize, Ranges, RangeCount);
UT_ASSERT_TRUE (RETURN_ERROR (Status)); UT_ASSERT_TRUE (RETURN_ERROR (Status));
return UNIT_TEST_PASSED; return UNIT_TEST_PASSED;
@@ -344,7 +371,7 @@ UnitTestIsMtrrSupported (
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
// //
@@ -357,8 +384,8 @@ UnitTestIsMtrrSupported (
// //
// MTRR capability on in CPUID leaf, but no variable or fixed MTRRs. // MTRR capability on in CPUID leaf, but no variable or fixed MTRRs.
// //
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = 0; SystemParameter.VariableMtrrCount = 0;
SystemParameter.FixedMtrrSupported = FALSE; SystemParameter.FixedMtrrSupported = FALSE;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_ASSERT_FALSE (IsMtrrSupported ()); UT_ASSERT_FALSE (IsMtrrSupported ());
@@ -366,8 +393,8 @@ UnitTestIsMtrrSupported (
// //
// MTRR capability on in CPUID leaf, but no variable MTRRs. // MTRR capability on in CPUID leaf, but no variable MTRRs.
// //
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = 0; SystemParameter.VariableMtrrCount = 0;
SystemParameter.FixedMtrrSupported = TRUE; SystemParameter.FixedMtrrSupported = TRUE;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_ASSERT_FALSE (IsMtrrSupported ()); UT_ASSERT_FALSE (IsMtrrSupported ());
@@ -375,8 +402,8 @@ UnitTestIsMtrrSupported (
// //
// MTRR capability on in CPUID leaf, but no fixed MTRRs. // MTRR capability on in CPUID leaf, but no fixed MTRRs.
// //
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = 7; SystemParameter.VariableMtrrCount = 7;
SystemParameter.FixedMtrrSupported = FALSE; SystemParameter.FixedMtrrSupported = FALSE;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_ASSERT_FALSE (IsMtrrSupported ()); UT_ASSERT_FALSE (IsMtrrSupported ());
@@ -384,8 +411,8 @@ UnitTestIsMtrrSupported (
// //
// MTRR capability on in CPUID leaf with both variable and fixed MTRRs. // MTRR capability on in CPUID leaf with both variable and fixed MTRRs.
// //
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = 7; SystemParameter.VariableMtrrCount = 7;
SystemParameter.FixedMtrrSupported = TRUE; SystemParameter.FixedMtrrSupported = TRUE;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_ASSERT_TRUE (IsMtrrSupported ()); UT_ASSERT_TRUE (IsMtrrSupported ());
@@ -409,11 +436,11 @@ UnitTestGetVariableMtrrCount (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
UINT32 Result; UINT32 Result;
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
// //
@@ -445,7 +472,7 @@ UnitTestGetVariableMtrrCount (
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL); UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL);
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = MAX_UINT8; SystemParameter.VariableMtrrCount = MAX_UINT8;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL); UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL);
@@ -469,12 +496,12 @@ UnitTestGetFirmwareVariableMtrrCount (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
UINT32 Result; UINT32 Result;
UINT32 ReservedMtrrs; UINT32 ReservedMtrrs;
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
@@ -516,7 +543,7 @@ UnitTestGetFirmwareVariableMtrrCount (
// //
// Negative test case when Fixed MTRRs are not supported // Negative test case when Fixed MTRRs are not supported
// //
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.FixedMtrrSupported = FALSE; SystemParameter.FixedMtrrSupported = FALSE;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, 2); PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, 2);
@@ -527,7 +554,7 @@ UnitTestGetFirmwareVariableMtrrCount (
// Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR
// //
SystemParameter.FixedMtrrSupported = TRUE; SystemParameter.FixedMtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1; SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (GetFirmwareVariableMtrrCount (), NULL); UT_EXPECT_ASSERT_FAILURE (GetFirmwareVariableMtrrCount (), NULL);
@@ -569,17 +596,17 @@ UnitTestMtrrGetFixedMtrr (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
MTRR_FIXED_SETTINGS *Result; MTRR_FIXED_SETTINGS *Result;
MTRR_FIXED_SETTINGS ExpectedFixedSettings; MTRR_FIXED_SETTINGS ExpectedFixedSettings;
MTRR_FIXED_SETTINGS FixedSettings; MTRR_FIXED_SETTINGS FixedSettings;
UINTN Index; UINTN Index;
UINTN MsrIndex; UINTN MsrIndex;
UINTN ByteIndex; UINTN ByteIndex;
UINT64 MsrValue; UINT64 MsrValue;
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
@@ -594,6 +621,7 @@ UnitTestMtrrGetFixedMtrr (
for (ByteIndex = 0; ByteIndex < sizeof (UINT64); ByteIndex++) { for (ByteIndex = 0; ByteIndex < sizeof (UINT64); ByteIndex++) {
MsrValue = MsrValue | LShiftU64 (GenerateRandomCacheType (), ByteIndex * 8); MsrValue = MsrValue | LShiftU64 (GenerateRandomCacheType (), ByteIndex * 8);
} }
ExpectedFixedSettings.Mtrr[MsrIndex] = MsrValue; ExpectedFixedSettings.Mtrr[MsrIndex] = MsrValue;
AsmWriteMsr64 (mFixedMtrrsIndex[MsrIndex], MsrValue); AsmWriteMsr64 (mFixedMtrrsIndex[MsrIndex], MsrValue);
} }
@@ -631,18 +659,18 @@ UnitTestMtrrGetFixedMtrr (
UNIT_TEST_STATUS UNIT_TEST_STATUS
EFIAPI EFIAPI
UnitTestMtrrGetAllMtrrs ( UnitTestMtrrGetAllMtrrs (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
MTRR_SETTINGS *Result; MTRR_SETTINGS *Result;
MTRR_SETTINGS Mtrrs; MTRR_SETTINGS Mtrrs;
MTRR_SETTINGS ExpectedMtrrs; MTRR_SETTINGS ExpectedMtrrs;
MTRR_VARIABLE_SETTING VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; MTRR_VARIABLE_SETTING VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
UINT32 Index; UINT32 Index;
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
@@ -652,6 +680,7 @@ UnitTestMtrrGetAllMtrrs (
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableMtrr[Index].Base); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableMtrr[Index].Base);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableMtrr[Index].Mask); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableMtrr[Index].Mask);
} }
Result = MtrrGetAllMtrrs (&Mtrrs); Result = MtrrGetAllMtrrs (&Mtrrs);
UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs); UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);
UT_ASSERT_MEM_EQUAL (Mtrrs.Variables.Mtrr, VariableMtrr, sizeof (MTRR_VARIABLE_SETTING) * SystemParameter.VariableMtrrCount); UT_ASSERT_MEM_EQUAL (Mtrrs.Variables.Mtrr, VariableMtrr, sizeof (MTRR_VARIABLE_SETTING) * SystemParameter.VariableMtrrCount);
@@ -671,7 +700,7 @@ UnitTestMtrrGetAllMtrrs (
// //
// Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR
// //
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1; SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (MtrrGetAllMtrrs (&Mtrrs), NULL); UT_EXPECT_ASSERT_FAILURE (MtrrGetAllMtrrs (&Mtrrs), NULL);
@@ -695,21 +724,21 @@ UnitTestMtrrSetAllMtrrs (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
MTRR_SETTINGS *Result; MTRR_SETTINGS *Result;
MTRR_SETTINGS Mtrrs; MTRR_SETTINGS Mtrrs;
UINT32 Index; UINT32 Index;
MSR_IA32_MTRR_DEF_TYPE_REGISTER Default; MSR_IA32_MTRR_DEF_TYPE_REGISTER Default;
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
Default.Uint64 = 0; Default.Uint64 = 0;
Default.Bits.E = 1; Default.Bits.E = 1;
Default.Bits.FE = 1; Default.Bits.FE = 1;
Default.Bits.Type = GenerateRandomCacheType (); Default.Bits.Type = GenerateRandomCacheType ();
ZeroMem (&Mtrrs, sizeof (Mtrrs)); ZeroMem (&Mtrrs, sizeof (Mtrrs));
@@ -717,6 +746,7 @@ UnitTestMtrrSetAllMtrrs (
for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) { for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {
GenerateRandomMtrrPair (SystemParameter.PhysicalAddressBits, GenerateRandomCacheType (), &Mtrrs.Variables.Mtrr[Index], NULL); GenerateRandomMtrrPair (SystemParameter.PhysicalAddressBits, GenerateRandomCacheType (), &Mtrrs.Variables.Mtrr[Index], NULL);
} }
Result = MtrrSetAllMtrrs (&Mtrrs); Result = MtrrSetAllMtrrs (&Mtrrs);
UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs); UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);
@@ -745,18 +775,18 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
UINT32 Result; UINT32 Result;
MTRR_VARIABLE_SETTING VariableSetting[MTRR_NUMBER_OF_VARIABLE_MTRR]; MTRR_VARIABLE_SETTING VariableSetting[MTRR_NUMBER_OF_VARIABLE_MTRR];
VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR]; VARIABLE_MTRR VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];
UINT64 ValidMtrrBitsMask; UINT64 ValidMtrrBitsMask;
UINT64 ValidMtrrAddressMask; UINT64 ValidMtrrAddressMask;
UINT32 Index; UINT32 Index;
MSR_IA32_MTRR_PHYSBASE_REGISTER Base; MSR_IA32_MTRR_PHYSBASE_REGISTER Base;
MSR_IA32_MTRR_PHYSMASK_REGISTER Mask; MSR_IA32_MTRR_PHYSMASK_REGISTER Mask;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
@@ -770,16 +800,17 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting[Index].Base); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting[Index].Base);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting[Index].Mask); AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting[Index].Mask);
} }
Result = MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr); Result = MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr);
UT_ASSERT_EQUAL (Result, SystemParameter.VariableMtrrCount); UT_ASSERT_EQUAL (Result, SystemParameter.VariableMtrrCount);
for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) { for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {
Base.Uint64 = VariableMtrr[Index].BaseAddress; Base.Uint64 = VariableMtrr[Index].BaseAddress;
Base.Bits.Type = (UINT32) VariableMtrr[Index].Type; Base.Bits.Type = (UINT32)VariableMtrr[Index].Type;
UT_ASSERT_EQUAL (Base.Uint64, VariableSetting[Index].Base); UT_ASSERT_EQUAL (Base.Uint64, VariableSetting[Index].Base);
Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask; Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask;
Mask.Bits.V = 1; Mask.Bits.V = 1;
UT_ASSERT_EQUAL (Mask.Uint64, VariableSetting[Index].Mask); UT_ASSERT_EQUAL (Mask.Uint64, VariableSetting[Index].Mask);
} }
@@ -794,7 +825,7 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
// //
// Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR
// //
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1; SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
UT_EXPECT_ASSERT_FAILURE (MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr), NULL); UT_EXPECT_ASSERT_FAILURE (MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr), NULL);
@@ -837,11 +868,11 @@ UnitTestMtrrGetDefaultMemoryType (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
MTRR_LIB_TEST_CONTEXT *LocalContext; MTRR_LIB_TEST_CONTEXT *LocalContext;
UINTN Index; UINTN Index;
MTRR_MEMORY_CACHE_TYPE Result; MTRR_MEMORY_CACHE_TYPE Result;
MTRR_LIB_SYSTEM_PARAMETER SystemParameter; MTRR_LIB_SYSTEM_PARAMETER SystemParameter;
MTRR_MEMORY_CACHE_TYPE CacheType[5]; MTRR_MEMORY_CACHE_TYPE CacheType[5];
CacheType[0] = CacheUncacheable; CacheType[0] = CacheUncacheable;
CacheType[1] = CacheWriteCombining; CacheType[1] = CacheWriteCombining;
@@ -849,7 +880,7 @@ UnitTestMtrrGetDefaultMemoryType (
CacheType[3] = CacheWriteProtected; CacheType[3] = CacheWriteProtected;
CacheType[4] = CacheWriteBack; CacheType[4] = CacheWriteBack;
LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context; LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;
CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter)); CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));
// //
@@ -871,15 +902,15 @@ UnitTestMtrrGetDefaultMemoryType (
Result = MtrrGetDefaultMemoryType (); Result = MtrrGetDefaultMemoryType ();
UT_ASSERT_EQUAL (Result, CacheUncacheable); UT_ASSERT_EQUAL (Result, CacheUncacheable);
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.FixedMtrrSupported = FALSE; SystemParameter.FixedMtrrSupported = FALSE;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
Result = MtrrGetDefaultMemoryType (); Result = MtrrGetDefaultMemoryType ();
UT_ASSERT_EQUAL (Result, CacheUncacheable); UT_ASSERT_EQUAL (Result, CacheUncacheable);
SystemParameter.MtrrSupported = TRUE; SystemParameter.MtrrSupported = TRUE;
SystemParameter.FixedMtrrSupported = TRUE; SystemParameter.FixedMtrrSupported = TRUE;
SystemParameter.VariableMtrrCount = 0; SystemParameter.VariableMtrrCount = 0;
InitializeMtrrRegs (&SystemParameter); InitializeMtrrRegs (&SystemParameter);
Result = MtrrGetDefaultMemoryType (); Result = MtrrGetDefaultMemoryType ();
UT_ASSERT_EQUAL (Result, CacheUncacheable); UT_ASSERT_EQUAL (Result, CacheUncacheable);
@@ -903,37 +934,46 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter; CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;
RETURN_STATUS Status; RETURN_STATUS Status;
UINT32 UcCount; UINT32 UcCount;
UINT32 WtCount; UINT32 WtCount;
UINT32 WbCount; UINT32 WbCount;
UINT32 WpCount; UINT32 WpCount;
UINT32 WcCount; UINT32 WcCount;
UINTN MtrrIndex; UINTN MtrrIndex;
UINTN Index; UINTN Index;
MTRR_SETTINGS LocalMtrrs; MTRR_SETTINGS LocalMtrrs;
MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR]; MTRR_MEMORY_RANGE RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];
MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; MTRR_MEMORY_RANGE ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
UINT32 ExpectedVariableMtrrUsage; UINT32 ExpectedVariableMtrrUsage;
UINTN ExpectedMemoryRangesCount; UINTN ExpectedMemoryRangesCount;
MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1]; MTRR_MEMORY_RANGE ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];
UINT32 ActualVariableMtrrUsage; UINT32 ActualVariableMtrrUsage;
UINTN ActualMemoryRangesCount; UINTN ActualMemoryRangesCount;
MTRR_SETTINGS *Mtrrs[2]; MTRR_SETTINGS *Mtrrs[2];
SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context; SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
GenerateRandomMemoryTypeCombination ( GenerateRandomMemoryTypeCombination (
SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs), SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),
&UcCount, &WtCount, &WbCount, &WpCount, &WcCount &UcCount,
&WtCount,
&WbCount,
&WpCount,
&WcCount
); );
GenerateValidAndConfigurableMtrrPairs ( GenerateValidAndConfigurableMtrrPairs (
SystemParameter->PhysicalAddressBits, RawMtrrRange, SystemParameter->PhysicalAddressBits,
UcCount, WtCount, WbCount, WpCount, WcCount RawMtrrRange,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
); );
ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount; ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;
@@ -941,8 +981,10 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
GetEffectiveMemoryRanges ( GetEffectiveMemoryRanges (
SystemParameter->DefaultCacheType, SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits, SystemParameter->PhysicalAddressBits,
RawMtrrRange, ExpectedVariableMtrrUsage, RawMtrrRange,
ExpectedMemoryRanges, &ExpectedMemoryRangesCount ExpectedVariableMtrrUsage,
ExpectedMemoryRanges,
&ExpectedMemoryRangesCount
); );
UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount); UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);
@@ -964,7 +1006,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
ExpectedMemoryRanges[Index].Type ExpectedMemoryRanges[Index].Type
); );
UT_ASSERT_TRUE (Status == RETURN_SUCCESS || Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL); UT_ASSERT_TRUE (Status == RETURN_SUCCESS || Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL);
if (Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL) { if ((Status == RETURN_OUT_OF_RESOURCES) || (Status == RETURN_BUFFER_TOO_SMALL)) {
return UNIT_TEST_SKIPPED; return UNIT_TEST_SKIPPED;
} }
} }
@@ -973,10 +1015,16 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs)); ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));
MtrrGetAllMtrrs (&LocalMtrrs); MtrrGetAllMtrrs (&LocalMtrrs);
} }
ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges); ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
CollectTestResult ( CollectTestResult (
SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount, SystemParameter->DefaultCacheType,
&LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage SystemParameter->PhysicalAddressBits,
SystemParameter->VariableMtrrCount,
&LocalMtrrs,
ActualMemoryRanges,
&ActualMemoryRangesCount,
&ActualVariableMtrrUsage
); );
UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount); UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);
DumpMemoryRanges (ActualMemoryRanges, ActualMemoryRangesCount); DumpMemoryRanges (ActualMemoryRanges, ActualMemoryRangesCount);
@@ -989,7 +1037,6 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
return UNIT_TEST_PASSED; return UNIT_TEST_PASSED;
} }
/** /**
Prep routine for UnitTestGetFirmwareVariableMtrrCount(). Prep routine for UnitTestGetFirmwareVariableMtrrCount().
@@ -1003,7 +1050,7 @@ SavePcdValue (
{ {
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
LocalContext->NumberOfReservedVariableMtrrs = PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs); LocalContext->NumberOfReservedVariableMtrrs = PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);
return UNIT_TEST_PASSED; return UNIT_TEST_PASSED;
} }
@@ -1021,7 +1068,7 @@ RestorePcdValue (
{ {
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext; MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;
LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context; LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;
PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, LocalContext->NumberOfReservedVariableMtrrs); PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, LocalContext->NumberOfReservedVariableMtrrs);
} }
@@ -1040,20 +1087,20 @@ STATIC
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
UnitTestingEntry ( UnitTestingEntry (
UINTN Iteration UINTN Iteration
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UNIT_TEST_FRAMEWORK_HANDLE Framework; UNIT_TEST_FRAMEWORK_HANDLE Framework;
UNIT_TEST_SUITE_HANDLE MtrrApiTests; UNIT_TEST_SUITE_HANDLE MtrrApiTests;
UINTN Index; UINTN Index;
UINTN SystemIndex; UINTN SystemIndex;
MTRR_LIB_TEST_CONTEXT Context; MTRR_LIB_TEST_CONTEXT Context;
MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT GetFirmwareVariableMtrrCountContext; MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT GetFirmwareVariableMtrrCountContext;
Context.SystemParameter = &mDefaultSystemParameter; Context.SystemParameter = &mDefaultSystemParameter;
GetFirmwareVariableMtrrCountContext.SystemParameter = &mDefaultSystemParameter; GetFirmwareVariableMtrrCountContext.SystemParameter = &mDefaultSystemParameter;
Framework = NULL; Framework = NULL;
// //
// Setup the test framework for running the tests. // Setup the test framework for running the tests.
@@ -1077,24 +1124,26 @@ UnitTestingEntry (
Status = EFI_OUT_OF_RESOURCES; Status = EFI_OUT_OF_RESOURCES;
goto EXIT; goto EXIT;
} }
AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext); AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttribute", "MtrrGetMemoryAttribute", UnitTestMtrrGetMemoryAttribute, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext);
AddTestCase (MtrrApiTests, "Test MtrrGetFixedMtrr", "MtrrGetFixedMtrr", UnitTestMtrrGetFixedMtrr, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttribute", "MtrrGetMemoryAttribute", UnitTestMtrrGetMemoryAttribute, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test MtrrGetAllMtrrs", "MtrrGetAllMtrrs", UnitTestMtrrGetAllMtrrs, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test MtrrGetFixedMtrr", "MtrrGetFixedMtrr", UnitTestMtrrGetFixedMtrr, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test MtrrSetAllMtrrs", "MtrrSetAllMtrrs", UnitTestMtrrSetAllMtrrs, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test MtrrGetAllMtrrs", "MtrrGetAllMtrrs", UnitTestMtrrGetAllMtrrs, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test MtrrSetAllMtrrs", "MtrrSetAllMtrrs", UnitTestMtrrSetAllMtrrs, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttributeInVariableMtrr", "MtrrGetMemoryAttributeInVariableMtrr", UnitTestMtrrGetMemoryAttributeInVariableMtrr, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttributeInVariableMtrr", "MtrrGetMemoryAttributeInVariableMtrr", UnitTestMtrrGetMemoryAttributeInVariableMtrr, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test MtrrDebugPrintAllMtrrs", "MtrrDebugPrintAllMtrrs", UnitTestMtrrDebugPrintAllMtrrs, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test MtrrDebugPrintAllMtrrs", "MtrrDebugPrintAllMtrrs", UnitTestMtrrDebugPrintAllMtrrs, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test MtrrGetDefaultMemoryType", "MtrrGetDefaultMemoryType", UnitTestMtrrGetDefaultMemoryType, NULL, NULL, &Context); AddTestCase (MtrrApiTests, "Test MtrrGetDefaultMemoryType", "MtrrGetDefaultMemoryType", UnitTestMtrrGetDefaultMemoryType, NULL, NULL, &Context);
for (SystemIndex = 0; SystemIndex < ARRAY_SIZE (mSystemParameters); SystemIndex++) { for (SystemIndex = 0; SystemIndex < ARRAY_SIZE (mSystemParameters); SystemIndex++) {
for (Index = 0; Index < Iteration; Index++) { for (Index = 0; Index < Iteration; Index++) {
AddTestCase (MtrrApiTests, "Test InvalidMemoryLayouts", "InvalidMemoryLayouts", UnitTestInvalidMemoryLayouts, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); AddTestCase (MtrrApiTests, "Test InvalidMemoryLayouts", "InvalidMemoryLayouts", UnitTestInvalidMemoryLayouts, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributeInMtrrSettings", "MtrrSetMemoryAttributeInMtrrSettings", UnitTestMtrrSetMemoryAttributeInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributeInMtrrSettings", "MtrrSetMemoryAttributeInMtrrSettings", UnitTestMtrrSetMemoryAttributeInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributesInMtrrSettings", "MtrrSetMemoryAttributesInMtrrSettings", UnitTestMtrrSetMemoryAttributesInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]); AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributesInMtrrSettings", "MtrrSetMemoryAttributesInMtrrSettings", UnitTestMtrrSetMemoryAttributesInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
} }
} }
// //
// Execute the tests. // Execute the tests.
// //
@@ -1118,14 +1167,14 @@ EXIT:
**/ **/
INT32 INT32
main ( main (
INT32 Argc, INT32 Argc,
CHAR8 *Argv[] CHAR8 *Argv[]
) )
{ {
UINTN Count; UINTN Count;
DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, UNIT_TEST_APP_VERSION)); DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, UNIT_TEST_APP_VERSION));
srand ((unsigned int) time (NULL)); srand ((unsigned int)time (NULL));
// //
// MtrrLibUnitTest generate-random-numbers <path to MtrrLib/UnitTest/RandomNumber.c> <random-number count> // MtrrLibUnitTest generate-random-numbers <path to MtrrLib/UnitTest/RandomNumber.c> <random-number count>

75
UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
View File

@@ -29,21 +29,21 @@
#include <Register/Cpuid.h> #include <Register/Cpuid.h>
#include <Register/Msr.h> #include <Register/Msr.h>
#define UNIT_TEST_APP_NAME "MtrrLib Unit Tests" #define UNIT_TEST_APP_NAME "MtrrLib Unit Tests"
#define UNIT_TEST_APP_VERSION "1.0" #define UNIT_TEST_APP_VERSION "1.0"
#define SCRATCH_BUFFER_SIZE SIZE_16KB #define SCRATCH_BUFFER_SIZE SIZE_16KB
typedef struct { typedef struct {
UINT8 PhysicalAddressBits; UINT8 PhysicalAddressBits;
BOOLEAN MtrrSupported; BOOLEAN MtrrSupported;
BOOLEAN FixedMtrrSupported; BOOLEAN FixedMtrrSupported;
MTRR_MEMORY_CACHE_TYPE DefaultCacheType; MTRR_MEMORY_CACHE_TYPE DefaultCacheType;
UINT32 VariableMtrrCount; UINT32 VariableMtrrCount;
} MTRR_LIB_SYSTEM_PARAMETER; } MTRR_LIB_SYSTEM_PARAMETER;
extern UINT32 mFixedMtrrsIndex[]; extern UINT32 mFixedMtrrsIndex[];
extern BOOLEAN mRandomInput; extern BOOLEAN mRandomInput;
/** /**
Initialize the MTRR registers. Initialize the MTRR registers.
@@ -64,7 +64,7 @@ InitializeMtrrRegs (
UNIT_TEST_STATUS UNIT_TEST_STATUS
EFIAPI EFIAPI
InitializeSystem ( InitializeSystem (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
); );
/** /**
@@ -88,13 +88,13 @@ GenerateRandomCacheType (
**/ **/
VOID VOID
GenerateValidAndConfigurableMtrrPairs ( GenerateValidAndConfigurableMtrrPairs (
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges, IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges,
IN UINT32 UcCount, IN UINT32 UcCount,
IN UINT32 WtCount, IN UINT32 WtCount,
IN UINT32 WbCount, IN UINT32 WbCount,
IN UINT32 WpCount, IN UINT32 WpCount,
IN UINT32 WcCount IN UINT32 WcCount
); );
/** /**
@@ -109,12 +109,12 @@ GenerateValidAndConfigurableMtrrPairs (
**/ **/
VOID VOID
GetEffectiveMemoryRanges ( GetEffectiveMemoryRanges (
IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN MTRR_MEMORY_CACHE_TYPE DefaultType,
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN MTRR_MEMORY_RANGE *RawMemoryRanges, IN MTRR_MEMORY_RANGE *RawMemoryRanges,
IN UINT32 RawMemoryRangeCount, IN UINT32 RawMemoryRangeCount,
OUT MTRR_MEMORY_RANGE *MemoryRanges, OUT MTRR_MEMORY_RANGE *MemoryRanges,
OUT UINTN *MemoryRangeCount OUT UINTN *MemoryRangeCount
); );
/** /**
@@ -127,10 +127,10 @@ GetEffectiveMemoryRanges (
**/ **/
VOID VOID
GenerateRandomMtrrPair ( GenerateRandomMtrrPair (
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN MTRR_MEMORY_CACHE_TYPE CacheType, IN MTRR_MEMORY_CACHE_TYPE CacheType,
OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL, OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL,
OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL
); );
/** /**
@@ -146,13 +146,13 @@ GenerateRandomMtrrPair (
**/ **/
VOID VOID
CollectTestResult ( CollectTestResult (
IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN MTRR_MEMORY_CACHE_TYPE DefaultType,
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN UINT32 VariableMtrrCount, IN UINT32 VariableMtrrCount,
IN MTRR_SETTINGS *Mtrrs, IN MTRR_SETTINGS *Mtrrs,
OUT MTRR_MEMORY_RANGE *Ranges, OUT MTRR_MEMORY_RANGE *Ranges,
IN OUT UINTN *RangeCount, IN OUT UINTN *RangeCount,
OUT UINT32 *MtrrCount OUT UINT32 *MtrrCount
); );
/** /**
@@ -189,7 +189,8 @@ Random32 (
**/ **/
VOID VOID
GenerateRandomNumbers ( GenerateRandomNumbers (
CHAR8 *FilePath, CHAR8 *FilePath,
UINTN Count UINTN Count
); );
#endif #endif

9600
UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c
View File

File diff suppressed because it is too large Load Diff

430
UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
View File

@@ -8,9 +8,9 @@
#include "MtrrLibUnitTest.h" #include "MtrrLibUnitTest.h"
MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = { MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = {
CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProtected, CacheWriteBack CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProtected, CacheWriteBack
}; };
UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTRR]; UINT64 mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTRR];
MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VARIABLE_MTRR]; MSR_IA32_MTRR_PHYSBASE_REGISTER mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VARIABLE_MTRR];
@@ -20,10 +20,10 @@ MSR_IA32_MTRRCAP_REGISTER mMtrrCapMsr;
CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx; CPUID_VERSION_INFO_EDX mCpuidVersionInfoEdx;
CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax; CPUID_VIR_PHY_ADDRESS_SIZE_EAX mCpuidVirPhyAddressSizeEax;
BOOLEAN mRandomInput; BOOLEAN mRandomInput;
UINTN mNumberIndex = 0; UINTN mNumberIndex = 0;
extern UINTN mNumbers[]; extern UINTN mNumbers[];
extern UINTN mNumberCount; extern UINTN mNumberCount;
/** /**
Return a random number between 0 and RAND_MAX. Return a random number between 0 and RAND_MAX.
@@ -65,8 +65,8 @@ CHAR8 mContentTemplate[] = {
**/ **/
VOID VOID
GenerateRandomNumbers ( GenerateRandomNumbers (
CHAR8 *FilePath, CHAR8 *FilePath,
UINTN Count UINTN Count
) )
{ {
FILE *File; FILE *File;
@@ -78,8 +78,10 @@ GenerateRandomNumbers (
if (Index % 10 == 0) { if (Index % 10 == 0) {
fprintf (File, "\n "); fprintf (File, "\n ");
} }
fprintf (File, " %d,", rand ()); fprintf (File, " %d,", rand ());
} }
fprintf (File, "\n};\n"); fprintf (File, "\n};\n");
fclose (File); fclose (File);
} }
@@ -112,38 +114,41 @@ GenerateRandomNumbers (
UINT32 UINT32
EFIAPI EFIAPI
UnitTestMtrrLibAsmCpuid ( UnitTestMtrrLibAsmCpuid (
IN UINT32 Index, IN UINT32 Index,
OUT UINT32 *Eax OPTIONAL, OUT UINT32 *Eax OPTIONAL,
OUT UINT32 *Ebx OPTIONAL, OUT UINT32 *Ebx OPTIONAL,
OUT UINT32 *Ecx OPTIONAL, OUT UINT32 *Ecx OPTIONAL,
OUT UINT32 *Edx OPTIONAL OUT UINT32 *Edx OPTIONAL
) )
{ {
switch (Index) { switch (Index) {
case CPUID_VERSION_INFO: case CPUID_VERSION_INFO:
if (Edx != NULL) { if (Edx != NULL) {
*Edx = mCpuidVersionInfoEdx.Uint32; *Edx = mCpuidVersionInfoEdx.Uint32;
} }
return Index;
break; return Index;
case CPUID_EXTENDED_FUNCTION: break;
if (Eax != NULL) { case CPUID_EXTENDED_FUNCTION:
*Eax = CPUID_VIR_PHY_ADDRESS_SIZE; if (Eax != NULL) {
} *Eax = CPUID_VIR_PHY_ADDRESS_SIZE;
return Index; }
break;
case CPUID_VIR_PHY_ADDRESS_SIZE: return Index;
if (Eax != NULL) { break;
*Eax = mCpuidVirPhyAddressSizeEax.Uint32; case CPUID_VIR_PHY_ADDRESS_SIZE:
} if (Eax != NULL) {
return Index; *Eax = mCpuidVirPhyAddressSizeEax.Uint32;
break; }
return Index;
break;
} }
// //
// Should never fall through to here // Should never fall through to here
// //
ASSERT(FALSE); ASSERT (FALSE);
return Index; return Index;
} }
@@ -163,11 +168,11 @@ UnitTestMtrrLibAsmCpuid (
**/ **/
UINT64 UINT64
EFIAPI EFIAPI
UnitTestMtrrLibAsmReadMsr64( UnitTestMtrrLibAsmReadMsr64 (
IN UINT32 MsrIndex IN UINT32 MsrIndex
) )
{ {
UINT32 Index; UINT32 Index;
for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) { for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) {
if (MsrIndex == mFixedMtrrsIndex[Index]) { if (MsrIndex == mFixedMtrrsIndex[Index]) {
@@ -176,7 +181,8 @@ UnitTestMtrrLibAsmReadMsr64(
} }
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) && if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) { (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
{
if (MsrIndex % 2 == 0) { if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1; Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
return mVariableMtrrsPhysBase[Index].Uint64; return mVariableMtrrsPhysBase[Index].Uint64;
@@ -197,7 +203,7 @@ UnitTestMtrrLibAsmReadMsr64(
// //
// Should never fall through to here // Should never fall through to here
// //
ASSERT(FALSE); ASSERT (FALSE);
return 0; return 0;
} }
@@ -220,12 +226,12 @@ UnitTestMtrrLibAsmReadMsr64(
**/ **/
UINT64 UINT64
EFIAPI EFIAPI
UnitTestMtrrLibAsmWriteMsr64( UnitTestMtrrLibAsmWriteMsr64 (
IN UINT32 MsrIndex, IN UINT32 MsrIndex,
IN UINT64 Value IN UINT64 Value
) )
{ {
UINT32 Index; UINT32 Index;
for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) { for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) {
if (MsrIndex == mFixedMtrrsIndex[Index]) { if (MsrIndex == mFixedMtrrsIndex[Index]) {
@@ -235,13 +241,14 @@ UnitTestMtrrLibAsmWriteMsr64(
} }
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) && if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) { (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
{
if (MsrIndex % 2 == 0) { if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1; Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
mVariableMtrrsPhysBase[Index].Uint64 = Value; mVariableMtrrsPhysBase[Index].Uint64 = Value;
return Value; return Value;
} else { } else {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSMASK0) >> 1; Index = (MsrIndex - MSR_IA32_MTRR_PHYSMASK0) >> 1;
mVariableMtrrsPhysMask[Index].Uint64 = Value; mVariableMtrrsPhysMask[Index].Uint64 = Value;
return Value; return Value;
} }
@@ -260,7 +267,7 @@ UnitTestMtrrLibAsmWriteMsr64(
// //
// Should never fall through to here // Should never fall through to here
// //
ASSERT(FALSE); ASSERT (FALSE);
return 0; return 0;
} }
@@ -275,7 +282,7 @@ InitializeMtrrRegs (
IN MTRR_LIB_SYSTEM_PARAMETER *SystemParameter IN MTRR_LIB_SYSTEM_PARAMETER *SystemParameter
) )
{ {
UINT32 Index; UINT32 Index;
SetMem (mFixedMtrrsValue, sizeof (mFixedMtrrsValue), SystemParameter->DefaultCacheType); SetMem (mFixedMtrrsValue, sizeof (mFixedMtrrsValue), SystemParameter->DefaultCacheType);
@@ -325,10 +332,10 @@ InitializeMtrrRegs (
UNIT_TEST_STATUS UNIT_TEST_STATUS
EFIAPI EFIAPI
InitializeSystem ( InitializeSystem (
IN UNIT_TEST_CONTEXT Context IN UNIT_TEST_CONTEXT Context
) )
{ {
return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *) Context); return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *)Context);
} }
/** /**
@@ -344,34 +351,34 @@ InitializeSystem (
**/ **/
VOID VOID
CollectTestResult ( CollectTestResult (
IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN MTRR_MEMORY_CACHE_TYPE DefaultType,
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN UINT32 VariableMtrrCount, IN UINT32 VariableMtrrCount,
IN MTRR_SETTINGS *Mtrrs, IN MTRR_SETTINGS *Mtrrs,
OUT MTRR_MEMORY_RANGE *Ranges, OUT MTRR_MEMORY_RANGE *Ranges,
IN OUT UINTN *RangeCount, IN OUT UINTN *RangeCount,
OUT UINT32 *MtrrCount OUT UINT32 *MtrrCount
) )
{ {
UINTN Index; UINTN Index;
UINT64 MtrrValidBitsMask; UINT64 MtrrValidBitsMask;
UINT64 MtrrValidAddressMask; UINT64 MtrrValidAddressMask;
MTRR_MEMORY_RANGE RawMemoryRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)]; MTRR_MEMORY_RANGE RawMemoryRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];
ASSERT (Mtrrs != NULL); ASSERT (Mtrrs != NULL);
ASSERT (VariableMtrrCount <= ARRAY_SIZE (Mtrrs->Variables.Mtrr)); ASSERT (VariableMtrrCount <= ARRAY_SIZE (Mtrrs->Variables.Mtrr));
MtrrValidBitsMask = (1ull << PhysicalAddressBits) - 1; MtrrValidBitsMask = (1ull << PhysicalAddressBits) - 1;
MtrrValidAddressMask = MtrrValidBitsMask & ~0xFFFull; MtrrValidAddressMask = MtrrValidBitsMask & ~0xFFFull;
*MtrrCount = 0; *MtrrCount = 0;
for (Index = 0; Index < VariableMtrrCount; Index++) { for (Index = 0; Index < VariableMtrrCount; Index++) {
if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) { if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) {
RawMemoryRanges[*MtrrCount].BaseAddress = Mtrrs->Variables.Mtrr[Index].Base & MtrrValidAddressMask; RawMemoryRanges[*MtrrCount].BaseAddress = Mtrrs->Variables.Mtrr[Index].Base & MtrrValidAddressMask;
RawMemoryRanges[*MtrrCount].Type = RawMemoryRanges[*MtrrCount].Type =
((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type; ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type;
RawMemoryRanges[*MtrrCount].Length = RawMemoryRanges[*MtrrCount].Length =
((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1; ((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;
(*MtrrCount)++; (*MtrrCount)++;
} }
} }
@@ -392,7 +399,7 @@ Random32 (
UINT32 Limit UINT32 Limit
) )
{ {
return (UINT32) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start; return (UINT32)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start;
} }
/** /**
@@ -408,7 +415,7 @@ Random64 (
UINT64 Limit UINT64 Limit
) )
{ {
return (UINT64) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start; return (UINT64)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start;
} }
/** /**
@@ -421,30 +428,30 @@ Random64 (
**/ **/
VOID VOID
GenerateRandomMtrrPair ( GenerateRandomMtrrPair (
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN MTRR_MEMORY_CACHE_TYPE CacheType, IN MTRR_MEMORY_CACHE_TYPE CacheType,
OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL, OUT MTRR_VARIABLE_SETTING *MtrrPair OPTIONAL,
OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL OUT MTRR_MEMORY_RANGE *MtrrMemoryRange OPTIONAL
) )
{ {
MSR_IA32_MTRR_PHYSBASE_REGISTER PhysBase; MSR_IA32_MTRR_PHYSBASE_REGISTER PhysBase;
MSR_IA32_MTRR_PHYSMASK_REGISTER PhysMask; MSR_IA32_MTRR_PHYSMASK_REGISTER PhysMask;
UINT32 SizeShift; UINT32 SizeShift;
UINT32 BaseShift; UINT32 BaseShift;
UINT64 RandomBoundary; UINT64 RandomBoundary;
UINT64 MaxPhysicalAddress; UINT64 MaxPhysicalAddress;
UINT64 RangeSize; UINT64 RangeSize;
UINT64 RangeBase; UINT64 RangeBase;
UINT64 PhysBasePhyMaskValidBitsMask; UINT64 PhysBasePhyMaskValidBitsMask;
MaxPhysicalAddress = 1ull << PhysicalAddressBits; MaxPhysicalAddress = 1ull << PhysicalAddressBits;
do { do {
SizeShift = Random32 (12, PhysicalAddressBits - 1); SizeShift = Random32 (12, PhysicalAddressBits - 1);
RangeSize = 1ull << SizeShift; RangeSize = 1ull << SizeShift;
BaseShift = Random32 (SizeShift, PhysicalAddressBits - 1); BaseShift = Random32 (SizeShift, PhysicalAddressBits - 1);
RandomBoundary = Random64 (0, 1ull << (PhysicalAddressBits - BaseShift)); RandomBoundary = Random64 (0, 1ull << (PhysicalAddressBits - BaseShift));
RangeBase = RandomBoundary << BaseShift; RangeBase = RandomBoundary << BaseShift;
} while (RangeBase < SIZE_1MB || RangeBase > MaxPhysicalAddress - 1); } while (RangeBase < SIZE_1MB || RangeBase > MaxPhysicalAddress - 1);
PhysBasePhyMaskValidBitsMask = (MaxPhysicalAddress - 1) & 0xfffffffffffff000ULL; PhysBasePhyMaskValidBitsMask = (MaxPhysicalAddress - 1) & 0xfffffffffffff000ULL;
@@ -468,7 +475,6 @@ GenerateRandomMtrrPair (
} }
} }
/** /**
Check whether the Range overlaps with any one in Ranges. Check whether the Range overlaps with any one in Ranges.
@@ -480,9 +486,9 @@ GenerateRandomMtrrPair (
**/ **/
BOOLEAN BOOLEAN
RangesOverlap ( RangesOverlap (
IN MTRR_MEMORY_RANGE *Range, IN MTRR_MEMORY_RANGE *Range,
IN MTRR_MEMORY_RANGE *Ranges, IN MTRR_MEMORY_RANGE *Ranges,
IN UINTN Count IN UINTN Count
) )
{ {
while (Count-- != 0) { while (Count-- != 0) {
@@ -491,11 +497,13 @@ RangesOverlap (
// 1. range#2.base is in the middle of range#1 // 1. range#2.base is in the middle of range#1
// 2. range#1.base is in the middle of range#2 // 2. range#1.base is in the middle of range#2
// //
if ((Range->BaseAddress <= Ranges[Count].BaseAddress && Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length) if ( ((Range->BaseAddress <= Ranges[Count].BaseAddress) && (Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length))
|| (Ranges[Count].BaseAddress <= Range->BaseAddress && Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)) { || ((Ranges[Count].BaseAddress <= Range->BaseAddress) && (Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)))
{
return TRUE; return TRUE;
} }
} }
return FALSE; return FALSE;
} }
@@ -512,16 +520,16 @@ RangesOverlap (
**/ **/
VOID VOID
GenerateValidAndConfigurableMtrrPairs ( GenerateValidAndConfigurableMtrrPairs (
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges, IN OUT MTRR_MEMORY_RANGE *RawMemoryRanges,
IN UINT32 UcCount, IN UINT32 UcCount,
IN UINT32 WtCount, IN UINT32 WtCount,
IN UINT32 WbCount, IN UINT32 WbCount,
IN UINT32 WpCount, IN UINT32 WpCount,
IN UINT32 WcCount IN UINT32 WcCount
) )
{ {
UINT32 Index; UINT32 Index;
// //
// 1. Generate UC, WT, WB in order. // 1. Generate UC, WT, WB in order.
@@ -567,7 +575,7 @@ GenerateRandomCacheType (
VOID VOID
) )
{ {
return mMemoryCacheTypes[Random32 (0, ARRAY_SIZE (mMemoryCacheTypes) - 1)]; return mMemoryCacheTypes[Random32 (0, ARRAY_SIZE (mMemoryCacheTypes) - 1)];
} }
/** /**
@@ -586,19 +594,20 @@ GenerateRandomCacheType (
**/ **/
INT32 INT32
CompareFuncUint64 ( CompareFuncUint64 (
CONST VOID * Left, CONST VOID *Left,
CONST VOID * Right CONST VOID *Right
) )
{ {
INT64 Delta; INT64 Delta;
Delta = (*(UINT64*)Left - *(UINT64*)Right);
if (Delta > 0) { Delta = (*(UINT64 *)Left - *(UINT64 *)Right);
return 1; if (Delta > 0) {
} else if (Delta == 0) { return 1;
return 0; } else if (Delta == 0) {
} else { return 0;
return -1; } else {
} return -1;
}
} }
/** /**
@@ -611,13 +620,14 @@ CompareFuncUint64 (
**/ **/
VOID VOID
DetermineMemoryCacheType ( DetermineMemoryCacheType (
IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN MTRR_MEMORY_CACHE_TYPE DefaultType,
IN OUT MTRR_MEMORY_RANGE *Range, IN OUT MTRR_MEMORY_RANGE *Range,
IN MTRR_MEMORY_RANGE *Ranges, IN MTRR_MEMORY_RANGE *Ranges,
IN UINT32 RangeCount IN UINT32 RangeCount
) )
{ {
UINT32 Index; UINT32 Index;
Range->Type = CacheInvalid; Range->Type = CacheInvalid;
for (Index = 0; Index < RangeCount; Index++) { for (Index = 0; Index < RangeCount; Index++) {
if (RangesOverlap (Range, &Ranges[Index], 1)) { if (RangesOverlap (Range, &Ranges[Index], 1)) {
@@ -643,16 +653,18 @@ DetermineMemoryCacheType (
**/ **/
UINT32 UINT32
GetNextDifferentElementInSortedArray ( GetNextDifferentElementInSortedArray (
IN UINT32 Index, IN UINT32 Index,
IN UINT64 *Array, IN UINT64 *Array,
IN UINT32 Count IN UINT32 Count
) )
{ {
UINT64 CurrentElement; UINT64 CurrentElement;
CurrentElement = Array[Index]; CurrentElement = Array[Index];
while (CurrentElement == Array[Index] && Index < Count) { while (CurrentElement == Array[Index] && Index < Count) {
Index++; Index++;
} }
return Index; return Index;
} }
@@ -664,12 +676,12 @@ GetNextDifferentElementInSortedArray (
**/ **/
VOID VOID
RemoveDuplicatesInSortedArray ( RemoveDuplicatesInSortedArray (
IN OUT UINT64 *Array, IN OUT UINT64 *Array,
IN OUT UINT32 *Count IN OUT UINT32 *Count
) )
{ {
UINT32 Index; UINT32 Index;
UINT32 NewCount; UINT32 NewCount;
Index = 0; Index = 0;
NewCount = 0; NewCount = 0;
@@ -678,6 +690,7 @@ RemoveDuplicatesInSortedArray (
NewCount++; NewCount++;
Index = GetNextDifferentElementInSortedArray (Index, Array, *Count); Index = GetNextDifferentElementInSortedArray (Index, Array, *Count);
} }
*Count = NewCount; *Count = NewCount;
} }
@@ -690,11 +703,11 @@ RemoveDuplicatesInSortedArray (
**/ **/
BOOLEAN BOOLEAN
AddressInRange ( AddressInRange (
IN UINT64 Address, IN UINT64 Address,
IN MTRR_MEMORY_RANGE Range IN MTRR_MEMORY_RANGE Range
) )
{ {
return (Address >= Range.BaseAddress) && (Address <= Range.BaseAddress + Range.Length - 1); return (Address >= Range.BaseAddress) && (Address <= Range.BaseAddress + Range.Length - 1);
} }
/** /**
@@ -706,13 +719,14 @@ AddressInRange (
**/ **/
UINT64 UINT64
GetOverlapBitFlag ( GetOverlapBitFlag (
IN MTRR_MEMORY_RANGE *RawMemoryRanges, IN MTRR_MEMORY_RANGE *RawMemoryRanges,
IN UINT32 RawMemoryRangeCount, IN UINT32 RawMemoryRangeCount,
IN UINT64 Address IN UINT64 Address
) )
{ {
UINT64 OverlapBitFlag; UINT64 OverlapBitFlag;
UINT32 Index; UINT32 Index;
OverlapBitFlag = 0; OverlapBitFlag = 0;
for (Index = 0; Index < RawMemoryRangeCount; Index++) { for (Index = 0; Index < RawMemoryRangeCount; Index++) {
if (AddressInRange (Address, RawMemoryRanges[Index])) { if (AddressInRange (Address, RawMemoryRanges[Index])) {
@@ -736,14 +750,23 @@ GetOverlapBitFlag (
**/ **/
UINT32 UINT32
CheckOverlapBitFlagsRelation ( CheckOverlapBitFlagsRelation (
IN UINT64 Flag1, IN UINT64 Flag1,
IN UINT64 Flag2 IN UINT64 Flag2
) )
{ {
if (Flag1 == Flag2) return 0; if (Flag1 == Flag2) {
if ((Flag1 | Flag2) == Flag2) return 1; return 0;
if ((Flag1 | Flag2) == Flag1) return 2; }
return 3;
if ((Flag1 | Flag2) == Flag2) {
return 1;
}
if ((Flag1 | Flag2) == Flag1) {
return 2;
}
return 3;
} }
/** /**
@@ -758,20 +781,21 @@ CheckOverlapBitFlagsRelation (
**/ **/
BOOLEAN BOOLEAN
IsEndpointInRanges ( IsEndpointInRanges (
IN UINT64 Endpoint, IN UINT64 Endpoint,
IN MTRR_MEMORY_RANGE *Ranges, IN MTRR_MEMORY_RANGE *Ranges,
IN UINTN RangeCount IN UINTN RangeCount
) )
{ {
UINT32 Index; UINT32 Index;
for (Index = 0; Index < RangeCount; Index++) {
if (AddressInRange (Endpoint, Ranges[Index])) {
return TRUE;
}
}
return FALSE;
}
for (Index = 0; Index < RangeCount; Index++) {
if (AddressInRange (Endpoint, Ranges[Index])) {
return TRUE;
}
}
return FALSE;
}
/** /**
Compact adjacent ranges of the same type. Compact adjacent ranges of the same type.
@@ -783,26 +807,26 @@ IsEndpointInRanges (
**/ **/
VOID VOID
CompactAndExtendEffectiveMtrrMemoryRanges ( CompactAndExtendEffectiveMtrrMemoryRanges (
IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN MTRR_MEMORY_CACHE_TYPE DefaultType,
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN OUT MTRR_MEMORY_RANGE **EffectiveMtrrMemoryRanges, IN OUT MTRR_MEMORY_RANGE **EffectiveMtrrMemoryRanges,
IN OUT UINTN *EffectiveMtrrMemoryRangesCount IN OUT UINTN *EffectiveMtrrMemoryRangesCount
) )
{ {
UINT64 MaxAddress; UINT64 MaxAddress;
UINTN NewRangesCountAtMost; UINTN NewRangesCountAtMost;
MTRR_MEMORY_RANGE *NewRanges; MTRR_MEMORY_RANGE *NewRanges;
UINTN NewRangesCountActual; UINTN NewRangesCountActual;
MTRR_MEMORY_RANGE *CurrentRangeInNewRanges; MTRR_MEMORY_RANGE *CurrentRangeInNewRanges;
MTRR_MEMORY_CACHE_TYPE CurrentRangeTypeInOldRanges; MTRR_MEMORY_CACHE_TYPE CurrentRangeTypeInOldRanges;
MTRR_MEMORY_RANGE *OldRanges; MTRR_MEMORY_RANGE *OldRanges;
MTRR_MEMORY_RANGE OldLastRange; MTRR_MEMORY_RANGE OldLastRange;
UINTN OldRangesIndex; UINTN OldRangesIndex;
NewRangesCountActual = 0; NewRangesCountActual = 0;
NewRangesCountAtMost = *EffectiveMtrrMemoryRangesCount + 2; // At most with 2 more range entries. NewRangesCountAtMost = *EffectiveMtrrMemoryRangesCount + 2; // At most with 2 more range entries.
NewRanges = (MTRR_MEMORY_RANGE *) calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE)); NewRanges = (MTRR_MEMORY_RANGE *)calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE));
OldRanges = *EffectiveMtrrMemoryRanges; OldRanges = *EffectiveMtrrMemoryRanges;
if (OldRanges[0].BaseAddress > 0) { if (OldRanges[0].BaseAddress > 0) {
NewRanges[NewRangesCountActual].BaseAddress = 0; NewRanges[NewRangesCountActual].BaseAddress = 0;
@@ -814,44 +838,45 @@ CompactAndExtendEffectiveMtrrMemoryRanges (
OldRangesIndex = 0; OldRangesIndex = 0;
while (OldRangesIndex < *EffectiveMtrrMemoryRangesCount) { while (OldRangesIndex < *EffectiveMtrrMemoryRangesCount) {
CurrentRangeTypeInOldRanges = OldRanges[OldRangesIndex].Type; CurrentRangeTypeInOldRanges = OldRanges[OldRangesIndex].Type;
CurrentRangeInNewRanges = NULL; CurrentRangeInNewRanges = NULL;
if (NewRangesCountActual > 0) // We need to check CurrentNewRange first before generate a new NewRange. if (NewRangesCountActual > 0) {
{ // We need to check CurrentNewRange first before generate a new NewRange.
CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1]; CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1];
} }
if (CurrentRangeInNewRanges != NULL && CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges) {
if ((CurrentRangeInNewRanges != NULL) && (CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges)) {
CurrentRangeInNewRanges->Length += OldRanges[OldRangesIndex].Length; CurrentRangeInNewRanges->Length += OldRanges[OldRangesIndex].Length;
} else { } else {
NewRanges[NewRangesCountActual].BaseAddress = OldRanges[OldRangesIndex].BaseAddress; NewRanges[NewRangesCountActual].BaseAddress = OldRanges[OldRangesIndex].BaseAddress;
NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length; NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;
NewRanges[NewRangesCountActual].Type = CurrentRangeTypeInOldRanges; NewRanges[NewRangesCountActual].Type = CurrentRangeTypeInOldRanges;
while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) {
{
OldRangesIndex++; OldRangesIndex++;
NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length; NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;
} }
NewRangesCountActual++; NewRangesCountActual++;
} }
OldRangesIndex++; OldRangesIndex++;
} }
MaxAddress = (1ull << PhysicalAddressBits) - 1; MaxAddress = (1ull << PhysicalAddressBits) - 1;
OldLastRange = OldRanges[(*EffectiveMtrrMemoryRangesCount) - 1]; OldLastRange = OldRanges[(*EffectiveMtrrMemoryRangesCount) - 1];
CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1]; CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1];
if (OldLastRange.BaseAddress + OldLastRange.Length - 1 < MaxAddress) { if (OldLastRange.BaseAddress + OldLastRange.Length - 1 < MaxAddress) {
if (CurrentRangeInNewRanges->Type == DefaultType) { if (CurrentRangeInNewRanges->Type == DefaultType) {
CurrentRangeInNewRanges->Length = MaxAddress - CurrentRangeInNewRanges->BaseAddress + 1; CurrentRangeInNewRanges->Length = MaxAddress - CurrentRangeInNewRanges->BaseAddress + 1;
} else { } else {
NewRanges[NewRangesCountActual].BaseAddress = OldLastRange.BaseAddress + OldLastRange.Length; NewRanges[NewRangesCountActual].BaseAddress = OldLastRange.BaseAddress + OldLastRange.Length;
NewRanges[NewRangesCountActual].Length = MaxAddress - NewRanges[NewRangesCountActual].BaseAddress + 1; NewRanges[NewRangesCountActual].Length = MaxAddress - NewRanges[NewRangesCountActual].BaseAddress + 1;
NewRanges[NewRangesCountActual].Type = DefaultType; NewRanges[NewRangesCountActual].Type = DefaultType;
NewRangesCountActual++; NewRangesCountActual++;
} }
} }
free (*EffectiveMtrrMemoryRanges); free (*EffectiveMtrrMemoryRanges);
*EffectiveMtrrMemoryRanges = NewRanges; *EffectiveMtrrMemoryRanges = NewRanges;
*EffectiveMtrrMemoryRangesCount = NewRangesCountActual; *EffectiveMtrrMemoryRangesCount = NewRangesCountActual;
} }
@@ -865,20 +890,20 @@ CompactAndExtendEffectiveMtrrMemoryRanges (
**/ **/
VOID VOID
CollectEndpoints ( CollectEndpoints (
IN OUT UINT64 *Endpoints, IN OUT UINT64 *Endpoints,
IN OUT UINT32 *EndPointCount, IN OUT UINT32 *EndPointCount,
IN MTRR_MEMORY_RANGE *RawMemoryRanges, IN MTRR_MEMORY_RANGE *RawMemoryRanges,
IN UINT32 RawMemoryRangeCount IN UINT32 RawMemoryRangeCount
) )
{ {
UINT32 Index; UINT32 Index;
UINT32 RawRangeIndex; UINT32 RawRangeIndex;
ASSERT ((RawMemoryRangeCount << 1) == *EndPointCount); ASSERT ((RawMemoryRangeCount << 1) == *EndPointCount);
for (Index = 0; Index < *EndPointCount; Index += 2) { for (Index = 0; Index < *EndPointCount; Index += 2) {
RawRangeIndex = Index >> 1; RawRangeIndex = Index >> 1;
Endpoints[Index] = RawMemoryRanges[RawRangeIndex].BaseAddress; Endpoints[Index] = RawMemoryRanges[RawRangeIndex].BaseAddress;
Endpoints[Index + 1] = RawMemoryRanges[RawRangeIndex].BaseAddress + RawMemoryRanges[RawRangeIndex].Length - 1; Endpoints[Index + 1] = RawMemoryRanges[RawRangeIndex].BaseAddress + RawMemoryRanges[RawRangeIndex].Length - 1;
} }
@@ -898,41 +923,41 @@ CollectEndpoints (
**/ **/
VOID VOID
GetEffectiveMemoryRanges ( GetEffectiveMemoryRanges (
IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN MTRR_MEMORY_CACHE_TYPE DefaultType,
IN UINT32 PhysicalAddressBits, IN UINT32 PhysicalAddressBits,
IN MTRR_MEMORY_RANGE *RawMemoryRanges, IN MTRR_MEMORY_RANGE *RawMemoryRanges,
IN UINT32 RawMemoryRangeCount, IN UINT32 RawMemoryRangeCount,
OUT MTRR_MEMORY_RANGE *MemoryRanges, OUT MTRR_MEMORY_RANGE *MemoryRanges,
OUT UINTN *MemoryRangeCount OUT UINTN *MemoryRangeCount
) )
{ {
UINTN Index; UINTN Index;
UINT32 AllEndPointsCount; UINT32 AllEndPointsCount;
UINT64 *AllEndPointsInclusive; UINT64 *AllEndPointsInclusive;
UINT32 AllRangePiecesCountMax; UINT32 AllRangePiecesCountMax;
MTRR_MEMORY_RANGE *AllRangePieces; MTRR_MEMORY_RANGE *AllRangePieces;
UINTN AllRangePiecesCountActual; UINTN AllRangePiecesCountActual;
UINT64 OverlapBitFlag1; UINT64 OverlapBitFlag1;
UINT64 OverlapBitFlag2; UINT64 OverlapBitFlag2;
INT32 OverlapFlagRelation; INT32 OverlapFlagRelation;
if (RawMemoryRangeCount == 0) { if (RawMemoryRangeCount == 0) {
MemoryRanges[0].BaseAddress = 0; MemoryRanges[0].BaseAddress = 0;
MemoryRanges[0].Length = (1ull << PhysicalAddressBits); MemoryRanges[0].Length = (1ull << PhysicalAddressBits);
MemoryRanges[0].Type = DefaultType; MemoryRanges[0].Type = DefaultType;
*MemoryRangeCount = 1; *MemoryRangeCount = 1;
return; return;
} }
AllEndPointsCount = RawMemoryRangeCount << 1; AllEndPointsCount = RawMemoryRangeCount << 1;
AllEndPointsInclusive = calloc (AllEndPointsCount, sizeof (UINT64)); AllEndPointsInclusive = calloc (AllEndPointsCount, sizeof (UINT64));
AllRangePiecesCountMax = RawMemoryRangeCount * 3 + 1; AllRangePiecesCountMax = RawMemoryRangeCount * 3 + 1;
AllRangePieces = calloc (AllRangePiecesCountMax, sizeof (MTRR_MEMORY_RANGE)); AllRangePieces = calloc (AllRangePiecesCountMax, sizeof (MTRR_MEMORY_RANGE));
CollectEndpoints (AllEndPointsInclusive, &AllEndPointsCount, RawMemoryRanges, RawMemoryRangeCount); CollectEndpoints (AllEndPointsInclusive, &AllEndPointsCount, RawMemoryRanges, RawMemoryRangeCount);
for (Index = 0, AllRangePiecesCountActual = 0; Index < AllEndPointsCount - 1; Index++) { for (Index = 0, AllRangePiecesCountActual = 0; Index < AllEndPointsCount - 1; Index++) {
OverlapBitFlag1 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index]); OverlapBitFlag1 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index]);
OverlapBitFlag2 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index + 1]); OverlapBitFlag2 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index + 1]);
OverlapFlagRelation = CheckOverlapBitFlagsRelation (OverlapBitFlag1, OverlapBitFlag2); OverlapFlagRelation = CheckOverlapBitFlagsRelation (OverlapBitFlag1, OverlapBitFlag2);
switch (OverlapFlagRelation) { switch (OverlapFlagRelation) {
case 0: // [1, 2] case 0: // [1, 2]
@@ -955,18 +980,23 @@ GetEffectiveMemoryRanges (
AllRangePieces[AllRangePiecesCountActual].Length = 1; AllRangePieces[AllRangePiecesCountActual].Length = 1;
AllRangePiecesCountActual++; AllRangePiecesCountActual++;
} }
break; break;
case 3: // (1, 2) case 3: // (1, 2)
AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index] + 1; AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index] + 1;
AllRangePieces[AllRangePiecesCountActual].Length = (AllEndPointsInclusive[Index + 1] - 1) - (AllEndPointsInclusive[Index] + 1) + 1; AllRangePieces[AllRangePiecesCountActual].Length = (AllEndPointsInclusive[Index + 1] - 1) - (AllEndPointsInclusive[Index] + 1) + 1;
if (AllRangePieces[AllRangePiecesCountActual].Length == 0) // Only in case 3 can exists Length=0, we should skip such "segment". if (AllRangePieces[AllRangePiecesCountActual].Length == 0) {
// Only in case 3 can exists Length=0, we should skip such "segment".
break; break;
}
AllRangePiecesCountActual++; AllRangePiecesCountActual++;
if (!IsEndpointInRanges (AllEndPointsInclusive[Index], AllRangePieces, AllRangePiecesCountActual)) { if (!IsEndpointInRanges (AllEndPointsInclusive[Index], AllRangePieces, AllRangePiecesCountActual)) {
AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index]; AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index];
AllRangePieces[AllRangePiecesCountActual].Length = 1; AllRangePieces[AllRangePiecesCountActual].Length = 1;
AllRangePiecesCountActual++; AllRangePiecesCountActual++;
} }
break; break;
default: default:
ASSERT (FALSE); ASSERT (FALSE);

8
UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c
View File

@@ -30,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
EFI_PEI_PPI_DESCRIPTOR * EFI_PEI_PPI_DESCRIPTOR *
EFIAPI EFIAPI
SecPlatformMain ( SecPlatformMain (
IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
) )
{ {
return NULL; return NULL;
@@ -50,9 +50,9 @@ SecPlatformMain (
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
SecPlatformInformation ( SecPlatformInformation (
IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_SERVICES **PeiServices,
IN OUT UINT64 *StructureSize, IN OUT UINT64 *StructureSize,
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
) )
{ {
return EFI_SUCCESS; return EFI_SUCCESS;

894
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
View File

File diff suppressed because it is too large Load Diff

114
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
View File

@@ -13,7 +13,7 @@
#include "RegisterCpuFeatures.h" #include "RegisterCpuFeatures.h"
CPU_FEATURES_DATA mCpuFeaturesData = {0}; CPU_FEATURES_DATA mCpuFeaturesData = { 0 };
/** /**
Worker function to get CPU_FEATURES_DATA pointer. Worker function to get CPU_FEATURES_DATA pointer.
@@ -38,17 +38,17 @@ GetMpService (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
MP_SERVICES MpService; MP_SERVICES MpService;
// //
// Get MP Services Protocol // Get MP Services Protocol
// //
Status = gBS->LocateProtocol ( Status = gBS->LocateProtocol (
&gEfiMpServiceProtocolGuid, &gEfiMpServiceProtocolGuid,
NULL, NULL,
(VOID **)&MpService.Protocol (VOID **)&MpService.Protocol
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return MpService; return MpService;
@@ -63,15 +63,15 @@ GetMpService (
**/ **/
UINTN UINTN
GetProcessorIndex ( GetProcessorIndex (
IN CPU_FEATURES_DATA *CpuFeaturesData IN CPU_FEATURES_DATA *CpuFeaturesData
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN ProcessorIndex; UINTN ProcessorIndex;
EFI_MP_SERVICES_PROTOCOL *MpServices; EFI_MP_SERVICES_PROTOCOL *MpServices;
MpServices = CpuFeaturesData->MpService.Protocol; MpServices = CpuFeaturesData->MpService.Protocol;
Status = MpServices->WhoAmI(MpServices, &ProcessorIndex); Status = MpServices->WhoAmI (MpServices, &ProcessorIndex);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return ProcessorIndex; return ProcessorIndex;
} }
@@ -88,22 +88,22 @@ GetProcessorIndex (
**/ **/
EFI_STATUS EFI_STATUS
GetProcessorInformation ( GetProcessorInformation (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_MP_SERVICES_PROTOCOL *MpServices; EFI_MP_SERVICES_PROTOCOL *MpServices;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
MpServices = CpuFeaturesData->MpService.Protocol; MpServices = CpuFeaturesData->MpService.Protocol;
Status = MpServices->GetProcessorInfo ( Status = MpServices->GetProcessorInfo (
MpServices, MpServices,
ProcessorNumber, ProcessorNumber,
ProcessorInfoBuffer ProcessorInfoBuffer
); );
return Status; return Status;
} }
@@ -117,29 +117,29 @@ GetProcessorInformation (
**/ **/
VOID VOID
StartupAllAPsWorker ( StartupAllAPsWorker (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN EFI_EVENT MpEvent IN EFI_EVENT MpEvent
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_MP_SERVICES_PROTOCOL *MpServices; EFI_MP_SERVICES_PROTOCOL *MpServices;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
MpServices = CpuFeaturesData->MpService.Protocol; MpServices = CpuFeaturesData->MpService.Protocol;
// //
// Wakeup all APs // Wakeup all APs
// //
Status = MpServices->StartupAllAPs ( Status = MpServices->StartupAllAPs (
MpServices, MpServices,
Procedure, Procedure,
FALSE, FALSE,
MpEvent, MpEvent,
0, 0,
CpuFeaturesData, CpuFeaturesData,
NULL NULL
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -150,24 +150,24 @@ StartupAllAPsWorker (
**/ **/
VOID VOID
SwitchNewBsp ( SwitchNewBsp (
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_MP_SERVICES_PROTOCOL *MpServices; EFI_MP_SERVICES_PROTOCOL *MpServices;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
MpServices = CpuFeaturesData->MpService.Protocol; MpServices = CpuFeaturesData->MpService.Protocol;
// //
// Wakeup all APs // Wakeup all APs
// //
Status = MpServices->SwitchBSP ( Status = MpServices->SwitchBSP (
MpServices, MpServices,
ProcessorNumber, ProcessorNumber,
TRUE TRUE
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -183,16 +183,16 @@ SwitchNewBsp (
**/ **/
VOID VOID
GetNumberOfProcessor ( GetNumberOfProcessor (
OUT UINTN *NumberOfCpus, OUT UINTN *NumberOfCpus,
OUT UINTN *NumberOfEnabledProcessors OUT UINTN *NumberOfEnabledProcessors
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EFI_MP_SERVICES_PROTOCOL *MpServices; EFI_MP_SERVICES_PROTOCOL *MpServices;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
MpServices = CpuFeaturesData->MpService.Protocol; MpServices = CpuFeaturesData->MpService.Protocol;
// //
// Get the number of CPUs // Get the number of CPUs
@@ -219,14 +219,14 @@ CpuFeaturesInitialize (
VOID VOID
) )
{ {
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
UINTN OldBspNumber; UINTN OldBspNumber;
EFI_EVENT MpEvent; EFI_EVENT MpEvent;
EFI_STATUS Status; EFI_STATUS Status;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
OldBspNumber = GetProcessorIndex (CpuFeaturesData); OldBspNumber = GetProcessorIndex (CpuFeaturesData);
CpuFeaturesData->BspNumber = OldBspNumber; CpuFeaturesData->BspNumber = OldBspNumber;
// //
@@ -263,6 +263,7 @@ CpuFeaturesInitialize (
do { do {
Status = gBS->CheckEvent (MpEvent); Status = gBS->CheckEvent (MpEvent);
} while (Status == EFI_NOT_READY); } while (Status == EFI_NOT_READY);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -273,4 +274,3 @@ CpuFeaturesInitialize (
SwitchNewBsp (CpuFeaturesData->BspNumber); SwitchNewBsp (CpuFeaturesData->BspNumber);
} }
} }

141
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
View File

@@ -20,7 +20,7 @@
0xa694c467, 0x697a, 0x446b, { 0xb9, 0x29, 0x5b, 0x14, 0xa0, 0xcf, 0x39, 0xf } \ 0xa694c467, 0x697a, 0x446b, { 0xb9, 0x29, 0x5b, 0x14, 0xa0, 0xcf, 0x39, 0xf } \
} }
EFI_GUID mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID; EFI_GUID mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID;
/** /**
Worker function to get CPU_FEATURES_DATA pointer. Worker function to get CPU_FEATURES_DATA pointer.
@@ -32,16 +32,16 @@ GetCpuFeaturesData (
VOID VOID
) )
{ {
CPU_FEATURES_DATA *CpuInitData; CPU_FEATURES_DATA *CpuInitData;
EFI_HOB_GUID_TYPE *GuidHob; EFI_HOB_GUID_TYPE *GuidHob;
VOID *DataInHob; VOID *DataInHob;
UINT64 Data64; UINT64 Data64;
CpuInitData = NULL; CpuInitData = NULL;
GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid); GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid);
if (GuidHob != NULL) { if (GuidHob != NULL) {
DataInHob = GET_GUID_HOB_DATA (GuidHob); DataInHob = GET_GUID_HOB_DATA (GuidHob);
CpuInitData = (CPU_FEATURES_DATA *) (*(UINTN *) DataInHob); CpuInitData = (CPU_FEATURES_DATA *)(*(UINTN *)DataInHob);
ASSERT (CpuInitData != NULL); ASSERT (CpuInitData != NULL);
} else { } else {
CpuInitData = AllocateZeroPool (sizeof (CPU_FEATURES_DATA)); CpuInitData = AllocateZeroPool (sizeof (CPU_FEATURES_DATA));
@@ -49,10 +49,10 @@ GetCpuFeaturesData (
// //
// Build location of CPU MP DATA buffer in HOB // Build location of CPU MP DATA buffer in HOB
// //
Data64 = (UINT64) (UINTN) CpuInitData; Data64 = (UINT64)(UINTN)CpuInitData;
BuildGuidDataHob ( BuildGuidDataHob (
&mRegisterCpuFeaturesHobGuid, &mRegisterCpuFeaturesHobGuid,
(VOID *) &Data64, (VOID *)&Data64,
sizeof (UINT64) sizeof (UINT64)
); );
} }
@@ -70,8 +70,8 @@ GetMpService (
VOID VOID
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
MP_SERVICES MpService; MP_SERVICES MpService;
// //
// Get MP Services2 Ppi // Get MP Services2 Ppi
@@ -95,12 +95,12 @@ GetMpService (
**/ **/
UINTN UINTN
GetProcessorIndex ( GetProcessorIndex (
IN CPU_FEATURES_DATA *CpuFeaturesData IN CPU_FEATURES_DATA *CpuFeaturesData
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
UINTN ProcessorIndex; UINTN ProcessorIndex;
CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
@@ -126,22 +126,22 @@ GetProcessorIndex (
**/ **/
EFI_STATUS EFI_STATUS
GetProcessorInformation ( GetProcessorInformation (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
) )
{ {
EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
EFI_STATUS Status; EFI_STATUS Status;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
Status = CpuMp2Ppi->GetProcessorInfo ( Status = CpuMp2Ppi->GetProcessorInfo (
CpuMp2Ppi, CpuMp2Ppi,
ProcessorNumber, ProcessorNumber,
ProcessorInfoBuffer ProcessorInfoBuffer
); );
return Status; return Status;
} }
@@ -155,27 +155,27 @@ GetProcessorInformation (
**/ **/
VOID VOID
StartupAllAPsWorker ( StartupAllAPsWorker (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN EFI_EVENT MpEvent IN EFI_EVENT MpEvent
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
// //
// Wakeup all APs for data collection. // Wakeup all APs for data collection.
// //
Status = CpuMp2Ppi->StartupAllAPs ( Status = CpuMp2Ppi->StartupAllAPs (
CpuMp2Ppi, CpuMp2Ppi,
Procedure, Procedure,
FALSE, FALSE,
0, 0,
CpuFeaturesData CpuFeaturesData
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -188,12 +188,12 @@ StartupAllAPsWorker (
**/ **/
VOID VOID
StartupAllCPUsWorker ( StartupAllCPUsWorker (
IN EFI_AP_PROCEDURE Procedure IN EFI_AP_PROCEDURE Procedure
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
@@ -201,12 +201,12 @@ StartupAllCPUsWorker (
// Get MP Services2 Ppi // Get MP Services2 Ppi
// //
CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
Status = CpuMp2Ppi->StartupAllCPUs ( Status = CpuMp2Ppi->StartupAllCPUs (
CpuMp2Ppi, CpuMp2Ppi,
Procedure, Procedure,
0, 0,
CpuFeaturesData CpuFeaturesData
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -217,24 +217,24 @@ StartupAllCPUsWorker (
**/ **/
VOID VOID
SwitchNewBsp ( SwitchNewBsp (
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
// //
// Wakeup all APs for data collection. // Wakeup all APs for data collection.
// //
Status = CpuMp2Ppi->SwitchBSP ( Status = CpuMp2Ppi->SwitchBSP (
CpuMp2Ppi, CpuMp2Ppi,
ProcessorNumber, ProcessorNumber,
TRUE TRUE
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -250,25 +250,25 @@ SwitchNewBsp (
**/ **/
VOID VOID
GetNumberOfProcessor ( GetNumberOfProcessor (
OUT UINTN *NumberOfCpus, OUT UINTN *NumberOfCpus,
OUT UINTN *NumberOfEnabledProcessors OUT UINTN *NumberOfEnabledProcessors
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi; EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
CpuMp2Ppi = CpuFeaturesData->MpService.Ppi; CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;
// //
// Get the number of CPUs // Get the number of CPUs
// //
Status = CpuMp2Ppi->GetNumberOfProcessors ( Status = CpuMp2Ppi->GetNumberOfProcessors (
CpuMp2Ppi, CpuMp2Ppi,
NumberOfCpus, NumberOfCpus,
NumberOfEnabledProcessors NumberOfEnabledProcessors
); );
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
} }
@@ -286,12 +286,12 @@ CpuFeaturesInitialize (
VOID VOID
) )
{ {
CPU_FEATURES_DATA *CpuFeaturesData; CPU_FEATURES_DATA *CpuFeaturesData;
UINTN OldBspNumber; UINTN OldBspNumber;
CpuFeaturesData = GetCpuFeaturesData (); CpuFeaturesData = GetCpuFeaturesData ();
OldBspNumber = GetProcessorIndex (CpuFeaturesData); OldBspNumber = GetProcessorIndex (CpuFeaturesData);
CpuFeaturesData->BspNumber = OldBspNumber; CpuFeaturesData->BspNumber = OldBspNumber;
// //
@@ -306,4 +306,3 @@ CpuFeaturesInitialize (
SwitchNewBsp (CpuFeaturesData->BspNumber); SwitchNewBsp (CpuFeaturesData->BspNumber);
} }
} }

110
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
View File

@@ -27,66 +27,66 @@
#define CPU_FEATURE_ENTRY_SIGNATURE SIGNATURE_32 ('C', 'F', 'E', 'S') #define CPU_FEATURE_ENTRY_SIGNATURE SIGNATURE_32 ('C', 'F', 'E', 'S')
#define CPU_FEATURE_NAME_SIZE 128 #define CPU_FEATURE_NAME_SIZE 128
typedef struct { typedef struct {
REGISTER_CPU_FEATURE_INFORMATION CpuInfo; REGISTER_CPU_FEATURE_INFORMATION CpuInfo;
UINT8 *FeaturesSupportedMask; UINT8 *FeaturesSupportedMask;
LIST_ENTRY OrderList; LIST_ENTRY OrderList;
} CPU_FEATURES_INIT_ORDER; } CPU_FEATURES_INIT_ORDER;
typedef struct { typedef struct {
UINT32 Signature; UINT32 Signature;
LIST_ENTRY Link; LIST_ENTRY Link;
UINT8 *FeatureMask; UINT8 *FeatureMask;
CHAR8 *FeatureName; CHAR8 *FeatureName;
CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc; CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc;
CPU_FEATURE_SUPPORT SupportFunc; CPU_FEATURE_SUPPORT SupportFunc;
CPU_FEATURE_INITIALIZE InitializeFunc; CPU_FEATURE_INITIALIZE InitializeFunc;
UINT8 *ThreadBeforeFeatureBitMask; UINT8 *ThreadBeforeFeatureBitMask;
UINT8 *ThreadAfterFeatureBitMask; UINT8 *ThreadAfterFeatureBitMask;
UINT8 *CoreBeforeFeatureBitMask; UINT8 *CoreBeforeFeatureBitMask;
UINT8 *CoreAfterFeatureBitMask; UINT8 *CoreAfterFeatureBitMask;
UINT8 *PackageBeforeFeatureBitMask; UINT8 *PackageBeforeFeatureBitMask;
UINT8 *PackageAfterFeatureBitMask; UINT8 *PackageAfterFeatureBitMask;
VOID *ConfigData; VOID *ConfigData;
BOOLEAN BeforeAll; BOOLEAN BeforeAll;
BOOLEAN AfterAll; BOOLEAN AfterAll;
} CPU_FEATURES_ENTRY; } CPU_FEATURES_ENTRY;
// //
// Flags used when program the register. // Flags used when program the register.
// //
typedef struct { typedef struct {
volatile UINTN MemoryMappedLock; // Spinlock used to program mmio volatile UINTN MemoryMappedLock; // Spinlock used to program mmio
volatile UINT32 *CoreSemaphoreCount; // Semaphore containers used to program Core semaphore. volatile UINT32 *CoreSemaphoreCount; // Semaphore containers used to program Core semaphore.
volatile UINT32 *PackageSemaphoreCount; // Semaphore containers used to program Package semaphore. volatile UINT32 *PackageSemaphoreCount; // Semaphore containers used to program Package semaphore.
} PROGRAM_CPU_REGISTER_FLAGS; } PROGRAM_CPU_REGISTER_FLAGS;
typedef union { typedef union {
EFI_MP_SERVICES_PROTOCOL *Protocol; EFI_MP_SERVICES_PROTOCOL *Protocol;
EDKII_PEI_MP_SERVICES2_PPI *Ppi; EDKII_PEI_MP_SERVICES2_PPI *Ppi;
} MP_SERVICES; } MP_SERVICES;
typedef struct { typedef struct {
UINTN FeaturesCount; UINTN FeaturesCount;
UINT32 BitMaskSize; UINT32 BitMaskSize;
LIST_ENTRY FeatureList; LIST_ENTRY FeatureList;
CPU_FEATURES_INIT_ORDER *InitOrder; CPU_FEATURES_INIT_ORDER *InitOrder;
UINT8 *CapabilityPcd; UINT8 *CapabilityPcd;
UINT8 *SettingPcd; UINT8 *SettingPcd;
UINT32 NumberOfCpus; UINT32 NumberOfCpus;
ACPI_CPU_DATA *AcpiCpuData; ACPI_CPU_DATA *AcpiCpuData;
CPU_REGISTER_TABLE *RegisterTable; CPU_REGISTER_TABLE *RegisterTable;
CPU_REGISTER_TABLE *PreSmmRegisterTable; CPU_REGISTER_TABLE *PreSmmRegisterTable;
UINTN BspNumber; UINTN BspNumber;
PROGRAM_CPU_REGISTER_FLAGS CpuFlags; PROGRAM_CPU_REGISTER_FLAGS CpuFlags;
MP_SERVICES MpService; MP_SERVICES MpService;
} CPU_FEATURES_DATA; } CPU_FEATURES_DATA;
#define CPU_FEATURE_ENTRY_FROM_LINK(a) \ #define CPU_FEATURE_ENTRY_FROM_LINK(a) \
@@ -116,7 +116,7 @@ GetCpuFeaturesData (
**/ **/
UINTN UINTN
GetProcessorIndex ( GetProcessorIndex (
IN CPU_FEATURES_DATA *CpuFeaturesData IN CPU_FEATURES_DATA *CpuFeaturesData
); );
/** /**
@@ -131,8 +131,8 @@ GetProcessorIndex (
**/ **/
EFI_STATUS EFI_STATUS
GetProcessorInformation ( GetProcessorInformation (
IN UINTN ProcessorNumber, IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
); );
/** /**
@@ -145,8 +145,8 @@ GetProcessorInformation (
**/ **/
VOID VOID
StartupAllAPsWorker ( StartupAllAPsWorker (
IN EFI_AP_PROCEDURE Procedure, IN EFI_AP_PROCEDURE Procedure,
IN EFI_EVENT MpEvent IN EFI_EVENT MpEvent
); );
/** /**
@@ -161,8 +161,8 @@ StartupAllAPsWorker (
**/ **/
VOID VOID
GetNumberOfProcessor ( GetNumberOfProcessor (
OUT UINTN *NumberOfCpus, OUT UINTN *NumberOfCpus,
OUT UINTN *NumberOfEnabledProcessors OUT UINTN *NumberOfEnabledProcessors
); );
/** /**
@@ -172,7 +172,7 @@ GetNumberOfProcessor (
**/ **/
VOID VOID
SwitchNewBsp ( SwitchNewBsp (
IN UINTN ProcessorNumber IN UINTN ProcessorNumber
); );
/** /**
@@ -184,8 +184,8 @@ SwitchNewBsp (
**/ **/
VOID VOID
DumpCpuFeatureMask ( DumpCpuFeatureMask (
IN UINT8 *FeatureMask, IN UINT8 *FeatureMask,
IN UINT32 BitMaskSize IN UINT32 BitMaskSize
); );
/** /**
@@ -212,9 +212,9 @@ DumpCpuFeature (
**/ **/
CPU_FEATURE_DEPENDENCE_TYPE CPU_FEATURE_DEPENDENCE_TYPE
DetectFeatureScope ( DetectFeatureScope (
IN CPU_FEATURES_ENTRY *CpuFeature, IN CPU_FEATURES_ENTRY *CpuFeature,
IN BOOLEAN Before, IN BOOLEAN Before,
IN UINT8 *NextCpuFeatureMask IN UINT8 *NextCpuFeatureMask
); );
/** /**
@@ -228,9 +228,9 @@ DetectFeatureScope (
**/ **/
CPU_FEATURE_DEPENDENCE_TYPE CPU_FEATURE_DEPENDENCE_TYPE
DetectNoneNeighborhoodFeatureScope ( DetectNoneNeighborhoodFeatureScope (
IN CPU_FEATURES_ENTRY *CpuFeature, IN CPU_FEATURES_ENTRY *CpuFeature,
IN BOOLEAN Before, IN BOOLEAN Before,
IN LIST_ENTRY *FeatureList IN LIST_ENTRY *FeatureList
); );
/** /**
@@ -242,7 +242,7 @@ DetectNoneNeighborhoodFeatureScope (
VOID VOID
EFIAPI EFIAPI
SetProcessorRegister ( SetProcessorRegister (
IN OUT VOID *Buffer IN OUT VOID *Buffer
); );
/** /**

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