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UefiCpuPkg: Apply uncrustify changes

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiCpuPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Michael Kubacki
2021-12-05 14:54:17 -08:00
committed by mergify[bot]
parent 91415a36ae
commit 053e878bfb
143 changed files with 14130 additions and 13035 deletions
Download Patch File Download Diff File Expand all files Collapse all files

209
UefiCpuPkg/Application/Cpuid/Cpuid.c
View File

@@ -221,7 +221,7 @@ CpuidVersionInfo (
}
DisplayModel = Eax.Bits.Model;
if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {
if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {
DisplayModel |= (Eax.Bits.ExtendedModelId << 4);
}
@@ -314,12 +314,14 @@ LookupCacheDescription (
if (CacheDescriptor == 0x00) {
return NULL;
}
NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);
for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {
if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {
return &mCpuidCacheInfoDescription[Descriptor];
}
}
return NULL;
}
@@ -354,13 +356,15 @@ CpuidCacheInfo (
for (Index = 1; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);
if (CacheDescription != NULL) {
Print (L" %-8a %a\n",
Print (
L" %-8a %a\n",
CacheDescription->Type,
CacheDescription->Description
);
}
}
}
if (Ebx.Bits.NotValid == 0) {
//
// Process Ebx.CacheDescriptor[0..3]
@@ -368,13 +372,15 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);
if (CacheDescription != NULL) {
Print (L" %-8a %a\n",
Print (
L" %-8a %a\n",
CacheDescription->Type,
CacheDescription->Description
);
}
}
}
if (Ecx.Bits.NotValid == 0) {
//
// Process Ecx.CacheDescriptor[0..3]
@@ -382,13 +388,15 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);
if (CacheDescription != NULL) {
Print (L" %-8a %a\n",
Print (
L" %-8a %a\n",
CacheDescription->Type,
CacheDescription->Description
);
}
}
}
if (Edx.Bits.NotValid == 0) {
//
// Process Edx.CacheDescriptor[0..3]
@@ -396,7 +404,8 @@ CpuidCacheInfo (
for (Index = 0; Index < 4; Index++) {
CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);
if (CacheDescription != NULL) {
Print (L" %-8a %a\n",
Print (
L" %-8a %a\n",
CacheDescription->Type,
CacheDescription->Description
);
@@ -457,8 +466,12 @@ CpuidCacheParams (
CacheLevel = 0;
do {
AsmCpuidEx (
CPUID_CACHE_PARAMS, CacheLevel,
&Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
CPUID_CACHE_PARAMS,
CacheLevel,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx,
&Edx.Uint32
);
if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {
Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);
@@ -477,6 +490,7 @@ CpuidCacheParams (
PRINT_BIT_FIELD (Edx, CacheInclusiveness);
PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);
}
CacheLevel++;
} while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
}
@@ -585,15 +599,21 @@ CpuidStructuredExtendedFeatureFlags (
AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
&Eax, NULL, NULL, NULL
&Eax,
NULL,
NULL,
NULL
);
for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
SubLeaf,
NULL, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
NULL,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
);
if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0 || Edx.Uint32 != 0) {
if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) {
Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
PRINT_BIT_FIELD (Ebx, FSGSBASE);
@@ -725,6 +745,7 @@ CpuidExtendedTopology (
if (LeafFunction > gMaximumBasicFunction) {
return;
}
if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {
return;
}
@@ -732,16 +753,22 @@ CpuidExtendedTopology (
LevelNumber = 0;
for (LevelNumber = 0; ; LevelNumber++) {
AsmCpuidEx (
LeafFunction, LevelNumber,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
LeafFunction,
LevelNumber,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx
);
if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break;
}
Print (
L"%a (Leaf %08x, Sub-Leaf %08x)\n",
LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",
LeafFunction, LevelNumber
LeafFunction,
LevelNumber
);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);
PRINT_BIT_FIELD (Eax, ApicIdShift);
@@ -767,8 +794,12 @@ CpuidExtendedStateSubLeaf (
UINT32 Edx;
AsmCpuidEx (
CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
CPUID_EXTENDED_STATE,
CPUID_EXTENDED_STATE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx
);
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);
@@ -801,8 +832,12 @@ CpuidExtendedStateSizeOffset (
for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
AsmCpuidEx (
CPUID_EXTENDED_STATE, SubLeaf,
&Eax, &Ebx, &Ecx.Uint32, &Edx
CPUID_EXTENDED_STATE,
SubLeaf,
&Eax,
&Ebx,
&Ecx.Uint32,
&Edx
);
if (Edx != 0) {
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);
@@ -834,8 +869,12 @@ CpuidExtendedStateMainLeaf (
}
AsmCpuidEx (
CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
&Eax.Uint32, &Ebx, &Ecx, &Edx
CPUID_EXTENDED_STATE,
CPUID_EXTENDED_STATE_MAIN_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx,
&Edx
);
Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);
@@ -872,8 +911,12 @@ CpuidIntelRdtMonitoringEnumerationSubLeaf (
}
AsmCpuidEx (
CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
NULL, &Ebx, NULL, &Edx.Uint32
CPUID_INTEL_RDT_MONITORING,
CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
NULL,
&Ebx,
NULL,
&Edx.Uint32
);
Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);
@@ -899,8 +942,12 @@ CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (
}
AsmCpuidEx (
CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
NULL, &Ebx, &Ecx, &Edx.Uint32
CPUID_INTEL_RDT_MONITORING,
CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
NULL,
&Ebx,
&Ecx,
&Edx.Uint32
);
Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);
@@ -927,8 +974,12 @@ CpuidIntelRdtAllocationMemoryBandwidthSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;
AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
CPUID_INTEL_RDT_ALLOCATION,
CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx.Uint32
);
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
@@ -954,8 +1005,12 @@ CpuidIntelRdtAllocationL3CacheSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
&Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
CPUID_INTEL_RDT_ALLOCATION,
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
&Ecx.Uint32,
&Edx.Uint32
);
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);
@@ -980,8 +1035,12 @@ CpuidIntelRdtAllocationL2CacheSubLeaf (
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;
AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
&Eax.Uint32, &Ebx, NULL, &Edx.Uint32
CPUID_INTEL_RDT_ALLOCATION,
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
&Eax.Uint32,
&Ebx,
NULL,
&Edx.Uint32
);
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
@@ -1006,8 +1065,12 @@ CpuidIntelRdtAllocationMainLeaf (
}
AsmCpuidEx (
CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
NULL, &Ebx.Uint32, NULL, NULL
CPUID_INTEL_RDT_ALLOCATION,
CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
NULL,
&Ebx.Uint32,
NULL,
NULL
);
Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", 0, Ebx.Uint32, 0, 0);
@@ -1033,8 +1096,12 @@ CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;
AsmCpuidEx (
CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
&Eax.Uint32, &Ebx, NULL, &Edx.Uint32
CPUID_INTEL_SGX,
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
&Eax.Uint32,
&Ebx,
NULL,
&Edx.Uint32
);
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);
@@ -1061,8 +1128,12 @@ CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (
UINT32 Edx;
AsmCpuidEx (
CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
&Eax, &Ebx, &Ecx, &Edx
CPUID_INTEL_SGX,
CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
&Eax,
&Ebx,
&Ecx,
&Edx
);
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx, Ecx, Edx);
@@ -1086,8 +1157,12 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf (
SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;
do {
AsmCpuidEx (
CPUID_INTEL_SGX, SubLeaf,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
CPUID_INTEL_SGX,
SubLeaf,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
);
if (Eax.Bits.SubLeafType == 0x1) {
Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);
@@ -1099,6 +1174,7 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf (
PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);
PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);
}
SubLeaf++;
} while (Eax.Bits.SubLeafType == 0x1);
}
@@ -1121,7 +1197,10 @@ CpuidEnumerationOfIntelSgx (
AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
NULL, &Ebx.Uint32, NULL, NULL
NULL,
&Ebx.Uint32,
NULL,
NULL
);
if (Ebx.Bits.SGX != 1) {
//
@@ -1153,8 +1232,12 @@ CpuidIntelProcessorTraceSubLeaf (
for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
AsmCpuidEx (
CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
&Eax.Uint32, &Ebx.Uint32, NULL, NULL
CPUID_INTEL_PROCESSOR_TRACE,
SubLeaf,
&Eax.Uint32,
&Ebx.Uint32,
NULL,
NULL
);
Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);
@@ -1183,8 +1266,12 @@ CpuidIntelProcessorTraceMainLeaf (
}
AsmCpuidEx (
CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
&Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
CPUID_INTEL_PROCESSOR_TRACE,
CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
&Eax,
&Ebx.Uint32,
&Ecx.Uint32,
NULL
);
Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);
@@ -1273,8 +1360,12 @@ CpuidSocVendorBrandString (
UINT32 BrandString[3 * 4 + 1];
AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
CPUID_SOC_VENDOR,
CPUID_SOC_VENDOR_BRAND_STRING1,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
);
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1284,8 +1375,12 @@ CpuidSocVendorBrandString (
BrandString[3] = Edx.Uint32;
AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
CPUID_SOC_VENDOR,
CPUID_SOC_VENDOR_BRAND_STRING2,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
);
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1295,8 +1390,12 @@ CpuidSocVendorBrandString (
BrandString[7] = Edx.Uint32;
AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
&Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
CPUID_SOC_VENDOR,
CPUID_SOC_VENDOR_BRAND_STRING3,
&Eax.Uint32,
&Ebx.Uint32,
&Ecx.Uint32,
&Edx.Uint32
);
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);
@@ -1329,8 +1428,12 @@ CpuidSocVendor (
}
AsmCpuidEx (
CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
&Eax, &Ebx.Uint32, &Ecx, &Edx
CPUID_SOC_VENDOR,
CPUID_SOC_VENDOR_MAIN_LEAF,
&Eax,
&Ebx.Uint32,
&Ecx,
&Edx
);
Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);
@@ -1338,6 +1441,7 @@ CpuidSocVendor (
Print (L" Not Supported\n");
return;
}
PRINT_VALUE (Eax, MaxSOCID_Index);
PRINT_BIT_FIELD (Ebx, SocVendorId);
PRINT_BIT_FIELD (Ebx, IsVendorScheme);
@@ -1367,7 +1471,10 @@ CpuidDeterministicAddressTranslationParameters (
AsmCpuidEx (
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
&Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32
&Eax,
&Ebx.Uint32,
&Ecx,
&Edx.Uint32
);
Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);
Print (L" EAX:%08x EBX:%08x ECX:%08x EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);

128
UefiCpuPkg/CpuDxe/CpuDxe.c
View File

@@ -79,7 +79,6 @@ FIXED_MTRR mFixedMtrrTable[] = {
},
};
EFI_CPU_ARCH_PROTOCOL gCpu = {
CpuFlushCpuDataCache,
CpuEnableInterrupt,
@@ -132,7 +131,6 @@ CpuFlushCpuDataCache (
}
}
/**
Enables CPU interrupts.
@@ -154,7 +152,6 @@ CpuEnableInterrupt (
return EFI_SUCCESS;
}
/**
Disables CPU interrupts.
@@ -176,7 +173,6 @@ CpuDisableInterrupt (
return EFI_SUCCESS;
}
/**
Return the state of interrupts.
@@ -202,7 +198,6 @@ CpuGetInterruptState (
return EFI_SUCCESS;
}
/**
Generates an INIT to the CPU.
@@ -225,7 +220,6 @@ CpuInit (
return EFI_UNSUPPORTED;
}
/**
Registers a function to be called from the CPU interrupt handler.
@@ -257,7 +251,6 @@ CpuRegisterInterruptHandler (
return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
}
/**
Returns a timer value from one of the CPU's internal timers. There is no
inherent time interval between ticks but is a function of the CPU frequency.
@@ -323,6 +316,7 @@ CpuGetTimerValue (
NULL
);
}
*TimerPeriod = mTimerPeriod;
}
@@ -450,6 +444,7 @@ CpuSetMemoryAttributes (
default:
return EFI_INVALID_PARAMETER;
}
CurrentCacheType = MtrrGetMemoryAttribute (BaseAddress);
if (CurrentCacheType != CacheType) {
//
@@ -484,6 +479,7 @@ CpuSetMemoryAttributes (
ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);
}
}
if (EFI_ERROR (Status)) {
return Status;
}
@@ -588,16 +584,20 @@ SearchGcdMemorySpaces (
*StartIndex = 0;
*EndIndex = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&
BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&
(BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))
{
*StartIndex = Index;
}
if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&
BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
if ((BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress) &&
(BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))
{
*EndIndex = Index;
return EFI_SUCCESS;
}
}
return EFI_NOT_FOUND;
}
@@ -655,6 +655,7 @@ SetGcdMemorySpaceAttributes (
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue;
}
//
// Calculate the start and end address of the overlapping range
//
@@ -663,11 +664,13 @@ SetGcdMemorySpaceAttributes (
} else {
RegionStart = MemorySpaceMap[Index].BaseAddress;
}
if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {
RegionLength = BaseAddress + Length - RegionStart;
} else {
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
}
//
// Set memory attributes according to MTRR attribute and the original attribute of descriptor
//
@@ -681,7 +684,6 @@ SetGcdMemorySpaceAttributes (
return EFI_SUCCESS;
}
/**
Refreshes the GCD Memory Space attributes according to MTRRs.
@@ -748,6 +750,7 @@ RefreshMemoryAttributesFromMtrr (
if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue;
}
gDS->SetMemorySpaceAttributes (
MemorySpaceMap[Index].BaseAddress,
MemorySpaceMap[Index].Length,
@@ -761,7 +764,8 @@ RefreshMemoryAttributesFromMtrr (
//
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {
(VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK))
{
SetGcdMemorySpaceAttributes (
MemorySpaceMap,
NumberOfDescriptors,
@@ -777,8 +781,9 @@ RefreshMemoryAttributesFromMtrr (
//
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&
VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {
(VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) &&
(VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE))
{
Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8)VariableMtrr[Index].Type);
SetGcdMemorySpaceAttributes (
MemorySpaceMap,
@@ -795,7 +800,8 @@ RefreshMemoryAttributesFromMtrr (
//
for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {
if (VariableMtrr[Index].Valid &&
VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {
(VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE))
{
SetGcdMemorySpaceAttributes (
MemorySpaceMap,
NumberOfDescriptors,
@@ -843,9 +849,11 @@ RefreshMemoryAttributesFromMtrr (
Attributes = CurrentAttributes;
}
}
Length += mFixedMtrrTable[Index].Length;
}
}
//
// Handle the last fixed MTRR region
//
@@ -922,14 +930,14 @@ InitInterruptDescriptorTable (
VectorInfo = NULL;
Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
if (Status == EFI_SUCCESS && VectorInfoList != NULL) {
if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {
VectorInfo = VectorInfoList;
}
Status = InitializeCpuInterruptHandlers (VectorInfo);
ASSERT_EFI_ERROR (Status);
}
/**
Callback function for idle events.
@@ -999,14 +1007,17 @@ IntersectMemoryDescriptor (
UINT64 IntersectionEnd;
EFI_STATUS Status;
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&
(Descriptor->Capabilities & Capabilities) == Capabilities) {
if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&
((Descriptor->Capabilities & Capabilities) == Capabilities))
{
return EFI_SUCCESS;
}
IntersectionBase = MAX (Base, Descriptor->BaseAddress);
IntersectionEnd = MIN (Base + Length,
Descriptor->BaseAddress + Descriptor->Length);
IntersectionEnd = MIN (
Base + Length,
Descriptor->BaseAddress + Descriptor->Length
);
if (IntersectionBase >= IntersectionEnd) {
//
// The descriptor and the aperture don't overlap.
@@ -1015,21 +1026,39 @@ IntersectMemoryDescriptor (
}
if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
IntersectionBase, IntersectionEnd - IntersectionBase,
Capabilities);
Status = gDS->AddMemorySpace (
EfiGcdMemoryTypeMemoryMappedIo,
IntersectionBase,
IntersectionEnd - IntersectionBase,
Capabilities
);
DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
"%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
IntersectionBase, IntersectionEnd, Status));
DEBUG ((
EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
"%a: %a: add [%Lx, %Lx): %r\n",
gEfiCallerBaseName,
__FUNCTION__,
IntersectionBase,
IntersectionEnd,
Status
));
return Status;
}
DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
"with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,
Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
(UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,
Base, Base + Length, Capabilities));
DEBUG ((
DEBUG_ERROR,
"%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
"with aperture [%Lx, %Lx) cap %Lx\n",
gEfiCallerBaseName,
__FUNCTION__,
Descriptor->BaseAddress,
Descriptor->BaseAddress + Descriptor->Length,
(UINT32)Descriptor->GcdMemoryType,
Descriptor->Capabilities,
Base,
Base + Length,
Capabilities
));
return EFI_INVALID_PARAMETER;
}
@@ -1058,14 +1087,23 @@ AddMemoryMappedIoSpace (
Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",
gEfiCallerBaseName, __FUNCTION__, Status));
DEBUG ((
DEBUG_ERROR,
"%a: %a: GetMemorySpaceMap(): %r\n",
gEfiCallerBaseName,
__FUNCTION__,
Status
));
return Status;
}
for (Index = 0; Index < NumberOfDescriptors; Index++) {
Status = IntersectMemoryDescriptor (Base, Length, Capabilities,
&MemorySpaceMap[Index]);
Status = IntersectMemoryDescriptor (
Base,
Length,
Capabilities,
&MemorySpaceMap[Index]
);
if (EFI_ERROR (Status)) {
goto FreeMemorySpaceMap;
}
@@ -1083,12 +1121,14 @@ AddMemoryMappedIoSpace (
for (CheckBase = Base;
CheckBase < Base + Length;
CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
CheckBase = Descriptor.BaseAddress + Descriptor.Length)
{
CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
ASSERT_EFI_ERROR (CheckStatus);
ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
}
DEBUG_CODE_END ();
FreeMemorySpaceMap:
@@ -1130,8 +1170,13 @@ AddLocalApicMemorySpace (
NULL
);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n",
gEfiCallerBaseName, __FUNCTION__, Status));
DEBUG ((
DEBUG_INFO,
"%a: %a: AllocateMemorySpace() Status - %r\n",
gEfiCallerBaseName,
__FUNCTION__,
Status
));
}
}
@@ -1180,7 +1225,8 @@ InitializeCpu (
//
Status = gBS->InstallMultipleProtocolInterfaces (
&mCpuHandle,
&gEfiCpuArchProtocolGuid, &gCpu,
&gEfiCpuArchProtocolGuid,
&gCpu,
NULL
);
ASSERT_EFI_ERROR (Status);

1
UefiCpuPkg/CpuDxe/CpuDxe.h
View File

@@ -297,4 +297,3 @@ extern BOOLEAN mIsAllocatingPageTable;
extern UINTN mNumberOfProcessors;
#endif

1
UefiCpuPkg/CpuDxe/CpuGdt.h
View File

@@ -65,4 +65,3 @@ struct _GDT_ENTRIES {
#endif
#endif // _CPU_GDT_H_

13
UefiCpuPkg/CpuDxe/CpuMp.c
View File

@@ -509,7 +509,7 @@ WhoAmI (
OUT UINTN *ProcessorNumber
)
{
return MpInitLibWhoAmI (ProcessorNumber);;
return MpInitLibWhoAmI (ProcessorNumber);
}
/**
@@ -583,6 +583,7 @@ CollectBistDataFromHob (
BistData = CpuInstance[CpuInstanceNumber].InfoRecord.IA32HealthFlags;
}
}
if (BistData.Uint32 != 0) {
//
// Report Status Code that self test is failed
@@ -758,10 +759,12 @@ InitializeMpExceptionStackSwitchHandlers (
EssData.Ia32.ExceptionTssDescSize);
EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;
DEBUG ((DEBUG_INFO,
DEBUG ((
DEBUG_INFO,
"Exception stack top[cpu%lu]: 0x%lX\n",
(UINT64)(UINTN)Index,
(UINT64)(UINTN)StackTop));
(UINT64)(UINTN)StackTop
));
if (Index == Bsp) {
InitializeExceptionStackSwitchHandlers (&EssData);
@@ -841,9 +844,9 @@ InitializeMpSupport (
Status = gBS->InstallMultipleProtocolInterfaces (
&mMpServiceHandle,
&gEfiMpServiceProtocolGuid, &mMpServicesTemplate,
&gEfiMpServiceProtocolGuid,
&mMpServicesTemplate,
NULL
);
ASSERT_EFI_ERROR (Status);
}

1
UefiCpuPkg/CpuDxe/CpuMp.h
View File

@@ -467,4 +467,3 @@ WhoAmI (
);
#endif // _CPU_MP_H_

71
UefiCpuPkg/CpuDxe/CpuPageTable.c
View File

@@ -179,15 +179,19 @@ GetCurrentPagingContext (
} else {
*PageTableBase = 0;
}
if (Cr0.Bits.WP != 0) {
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;
}
if (Cr4.Bits.PSE != 0) {
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;
}
if (Cr4.Bits.PAE != 0) {
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;
}
if (Cr4.Bits.LA57 != 0) {
*Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL;
}
@@ -231,11 +235,13 @@ PageAttributeToLength (
)
{
UINTN Index;
for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].Length;
}
}
return 0;
}
@@ -252,11 +258,13 @@ PageAttributeToMask (
)
{
UINTN Index;
for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].AddressMask;
}
}
return 0;
}
@@ -312,6 +320,7 @@ GetPageTableEntry (
} else {
L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;
}
if (L4PageTable[Index4] == 0) {
*PageAttribute = PageNone;
return NULL;
@@ -322,10 +331,12 @@ GetPageTableEntry (
ASSERT ((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0);
L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase;
}
if (L3PageTable[Index3] == 0) {
*PageAttribute = PageNone;
return NULL;
}
if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
// 1G
*PageAttribute = Page1G;
@@ -337,6 +348,7 @@ GetPageTableEntry (
*PageAttribute = PageNone;
return NULL;
}
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M
*PageAttribute = Page2M;
@@ -349,6 +361,7 @@ GetPageTableEntry (
*PageAttribute = PageNone;
return NULL;
}
*PageAttribute = Page4K;
return &L1PageTable[Index1];
}
@@ -366,16 +379,20 @@ GetAttributesFromPageEntry (
)
{
UINT64 Attributes;
Attributes = 0;
if ((*PageEntry & IA32_PG_P) == 0) {
Attributes |= EFI_MEMORY_RP;
}
if ((*PageEntry & IA32_PG_RW) == 0) {
Attributes |= EFI_MEMORY_RO;
}
if ((*PageEntry & IA32_PG_NX) != 0) {
Attributes |= EFI_MEMORY_XP;
}
return Attributes;
}
@@ -423,6 +440,7 @@ ConvertPageEntryAttribute (
break;
}
}
if ((Attributes & EFI_MEMORY_RO) != 0) {
switch (PageAction) {
case PageActionAssign:
@@ -468,6 +486,7 @@ ConvertPageEntryAttribute (
}
}
}
*PageEntry = NewPageEntry;
if (CurrentPageEntry != NewPageEntry) {
*IsModified = TRUE;
@@ -555,10 +574,12 @@ SplitPage (
if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
BaseAddress = *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MASK_64;
for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
}
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS);
return RETURN_SUCCESS;
} else {
@@ -570,16 +591,18 @@ SplitPage (
// No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.
//
ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);
if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) {
if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) {
NewPageEntry = AllocatePagesFunc (1);
DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));
if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
BaseAddress = *PageEntry & ~AddressEncMask & PAGING_1G_ADDRESS_MASK_64;
for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
}
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS);
return RETURN_SUCCESS;
} else {
@@ -603,6 +626,7 @@ IsReadOnlyPageWriteProtected (
)
{
IA32_CR0 Cr0;
//
// To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver.
@@ -611,6 +635,7 @@ IsReadOnlyPageWriteProtected (
Cr0.UintN = AsmReadCr0 ();
return (BOOLEAN)(Cr0.Bits.WP != 0);
}
return FALSE;
}
@@ -623,6 +648,7 @@ DisableReadOnlyPageWriteProtect (
)
{
IA32_CR0 Cr0;
//
// To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver.
@@ -643,6 +669,7 @@ EnableReadOnlyPageWriteProtect (
)
{
IA32_CR0 Cr0;
//
// To avoid unforseen consequences, don't touch paging settings in SMM mode
// in this driver.
@@ -708,10 +735,12 @@ ConvertMemoryPageAttributes (
DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddress));
return EFI_UNSUPPORTED;
}
if ((Length & (SIZE_4KB - 1)) != 0) {
DEBUG ((DEBUG_ERROR, "Length(0x%lx) is not aligned!\n", Length));
return EFI_UNSUPPORTED;
}
if (Length == 0) {
DEBUG ((DEBUG_ERROR, "Length is 0!\n"));
return RETURN_INVALID_PARAMETER;
@@ -727,6 +756,7 @@ ConvertMemoryPageAttributes (
} else {
CopyMem (&CurrentPagingContext, PagingContext, sizeof (CurrentPagingContext));
}
switch (CurrentPagingContext.MachineType) {
case IMAGE_FILE_MACHINE_I386:
if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) {
@@ -737,14 +767,17 @@ ConvertMemoryPageAttributes (
return EFI_UNSUPPORTED;
}
}
if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) {
DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n"));
return EFI_UNSUPPORTED;
}
if ((BaseAddress + Length) > BASE_4GB) {
DEBUG ((DEBUG_ERROR, "Beyond 4GB memory in 32-bit mode!\n"));
return EFI_UNSUPPORTED;
}
break;
case IMAGE_FILE_MACHINE_X64:
ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0);
@@ -760,9 +793,11 @@ ConvertMemoryPageAttributes (
if (IsSplitted != NULL) {
*IsSplitted = FALSE;
}
if (IsModified != NULL) {
*IsModified = FALSE;
}
if (AllocatePagesFunc == NULL) {
AllocatePagesFunc = AllocatePageTableMemory;
}
@@ -785,6 +820,7 @@ ConvertMemoryPageAttributes (
Status = RETURN_UNSUPPORTED;
goto Done;
}
PageEntryLength = PageAttributeToLength (PageAttribute);
SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);
if (SplitAttribute == PageNone) {
@@ -794,6 +830,7 @@ ConvertMemoryPageAttributes (
*IsModified = TRUE;
}
}
//
// Convert success, move to next
//
@@ -804,17 +841,21 @@ ConvertMemoryPageAttributes (
Status = RETURN_UNSUPPORTED;
goto Done;
}
Status = SplitPage (PageEntry, PageAttribute, SplitAttribute, AllocatePagesFunc);
if (RETURN_ERROR (Status)) {
Status = RETURN_UNSUPPORTED;
goto Done;
}
if (IsSplitted != NULL) {
*IsSplitted = TRUE;
}
if (IsModified != NULL) {
*IsModified = TRUE;
}
//
// Just split current page
// Convert success in next around
@@ -829,6 +870,7 @@ Done:
if (IsWpEnabled) {
EnableReadOnlyPageWriteProtect ();
}
return Status;
}
@@ -975,7 +1017,8 @@ RefreshGcdMemoryAttributesFromPaging (
DEBUG ((
DEBUG_WARN,
"Failed to update capability: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n",
(UINT64)Index, MemorySpaceMap[Index].BaseAddress,
(UINT64)Index,
MemorySpaceMap[Index].BaseAddress,
MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - 1,
MemorySpaceMap[Index].Capabilities,
MemorySpaceMap[Index].Capabilities | Capabilities
@@ -1018,7 +1061,8 @@ RefreshGcdMemoryAttributesFromPaging (
Length = MIN (PageLength, MemorySpaceLength);
if (Attributes != (MemorySpaceMap[Index].Attributes &
EFI_MEMORY_ATTRIBUTE_MASK)) {
EFI_MEMORY_ATTRIBUTE_MASK))
{
NewAttributes = (MemorySpaceMap[Index].Attributes &
~EFI_MEMORY_ATTRIBUTE_MASK) | Attributes;
Status = gDS->SetMemorySpaceAttributes (
@@ -1030,7 +1074,9 @@ RefreshGcdMemoryAttributesFromPaging (
DEBUG ((
DEBUG_VERBOSE,
"Updated memory space attribute: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n",
(UINT64)Index, BaseAddress, BaseAddress + Length - 1,
(UINT64)Index,
BaseAddress,
BaseAddress + Length - 1,
MemorySpaceMap[Index].Attributes,
NewAttributes
));
@@ -1169,8 +1215,9 @@ AllocatePageTableMemory (
//
// Renew the pool if necessary.
//
if (mPageTablePool == NULL ||
Pages > mPageTablePool->FreePages) {
if ((mPageTablePool == NULL) ||
(Pages > mPageTablePool->FreePages))
{
if (!InitializePageTablePool (Pages)) {
return NULL;
}
@@ -1295,8 +1342,13 @@ PageFaultExceptionHandler (
Attributes = GetAttributesFromPageEntry (PageEntry);
if ((Attributes & EFI_MEMORY_RP) != 0) {
Attributes &= ~EFI_MEMORY_RP;
Status = AssignMemoryPageAttributes (&PagingContext, PFAddress,
EFI_PAGE_SIZE, Attributes, NULL);
Status = AssignMemoryPageAttributes (
&PagingContext,
PFAddress,
EFI_PAGE_SIZE,
Attributes,
NULL
);
if (!EFI_ERROR (Status)) {
Index = mPFEntryCount[CpuIndex];
//
@@ -1357,7 +1409,8 @@ InitializePageTableLib (
// Reserve memory of page tables for future uses, if paging is enabled.
//
if ((*PageTableBase != 0) &&
(*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0) {
((*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0))
{
DisableReadOnlyPageWriteProtect ();
InitializePageTablePool (1);
EnableReadOnlyPageWriteProtect ();

1
UefiCpuPkg/CpuDxe/CpuPageTable.h
View File

@@ -57,7 +57,6 @@ typedef struct {
UINTN FreePages;
} PAGE_TABLE_POOL;
/**
Allocates one or more 4KB pages for page table.

3
UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c
View File

@@ -8,7 +8,6 @@
#include "CpuPageTable.h"
/**
Get paging details.
@@ -27,8 +26,8 @@ GetPagingDetails (
if (PageTableBase != NULL) {
*PageTableBase = &PagingContextData->Ia32.PageTableBase;
}
if (Attributes != NULL) {
*Attributes = &PagingContextData->Ia32.Attributes;
}
}

3
UefiCpuPkg/CpuDxe/X64/PagingAttribute.c
View File

@@ -8,7 +8,6 @@
#include "CpuPageTable.h"
/**
Get paging details.
@@ -27,8 +26,8 @@ GetPagingDetails (
if (PageTableBase != NULL) {
*PageTableBase = &PagingContextData->X64.PageTableBase;
}
if (Attributes != NULL) {
*Attributes = &PagingContextData->X64.Attributes;
}
}

2
UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
View File

@@ -18,7 +18,6 @@
#include <Protocol/SmmConfiguration.h>
#include <Guid/CpuFeaturesInitDone.h>
/**
Worker function to perform CPU feature initialization.
@@ -133,4 +132,3 @@ CpuFeaturesDxeInitialize (
return EFI_SUCCESS;
}

6
UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c
View File

@@ -46,8 +46,9 @@ CpuFeaturesPeimInitialize (
Status = PeiServicesGetBootMode (&BootMode);
ASSERT_EFI_ERROR (Status);
if (BootMode == BOOT_ON_S3_RESUME &&
!PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) {
if ((BootMode == BOOT_ON_S3_RESUME) &&
!PcdGetBool (PcdCpuFeaturesInitOnS3Resume))
{
//
// Does nothing when if PcdCpuFeaturesInitOnS3Resume is FLASE
// on S3 boot mode
@@ -72,4 +73,3 @@ CpuFeaturesPeimInitialize (
return EFI_SUCCESS;
}

8
UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
View File

@@ -120,7 +120,7 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access,
// so treat Count as 1
//
if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
Count = 1;
}
@@ -164,6 +164,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED;
}
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED;
}
@@ -257,6 +258,7 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
}
}
return EFI_SUCCESS;
}
@@ -337,6 +339,7 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
}
}
return EFI_SUCCESS;
}
@@ -573,7 +576,8 @@ CpuIo2Initialize (
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
Status = gBS->InstallMultipleProtocolInterfaces (
&mHandle,
&gEfiCpuIo2ProtocolGuid, &mCpuIo2,
&gEfiCpuIo2ProtocolGuid,
&mCpuIo2,
NULL
);
ASSERT_EFI_ERROR (Status);

3
UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c
View File

@@ -112,6 +112,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED;
}
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED;
}
@@ -184,6 +185,7 @@ CpuMemoryServiceRead (
*((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
}
}
return EFI_SUCCESS;
}
@@ -244,6 +246,7 @@ CpuMemoryServiceWrite (
MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
}
}
return EFI_SUCCESS;
}

5
UefiCpuPkg/CpuIoPei/CpuIoPei.c
View File

@@ -131,7 +131,7 @@ CpuIoCheckParameter (
// For FIFO type, the target address won't increase during the access,
// so treat Count as 1
//
if (Width >= EfiPeiCpuIoWidthFifoUint8 && Width <= EfiPeiCpuIoWidthFifoUint64) {
if ((Width >= EfiPeiCpuIoWidthFifoUint8) && (Width <= EfiPeiCpuIoWidthFifoUint64)) {
Count = 1;
}
@@ -168,6 +168,7 @@ CpuIoCheckParameter (
if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED;
}
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED;
}
@@ -247,6 +248,7 @@ CpuMemoryServiceRead (
}
}
}
return EFI_SUCCESS;
}
@@ -321,6 +323,7 @@ CpuMemoryServiceWrite (
}
}
}
return EFI_SUCCESS;
}

9
UefiCpuPkg/CpuMpPei/CpuBist.c
View File

@@ -134,6 +134,7 @@ GetBistInfoFromPpi (
if (BistInformationSize != NULL) {
*BistInformationSize = InformationSize;
}
return EFI_SUCCESS;
}
}
@@ -174,7 +175,6 @@ CollectBistDataFromPpi (
EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2;
EFI_SEC_PLATFORM_INFORMATION_CPU *CpuInstanceInHob;
MpInitLibGetNumberOfProcessors (&NumberOfProcessors, &NumberOfEnabledProcessors);
BistInformationSize = sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2) +
@@ -230,6 +230,7 @@ CollectBistDataFromPpi (
DEBUG ((DEBUG_INFO, "Does not find any stored CPU BIST information from PPI!\n"));
}
}
for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber++) {
MpInitLibGetProcessorInfo (ProcessorNumber, &ProcessorInfo, &BistData);
for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex++) {
@@ -241,6 +242,7 @@ CollectBistDataFromPpi (
BistData = CpuInstance[CpuIndex].InfoRecord.IA32HealthFlags;
}
}
if (BistData.Uint32 != 0) {
//
// Report Status Code that self test is failed
@@ -250,7 +252,10 @@ CollectBistDataFromPpi (
(EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST)
);
}
DEBUG ((DEBUG_INFO, " APICID - 0x%08x, BIST - 0x%08x\n",
DEBUG ((
DEBUG_INFO,
" APICID - 0x%08x, BIST - 0x%08x\n",
(UINT32)ProcessorInfo.ProcessorId,
BistData
));

1
UefiCpuPkg/CpuMpPei/CpuMp2Pei.c
View File

@@ -414,4 +414,3 @@ EDKII_PEI_MP_SERVICES2_PPI mMpServices2Ppi = {
EdkiiPeiWhoAmI,
EdkiiPeiStartupAllCPUs
};

7
UefiCpuPkg/CpuMpPei/CpuMpPei.c
View File

@@ -500,6 +500,7 @@ InitializeMpExceptionStackSwitchHandlers (
if (StackTop == NULL) {
return;
}
StackTop += NewStackSize * NumberOfProcessors;
//
@@ -592,10 +593,12 @@ InitializeMpExceptionStackSwitchHandlers (
EssData.Ia32.ExceptionTssDescSize);
EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;
DEBUG ((DEBUG_INFO,
DEBUG ((
DEBUG_INFO,
"Exception stack top[cpu%lu]: 0x%lX\n",
(UINT64)(UINTN)Index,
(UINT64)(UINTN)StackTop));
(UINT64)(UINTN)StackTop
));
if (Index == Bsp) {
InitializeExceptionStackSwitchHandlers (&EssData);

44
UefiCpuPkg/CpuMpPei/CpuPaging.c
View File

@@ -204,7 +204,7 @@ GetPageTableEntry (
//
// Page memory?
//
if ((PageTable[Index] & IA32_PG_PS) != 0 || Level == PageMin) {
if (((PageTable[Index] & IA32_PG_PS) != 0) || (Level == PageMin)) {
*PageAttribute = (PAGE_ATTRIBUTE)Level;
return &PageTable[Index];
}
@@ -247,7 +247,7 @@ SplitPage (
UINT64 AddressEncMask;
PAGE_ATTRIBUTE SplitTo;
if (SplitAttribute == PageNone || SplitAttribute >= PageAttribute) {
if ((SplitAttribute == PageNone) || (SplitAttribute >= PageAttribute)) {
ASSERT (SplitAttribute != PageNone);
ASSERT (SplitAttribute < PageAttribute);
return RETURN_INVALID_PARAMETER;
@@ -276,7 +276,7 @@ SplitPage (
NewPageEntry[Index] |= IA32_PG_PS;
}
if (Recursively && SplitTo > SplitAttribute) {
if (Recursively && (SplitTo > SplitAttribute)) {
SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively);
}
@@ -323,10 +323,10 @@ ConvertMemoryPageAttributes (
RETURN_STATUS Status;
EFI_PHYSICAL_ADDRESS MaximumAddress;
if (Length == 0 ||
(BaseAddress & (SIZE_4KB - 1)) != 0 ||
(Length & (SIZE_4KB - 1)) != 0) {
if ((Length == 0) ||
((BaseAddress & (SIZE_4KB - 1)) != 0) ||
((Length & (SIZE_4KB - 1)) != 0))
{
ASSERT (Length > 0);
ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
ASSERT ((Length & (SIZE_4KB - 1)) == 0);
@@ -335,9 +335,10 @@ ConvertMemoryPageAttributes (
}
MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32;
if (BaseAddress > MaximumAddress ||
Length > MaximumAddress ||
(BaseAddress > MaximumAddress - (Length - 1))) {
if ((BaseAddress > MaximumAddress) ||
(Length > MaximumAddress) ||
(BaseAddress > MaximumAddress - (Length - 1)))
{
return RETURN_UNSUPPORTED;
}
@@ -355,6 +356,7 @@ ConvertMemoryPageAttributes (
if (RETURN_ERROR (Status)) {
return Status;
}
//
// Do it again until the page is 4K.
//
@@ -470,7 +472,6 @@ CreatePageTable (
PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length;
}
return PageTable;
}
@@ -554,11 +555,15 @@ SetupStackGuardPage (
if (Index == Bsp) {
Hob.Raw = GetHobList ();
while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {
if (CompareGuid (&gEfiHobMemoryAllocStackGuid,
&(Hob.MemoryAllocationStack->AllocDescriptor.Name))) {
if (CompareGuid (
&gEfiHobMemoryAllocStackGuid,
&(Hob.MemoryAllocationStack->AllocDescriptor.Name)
))
{
StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress;
break;
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
} else {
@@ -567,13 +572,18 @@ SetupStackGuardPage (
//
MpInitLibStartupThisAP (GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);
}
ASSERT (StackBase != 0);
//
// Set Guard page at stack base address.
//
ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0);
DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n",
(UINT64)StackBase, (UINT64)Index));
DEBUG ((
DEBUG_INFO,
"Stack Guard set at %lx [cpu%lu]!\n",
(UINT64)StackBase,
(UINT64)Index
));
}
//
@@ -620,7 +630,7 @@ MemoryDiscoveredPpiNotifyCallback (
InitStackGuard = PcdGetBool (PcdCpuStackGuard);
}
if (InitStackGuard || Hob.Raw != NULL) {
if (InitStackGuard || (Hob.Raw != NULL)) {
EnablePaging ();
}
@@ -643,8 +653,8 @@ MemoryDiscoveredPpiNotifyCallback (
Hob.Raw = GET_NEXT_HOB (Hob);
Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw);
}
CpuFlushTlb ();
return Status;
}

1
UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
View File

@@ -95,6 +95,7 @@ AllocateZeroPages (
return Buffer;
}
/**
Callback function executed when the EndOfDxe event group is signaled.

2
UefiCpuPkg/Include/Library/LocalApicLib.h
View File

@@ -453,5 +453,5 @@ GetProcessorLocation2ByApicId (
OUT UINT32 *Core OPTIONAL,
OUT UINT32 *Thread OPTIONAL
);
#endif
#endif

7
UefiCpuPkg/Include/Library/MtrrLib.h
View File

@@ -168,7 +168,6 @@ MtrrSetMemoryAttribute (
IN MTRR_MEMORY_CACHE_TYPE Attribute
);
/**
This function will get the memory cache type of the specific address.
This function is mainly for debugging purposes.
@@ -184,7 +183,6 @@ MtrrGetMemoryAttribute (
IN PHYSICAL_ADDRESS Address
);
/**
This function gets the content in fixed MTRRs
@@ -199,7 +197,6 @@ MtrrGetFixedMtrr (
OUT MTRR_FIXED_SETTINGS *FixedSettings
);
/**
This function gets the content in all MTRRs (variable and fixed)
@@ -214,7 +211,6 @@ MtrrGetAllMtrrs (
OUT MTRR_SETTINGS *MtrrSetting
);
/**
This function sets all MTRRs (variable and fixed)
@@ -229,7 +225,6 @@ MtrrSetAllMtrrs (
IN MTRR_SETTINGS *MtrrSetting
);
/**
Get the attribute of variable MTRRs.
@@ -253,7 +248,6 @@ MtrrGetMemoryAttributeInVariableMtrr (
OUT VARIABLE_MTRR *VariableMtrr
);
/**
This function prints all MTRRs for debugging.
**/
@@ -361,4 +355,5 @@ MtrrSetMemoryAttributesInMtrrSettings (
IN CONST MTRR_MEMORY_RANGE *Ranges,
IN UINTN RangeCount
);
#endif // _MTRR_LIB_H_

2
UefiCpuPkg/Include/Library/UefiCpuLib.h
View File

@@ -13,8 +13,6 @@
#ifndef __UEFI_CPU_LIB_H__
#define __UEFI_CPU_LIB_H__
/**
Initializes floating point units for requirement of UEFI specification.

1
UefiCpuPkg/Include/Library/VmgExitLib.h
View File

@@ -15,7 +15,6 @@
#include <Protocol/DebugSupport.h>
#include <Register/Amd/Ghcb.h>
/**
Perform VMGEXIT.

1
UefiCpuPkg/Include/Ppi/MpServices2.h
View File

@@ -232,7 +232,6 @@ EFI_STATUS
OUT UINTN *ProcessorNumber
);
/**
Activate all of the application proessors.

1
UefiCpuPkg/Include/Ppi/ShadowMicrocode.h
View File

@@ -63,4 +63,3 @@ struct _EDKII_PEI_SHADOW_MICROCODE_PPI {
extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid;
#endif

1
UefiCpuPkg/Include/Register/LocalApic.h
View File

@@ -11,4 +11,3 @@
#include <Register/Intel/LocalApic.h>
#endif

26
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
View File

@@ -44,13 +44,14 @@ LocalApicBaseAddressMsrSupported (
AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) {
if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
//
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR
//
return FALSE;
}
return TRUE;
}
@@ -222,7 +223,6 @@ SendIpi (
WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState);
}
//
@@ -350,6 +350,7 @@ GetApicId (
ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);
ApicId >>= 24;
}
return ApicId;
}
@@ -752,6 +753,7 @@ InitializeApicTimer (
} else {
LvtTimer.Bits.TimerMode = 0;
}
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
@@ -792,7 +794,7 @@ GetApicTimerState (
*DivideValue = ((UINTN)1) << Divisor;
}
if (PeriodicMode != NULL || Vector != NULL) {
if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) {
@@ -801,6 +803,7 @@ GetApicTimerState (
*PeriodicMode = FALSE;
}
}
if (Vector != NULL) {
*Vector = (UINT8)LvtTimer.Bits.Vector;
}
@@ -944,6 +947,7 @@ GetApicMsiValue (
MsiData.Bits.Level = 1;
}
}
return MsiData.Uint64;
}
@@ -995,12 +999,15 @@ GetProcessorLocationByApicId (
if (Thread != NULL) {
*Thread = 0;
}
if (Core != NULL) {
*Core = 0;
}
if (Package != NULL) {
*Package = 0;
}
return;
}
@@ -1065,6 +1072,7 @@ GetProcessorLocationByApicId (
CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break;
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
}
@@ -1102,8 +1110,7 @@ GetProcessorLocationByApicId (
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
}
}
}
else {
} else {
//
// Extract core count based on CACHE information
//
@@ -1122,9 +1129,11 @@ GetProcessorLocationByApicId (
if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
}
@@ -1178,12 +1187,15 @@ GetProcessorLocation2ByApicId (
if (Die != NULL) {
*Die = 0;
}
if (Tile != NULL) {
*Tile = 0;
}
if (Module != NULL) {
*Module = 0;
}
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return;
}
@@ -1211,6 +1223,7 @@ GetProcessorLocation2ByApicId (
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break;
}
ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
}
@@ -1237,7 +1250,8 @@ GetProcessorLocation2ByApicId (
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
; LevelType++
) {
)
{
if (Location[LevelType] != NULL) {
//
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique

26
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
View File

@@ -45,13 +45,14 @@ LocalApicBaseAddressMsrSupported (
AsmCpuid (1, &RegEax, NULL, NULL, NULL);
FamilyId = BitFieldRead32 (RegEax, 8, 11);
if (FamilyId == 0x04 || FamilyId == 0x05) {
if ((FamilyId == 0x04) || (FamilyId == 0x05)) {
//
// CPUs with a FamilyId of 0x04 or 0x05 do not support the
// Local APIC Base Address MSR
//
return FALSE;
}
return TRUE;
}
@@ -271,7 +272,6 @@ SendIpi (
MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);
SetInterruptState (InterruptState);
} else {
//
// For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an
@@ -419,6 +419,7 @@ GetInitialApicId (
return ApicId;
}
}
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
return RegEbx >> 24;
} else {
@@ -847,6 +848,7 @@ InitializeApicTimer (
} else {
LvtTimer.Bits.TimerMode = 0;
}
LvtTimer.Bits.Mask = 0;
LvtTimer.Bits.Vector = Vector;
WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);
@@ -887,7 +889,7 @@ GetApicTimerState (
*DivideValue = ((UINTN)1) << Divisor;
}
if (PeriodicMode != NULL || Vector != NULL) {
if ((PeriodicMode != NULL) || (Vector != NULL)) {
LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);
if (PeriodicMode != NULL) {
if (LvtTimer.Bits.TimerMode == 1) {
@@ -896,6 +898,7 @@ GetApicTimerState (
*PeriodicMode = FALSE;
}
}
if (Vector != NULL) {
*Vector = (UINT8)LvtTimer.Bits.Vector;
}
@@ -1039,6 +1042,7 @@ GetApicMsiValue (
MsiData.Bits.Level = 1;
}
}
return MsiData.Uint64;
}
@@ -1090,12 +1094,15 @@ GetProcessorLocationByApicId (
if (Thread != NULL) {
*Thread = 0;
}
if (Core != NULL) {
*Core = 0;
}
if (Package != NULL) {
*Package = 0;
}
return;
}
@@ -1160,6 +1167,7 @@ GetProcessorLocationByApicId (
CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
break;
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
}
@@ -1197,8 +1205,7 @@ GetProcessorLocationByApicId (
MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
}
}
}
else {
} else {
//
// Extract core count based on CACHE information
//
@@ -1217,9 +1224,11 @@ GetProcessorLocationByApicId (
if (Thread != NULL) {
*Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
*Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
}
@@ -1273,12 +1282,15 @@ GetProcessorLocation2ByApicId (
if (Die != NULL) {
*Die = 0;
}
if (Tile != NULL) {
*Tile = 0;
}
if (Module != NULL) {
*Module = 0;
}
GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);
return;
}
@@ -1306,6 +1318,7 @@ GetProcessorLocation2ByApicId (
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {
break;
}
ASSERT (LevelType < ARRAY_SIZE (Bits));
Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;
}
@@ -1332,7 +1345,8 @@ GetProcessorLocation2ByApicId (
for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1
; LevelType++
) {
)
{
if (Location[LevelType] != NULL) {
//
// Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique

43
UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
View File

@@ -28,10 +28,20 @@ CpuCacheInfoPrintCpuCacheInfoTable (
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
for (Index = 0; Index < CpuCacheInfoCount; Index++) {
DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n",
Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,
CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache,
CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount));
DEBUG ((
DEBUG_INFO,
"| %4x | %4x %2x %2x %2x %4x ( %x| %x) %8x %4x |\n",
Index,
CpuCacheInfo[Index].Package,
CpuCacheInfo[Index].CoreType,
CpuCacheInfo[Index].CacheLevel,
CpuCacheInfo[Index].CacheType,
CpuCacheInfo[Index].CacheWays,
CpuCacheInfo[Index].FullyAssociativeCache,
CpuCacheInfo[Index].DirectMappedCache,
CpuCacheInfo[Index].CacheSizeinKB,
CpuCacheInfo[Index].CacheCount
));
}
DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));
@@ -320,12 +330,13 @@ CpuCacheInfoCollectCpuCacheInfoData (
continue;
}
if (CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel &&
CacheData[Index].CacheType == CacheData[NextIndex].CacheType &&
ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package &&
ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType &&
(ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) ==
(ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)) {
if ((CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel) &&
(CacheData[Index].CacheType == CacheData[NextIndex].CacheType) &&
(ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&
(ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&
((ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) ==
(ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)))
{
CacheData[NextIndex].CacheSizeinKB = 0; // uses the sharing cache
}
}
@@ -334,10 +345,11 @@ CpuCacheInfoCollectCpuCacheInfoData (
// For the cache that already exists in LocalCacheInfo, increase its CacheCount.
//
for (CacheInfoIndex = 0; CacheInfoIndex < LocalCacheInfoCount; CacheInfoIndex++) {
if (LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package &&
LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType &&
LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel &&
LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType) {
if ((LocalCacheInfo[CacheInfoIndex].Package == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&
(LocalCacheInfo[CacheInfoIndex].CoreType == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&
(LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel) &&
(LocalCacheInfo[CacheInfoIndex].CacheType == CacheData[Index].CacheType))
{
LocalCacheInfo[CacheInfoIndex].CacheCount++;
break;
}
@@ -421,7 +433,7 @@ GetCpuCacheInfo (
return EFI_INVALID_PARAMETER;
}
if (*CpuCacheInfoCount != 0 && CpuCacheInfo == NULL) {
if ((*CpuCacheInfoCount != 0) && (CpuCacheInfo == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -445,6 +457,7 @@ GetCpuCacheInfo (
if (Context.ProcessorInfo == NULL) {
return EFI_OUT_OF_RESOURCES;
}
//
// Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CacheData.
// CacheData array consists of CPUID_CACHE_DATA data structure for each Cpuid Cache Parameter Leaf

1
UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c
View File

@@ -58,6 +58,7 @@ CpuCacheInfoStartupAllCPUs (
//
Status = EFI_SUCCESS;
}
ASSERT_EFI_ERROR (Status);
Procedure (ProcedureArgument);

2
UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
View File

@@ -114,7 +114,6 @@ typedef struct {
CPUID_CACHE_DATA *CacheData;
} COLLECT_CPUID_CACHE_DATA_CONTEXT;
/*
Defines the maximum count of Deterministic Cache Parameters Leaf of all APs and BSP.
To save boot time, skip starting up all APs to calculate each AP's count of Deterministic
@@ -193,4 +192,5 @@ UINT32
CpuCacheInfoGetNumberOfProcessors (
IN MP_SERVICES MpServices
);
#endif

2
UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
View File

@@ -62,6 +62,7 @@ AesniSupport (
MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
return TRUE;
}
return FALSE;
}
@@ -115,5 +116,6 @@ AesniInitialize (
);
}
}
return RETURN_SUCCESS;
}

1
UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
View File

@@ -74,6 +74,7 @@ ClockModulationSupport (
CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
return TRUE;
}
return FALSE;
}

20
UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
View File

@@ -33,6 +33,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) {
Status = RegisterCpuFeature (
"MWAIT",
@@ -44,6 +45,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) {
Status = RegisterCpuFeature (
"ACPI",
@@ -55,6 +57,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) {
Status = RegisterCpuFeature (
"EIST",
@@ -66,6 +69,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) {
Status = RegisterCpuFeature (
"FastStrings",
@@ -77,6 +81,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {
Status = RegisterCpuFeature (
"Lock Feature Control Register",
@@ -88,6 +93,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {
Status = RegisterCpuFeature (
"SMX",
@@ -100,6 +106,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {
Status = RegisterCpuFeature (
"VMX",
@@ -112,6 +119,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) {
Status = RegisterCpuFeature (
"Limit CpuId Maximum Value",
@@ -123,6 +131,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) {
Status = RegisterCpuFeature (
"Machine Check Enable",
@@ -134,6 +143,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) {
Status = RegisterCpuFeature (
"Machine Check Architect",
@@ -145,6 +155,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) {
Status = RegisterCpuFeature (
"MCG_CTL",
@@ -156,6 +167,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) {
Status = RegisterCpuFeature (
"Pending Break",
@@ -167,6 +179,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) {
Status = RegisterCpuFeature (
"C1E",
@@ -178,6 +191,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
Status = RegisterCpuFeature (
"X2Apic",
@@ -189,6 +203,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) {
Status = RegisterCpuFeature (
"PPIN",
@@ -200,6 +215,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {
Status = RegisterCpuFeature (
"LMCE",
@@ -212,6 +228,7 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) {
Status = RegisterCpuFeature (
"Proc Trace",
@@ -226,6 +243,3 @@ CpuCommonFeaturesLibConstructor (
return RETURN_SUCCESS;
}

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
View File

@@ -69,7 +69,8 @@ EistInitialize (
//
if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
View File

@@ -40,7 +40,8 @@ FastStringsInitialize (
//
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}

9
UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
View File

@@ -68,7 +68,8 @@ VmxInitialize (
//
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
@@ -146,7 +147,8 @@ LockFeatureControlRegisterInitialize (
//
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
@@ -226,7 +228,8 @@ SmxInitialize (
// core.
//
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
View File

@@ -72,7 +72,8 @@ LimitCpuidMaxvalInitialize (
IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}

9
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
View File

@@ -102,6 +102,7 @@ McaSupport (
if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE;
}
return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);
}
@@ -144,7 +145,8 @@ McaInitialize (
IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
@@ -215,6 +217,7 @@ McgCtlSupport (
if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {
return FALSE;
}
McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
return (McgCap.Bits.MCG_CTL_P == 1);
}
@@ -289,6 +292,7 @@ LmceSupport (
if (ProcessorNumber == 0) {
DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0)));
}
return (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0);
}
@@ -325,7 +329,8 @@ LmceInitialize (
//
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
View File

@@ -70,7 +70,8 @@ MonitorMwaitInitialize (
IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}

4
UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
View File

@@ -36,9 +36,11 @@ PendingBreakSupport (
IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1);
}
return FALSE;
}

3
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
View File

@@ -65,7 +65,8 @@ PpinSupport (
(CpuInfo->DisplayModel == 0x55) || // Xeon Processor Scalable
(CpuInfo->DisplayModel == 0x57) || // Xeon Phi processor 3200, 5200, 7200 series.
(CpuInfo->DisplayModel == 0x85) // Future Xeon phi processor
)) {
))
{
//
// Check whether platform support this feature.
//

21
UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
View File

@@ -19,7 +19,6 @@
///
#define MAX_TOPA_ENTRY_COUNT 2
///
/// Processor trace output scheme selection.
///
@@ -117,7 +116,8 @@ ProcTraceSupport (
ProcTraceData = (PROC_TRACE_DATA *)ConfigData;
ASSERT (ProcTraceData != NULL);
if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||
(ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {
(ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA))
{
return FALSE;
}
@@ -133,7 +133,8 @@ ProcTraceSupport (
ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN)(Ecx.Bits.RTIT == 1);
ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1);
if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||
(ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {
(ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)))
{
ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
@@ -193,7 +194,8 @@ ProcTraceInitialize (
// MSR_IA32_RTIT_* for thread 0 in each core.
//
if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))
{
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
@@ -263,6 +265,7 @@ ProcTraceInitialize (
DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));
return RETURN_OUT_OF_RESOURCES;
}
ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;
for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {
@@ -279,6 +282,7 @@ ProcTraceInitialize (
ThreadMemRegionTable = NULL;
return RETURN_OUT_OF_RESOURCES;
}
break;
}
@@ -303,7 +307,8 @@ ProcTraceInitialize (
// Single Range output scheme
//
if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))
{
if (FirstIn) {
DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));
}
@@ -350,7 +355,8 @@ ProcTraceInitialize (
// ToPA(Table of physical address) scheme
//
if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {
(ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA))
{
//
// Create ToPA structure aligned at 4KB for each logical thread
// with at least 2 entries by 8 bytes size each. The first entry
@@ -369,6 +375,7 @@ ProcTraceInitialize (
DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));
return RETURN_OUT_OF_RESOURCES;
}
ProcTraceData->TopaMemArray = TopaMemArray;
for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {
@@ -379,6 +386,7 @@ ProcTraceInitialize (
if (Index < ProcTraceData->AllocatedThreads) {
ProcTraceData->AllocatedThreads = Index;
}
DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));
if (Index == 0) {
//
@@ -388,6 +396,7 @@ ProcTraceInitialize (
TopaMemArray = NULL;
return RETURN_OUT_OF_RESOURCES;
}
break;
}

1
UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
View File

@@ -133,5 +133,6 @@ X2ApicInitialize (
);
}
}
return RETURN_SUCCESS;
}

5
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
View File

@@ -134,6 +134,7 @@ DumpModuleImageInfo (
if (EFI_ERROR (Status)) {
EntryPoint = NULL;
}
InternalPrintMessage ("!!!! Find image based on IP(0x%x) ", CurrentEip);
PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);
if (PdbPointer != NULL) {
@@ -141,6 +142,7 @@ DumpModuleImageInfo (
} else {
InternalPrintMessage ("(No PDB) ");
}
InternalPrintMessage (
" (ImageBase=%016lp, EntryPoint=%016p) !!!!\n",
(VOID *)Pe32Data,
@@ -174,10 +176,13 @@ ReadAndVerifyVectorInfo (
//
return EFI_INVALID_PARAMETER;
}
if (VectorInfo->VectorNumber < VectorCount) {
ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute;
}
VectorInfo++;
}
return EFI_SUCCESS;
}

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
View File

@@ -318,4 +318,3 @@ AsmGetTssTemplateMap (
);
#endif

4
UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
View File

@@ -127,6 +127,7 @@ InitializeCpuInterruptHandlers (
if (IdtEntryCount > CPU_INTERRUPT_NUM) {
IdtEntryCount = CPU_INTERRUPT_NUM;
}
//
// Create Interrupt Descriptor Table and Copy the old IDT table in
//
@@ -246,7 +247,7 @@ InitializeCpuExceptionHandlersEx (
// version instead; or this method must be implemented as a simple wrapper of
// non-ex version of it, if this version has to be called.
//
if (InitData == NULL || InitData->X64.InitDefaultHandlers) {
if ((InitData == NULL) || InitData->X64.InitDefaultHandlers) {
Status = InitializeCpuExceptionHandlers (VectorInfo);
} else {
Status = EFI_SUCCESS;
@@ -279,6 +280,7 @@ InitializeCpuExceptionHandlersEx (
InitData = &EssData;
}
Status = ArchSetupExceptionStack (InitData);
}
}

44
UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
View File

@@ -131,17 +131,18 @@ ArchSetupExceptionStack (
UINTN GdtSize;
EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap;
if (StackSwitchData == NULL ||
StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||
StackSwitchData->Ia32.KnownGoodStackTop == 0 ||
StackSwitchData->Ia32.KnownGoodStackSize == 0 ||
StackSwitchData->Ia32.StackSwitchExceptions == NULL ||
StackSwitchData->Ia32.StackSwitchExceptionNumber == 0 ||
StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||
StackSwitchData->Ia32.GdtTable == NULL ||
StackSwitchData->Ia32.IdtTable == NULL ||
StackSwitchData->Ia32.ExceptionTssDesc == NULL ||
StackSwitchData->Ia32.ExceptionTss == NULL) {
if ((StackSwitchData == NULL) ||
(StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
(StackSwitchData->Ia32.KnownGoodStackTop == 0) ||
(StackSwitchData->Ia32.KnownGoodStackSize == 0) ||
(StackSwitchData->Ia32.StackSwitchExceptions == NULL) ||
(StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) ||
(StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
(StackSwitchData->Ia32.GdtTable == NULL) ||
(StackSwitchData->Ia32.IdtTable == NULL) ||
(StackSwitchData->Ia32.ExceptionTssDesc == NULL) ||
(StackSwitchData->Ia32.ExceptionTss == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -159,7 +160,8 @@ ArchSetupExceptionStack (
}
if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize >
((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) {
((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize))
{
return EFI_INVALID_PARAMETER;
}
@@ -168,11 +170,14 @@ ArchSetupExceptionStack (
// specified.
//
if (StackSwitchData->Ia32.ExceptionTssDescSize <
sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) {
sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))
{
return EFI_INVALID_PARAMETER;
}
if (StackSwitchData->Ia32.ExceptionTssSize <
sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) {
sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))
{
return EFI_INVALID_PARAMETER;
}
@@ -198,6 +203,7 @@ ArchSetupExceptionStack (
if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) {
Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable;
}
if (StackSwitchData->Ia32.IdtTableSize > 0) {
Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1);
}
@@ -246,8 +252,9 @@ ArchSetupExceptionStack (
// Fixup TSS
//
Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index];
if (Vector >= CPU_EXCEPTION_NUM ||
Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {
if ((Vector >= CPU_EXCEPTION_NUM) ||
(Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
{
continue;
}
@@ -331,8 +338,10 @@ DumpCpuContext (
(SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX) != 0
);
}
InternalPrintMessage ("\n");
}
InternalPrintMessage (
"EIP - %08x, CS - %08x, EFLAGS - %08x\n",
SystemContext.SystemContextIa32->Eip,
@@ -415,7 +424,8 @@ DumpImageAndCpuContent (
// Dump module image base and module entry point by EIP
//
if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&
((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)) {
((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0))
{
//
// The EIP in SystemContext could not be used
// if it is page fault with I/D set.

5
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
View File

@@ -62,6 +62,7 @@ SetExceptionHandlerData (
EXCEPTION0_STUB_HEADER *Exception0StubHeader;
IA32_DESCRIPTOR IdtDescriptor;
IA32_IDT_GATE_DESCRIPTOR *IdtTable;
//
// Duplicate the exception #0 stub header in pool and cache the ExceptionHandlerData just after the stub header.
// So AP can get the ExceptionHandlerData by reading the IDT[0].
@@ -243,7 +244,7 @@ InitializeCpuExceptionHandlersEx (
// version instead; or this method must be implemented as a simple wrapper of
// non-ex version of it, if this version has to be called.
//
if (InitData == NULL || InitData->Ia32.InitDefaultHandlers) {
if ((InitData == NULL) || InitData->Ia32.InitDefaultHandlers) {
Status = InitializeCpuExceptionHandlers (VectorInfo);
} else {
Status = EFI_SUCCESS;
@@ -253,7 +254,7 @@ InitializeCpuExceptionHandlersEx (
//
// Initializing stack switch is only necessary for Stack Guard functionality.
//
if (PcdGetBool (PcdCpuStackGuard) && InitData != NULL) {
if (PcdGetBool (PcdCpuStackGuard) && (InitData != NULL)) {
Status = ArchSetupExceptionStack (InitData);
}
}

19
UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
View File

@@ -75,6 +75,7 @@ CommonExceptionHandlerWorker (
ExceptionHandlerContext->OldIdtHandler = ReservedVectors[ExceptionType].ExceptonHandler;
return;
}
//
// If spin-lock cannot be acquired, it's the second time entering here.
// 'break' instead of 'return' is used so the new exception handler can be executed.
@@ -91,8 +92,10 @@ CommonExceptionHandlerWorker (
ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock);
break;
}
CpuPause ();
}
break;
case 0xffffffff:
break;
@@ -104,8 +107,9 @@ CommonExceptionHandlerWorker (
break;
}
if (ExternalInterruptHandler != NULL &&
ExternalInterruptHandler[ExceptionType] != NULL) {
if ((ExternalInterruptHandler != NULL) &&
(ExternalInterruptHandler[ExceptionType] != NULL))
{
(ExternalInterruptHandler[ExceptionType])(ExceptionType, SystemContext);
} else if (ExceptionType < CPU_EXCEPTION_NUM) {
//
@@ -114,6 +118,7 @@ CommonExceptionHandlerWorker (
while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) {
CpuPause ();
}
//
// Initialize the serial port before dumping.
//
@@ -295,20 +300,20 @@ RegisterCpuInterruptHandlerWorker (
ReservedVectors = ExceptionHandlerData->ReservedVectors;
ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;
if (InterruptType < 0 || InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum ||
ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) {
if ((InterruptType < 0) || (InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum) ||
(ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK))
{
return EFI_UNSUPPORTED;
}
if (InterruptHandler == NULL && ExternalInterruptHandler[InterruptType] == NULL) {
if ((InterruptHandler == NULL) && (ExternalInterruptHandler[InterruptType] == NULL)) {
return EFI_INVALID_PARAMETER;
}
if (InterruptHandler != NULL && ExternalInterruptHandler[InterruptType] != NULL) {
if ((InterruptHandler != NULL) && (ExternalInterruptHandler[InterruptType] != NULL)) {
return EFI_ALREADY_STARTED;
}
ExternalInterruptHandler[InterruptType] = InterruptHandler;
return EFI_SUCCESS;
}

4
UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
View File

@@ -99,6 +99,7 @@ InitializeCpuExceptionHandlers (
return EFI_INVALID_PARAMETER;
}
}
//
// Read IDT descriptor and calculate IDT size
//
@@ -110,6 +111,7 @@ InitializeCpuExceptionHandlers (
//
IdtEntryCount = CPU_EXCEPTION_NUM;
}
//
// Use current CS as the segment selector of interrupt gate in IDT
//
@@ -128,12 +130,14 @@ InitializeCpuExceptionHandlers (
continue;
}
}
//
// Update IDT entry
//
InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;
ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);
}
return EFI_SUCCESS;
}

1
UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
View File

@@ -19,6 +19,7 @@ SPIN_LOCK mDisplayMessageSpinLock;
RESERVED_VECTORS_DATA mReservedVectorsData[CPU_EXCEPTION_NUM];
EFI_CPU_INTERRUPT_HANDLER mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];
EXCEPTION_HANDLER_DATA mExceptionHandlerData;
/**
Common exception handler.

39
UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
View File

@@ -135,17 +135,18 @@ ArchSetupExceptionStack (
UINTN TssBase;
UINTN GdtSize;
if (StackSwitchData == NULL ||
StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||
StackSwitchData->X64.KnownGoodStackTop == 0 ||
StackSwitchData->X64.KnownGoodStackSize == 0 ||
StackSwitchData->X64.StackSwitchExceptions == NULL ||
StackSwitchData->X64.StackSwitchExceptionNumber == 0 ||
StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||
StackSwitchData->X64.GdtTable == NULL ||
StackSwitchData->X64.IdtTable == NULL ||
StackSwitchData->X64.ExceptionTssDesc == NULL ||
StackSwitchData->X64.ExceptionTss == NULL) {
if ((StackSwitchData == NULL) ||
(StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||
(StackSwitchData->X64.KnownGoodStackTop == 0) ||
(StackSwitchData->X64.KnownGoodStackSize == 0) ||
(StackSwitchData->X64.StackSwitchExceptions == NULL) ||
(StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||
(StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||
(StackSwitchData->X64.GdtTable == NULL) ||
(StackSwitchData->X64.IdtTable == NULL) ||
(StackSwitchData->X64.ExceptionTssDesc == NULL) ||
(StackSwitchData->X64.ExceptionTss == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -163,7 +164,8 @@ ArchSetupExceptionStack (
}
if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >
((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) {
((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))
{
return EFI_INVALID_PARAMETER;
}
@@ -173,6 +175,7 @@ ArchSetupExceptionStack (
if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {
return EFI_INVALID_PARAMETER;
}
if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {
return EFI_INVALID_PARAMETER;
}
@@ -203,6 +206,7 @@ ArchSetupExceptionStack (
if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {
Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;
}
if (StackSwitchData->X64.IdtTableSize > 0) {
Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);
}
@@ -242,10 +246,12 @@ ArchSetupExceptionStack (
// Set the IST field to enable corresponding IST
//
Vector = StackSwitchData->X64.StackSwitchExceptions[Index];
if (Vector >= CPU_EXCEPTION_NUM ||
Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {
if ((Vector >= CPU_EXCEPTION_NUM) ||
(Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))
{
continue;
}
IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);
}
@@ -304,8 +310,10 @@ DumpCpuContext (
(SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX) != 0
);
}
InternalPrintMessage ("\n");
}
InternalPrintMessage (
"RIP - %016lx, CS - %016lx, RFLAGS - %016lx\n",
SystemContext.SystemContextX64->Rip,
@@ -415,7 +423,8 @@ DumpImageAndCpuContent (
// Dump module image base and module entry point by RIP
//
if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&
((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0)) {
((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0))
{
//
// The RIP in SystemContext could not be used
// if it is page fault with I/D set.

1
UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
View File

@@ -38,4 +38,3 @@ InternalGetPerformanceCounterFrequency (
{
return CpuidCoreClockCalculateTscFrequency ();
}

10
UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
View File

@@ -13,7 +13,9 @@
#include <Library/DebugLib.h>
#include <Register/Cpuid.h>
GUID mCpuCrystalFrequencyHobGuid = { 0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a } };
GUID mCpuCrystalFrequencyHobGuid = {
0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a }
};
/**
Internal function to retrieves the 64-bit frequency in Hz.
@@ -57,11 +59,12 @@ CpuidCoreClockCalculateTscFrequency (
//
// If EAX or EBX returns 0, the XTAL ratio is not enumerated.
//
if (RegEax == 0 || RegEbx ==0 ) {
if ((RegEax == 0) || (RegEbx == 0)) {
ASSERT (RegEax != 0);
ASSERT (RegEbx != 0);
return 0;
}
//
// If ECX returns 0, the XTAL frequency is not enumerated.
// And PcdCpuCoreCrystalClockFrequency defined should base on processor series.
@@ -128,7 +131,6 @@ MicroSecondDelay (
IN UINTN MicroSeconds
)
{
InternalCpuDelay (
DivU64x32 (
MultU64x64 (
@@ -158,7 +160,6 @@ NanoSecondDelay (
IN UINTN NanoSeconds
)
{
InternalCpuDelay (
DivU64x32 (
MultU64x64 (
@@ -230,6 +231,7 @@ GetPerformanceCounterProperties (
if (EndValue != NULL) {
*EndValue = 0xffffffffffffffffULL;
}
return InternalGetPerformanceCounterFrequency ();
}

15
UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c
View File

@@ -82,6 +82,7 @@ GetMicrocodeLength (
if (Microcode->DataSize != 0) {
TotalSize = Microcode->TotalSize;
}
return TotalSize;
}
@@ -133,7 +134,8 @@ IsProcessorMatchedMicrocode (
for (Index = 0; Index < MicrocodeCpuIdCount; Index++) {
if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) &&
(ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0) {
((ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0))
{
return TRUE;
}
}
@@ -272,6 +274,7 @@ IsValidMicrocode (
if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) || ((ExtendedTableLength % 4) != 0)) {
return FALSE;
}
//
// Extended Table exist, check if the CPU in support list
//
@@ -279,10 +282,13 @@ IsValidMicrocode (
if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (CPU_MICROCODE_EXTENDED_TABLE)) {
return FALSE;
}
if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_EXTENDED_TABLE)
> ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) {
> ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER))
{
return FALSE;
}
//
// Check the extended table checksum
//
@@ -294,7 +300,8 @@ IsValidMicrocode (
for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index++) {
if (VerifyChecksum &&
(ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[Index].ProcessorFlag
+ ExtendedTable[Index].Checksum != Sum32)) {
+ ExtendedTable[Index].Checksum != Sum32))
{
//
// The extended table entry is valid when the summation of Processor Signature, Processor Flags
// and Checksum equal to the coresponding summation from primary header. Because:
@@ -308,6 +315,7 @@ IsValidMicrocode (
//
continue;
}
Match = IsProcessorMatchedMicrocode (
ExtendedTable[Index].ProcessorSignature.Uint32,
ExtendedTable[Index].ProcessorFlag,
@@ -318,5 +326,6 @@ IsValidMicrocode (
return TRUE;
}
}
return FALSE;
}

42
UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
View File

@@ -115,6 +115,7 @@ GetWakeupBuffer (
} else {
StartAddress = 0x88000;
}
Status = gBS->AllocatePages (
AllocateMaxAddress,
MemoryType,
@@ -131,8 +132,12 @@ GetWakeupBuffer (
mSevEsDxeWakeupBuffer = StartAddress;
}
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
(UINTN) StartAddress, WakeupBufferSize));
DEBUG ((
DEBUG_INFO,
"WakeupBufferStart = %x, WakeupBufferSize = %x\n",
(UINTN)StartAddress,
WakeupBufferSize
));
return (UINTN)StartAddress;
}
@@ -236,7 +241,6 @@ CheckAndUpdateApsStatus (
// First, check whether pending StartupAllAPs() exists.
//
if (CpuMpData->WaitEvent != NULL) {
Status = CheckAllAPs ();
//
// If all APs finish for StartupAllAPs(), signal the WaitEvent for it.
@@ -251,7 +255,6 @@ CheckAndUpdateApsStatus (
// Second, check whether pending StartupThisAPs() callings exist.
//
for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {
if (CpuMpData->CpuData[ProcessorNumber].WaitEvent == NULL) {
continue;
}
@@ -313,12 +316,14 @@ GetProtectedMode16CS (
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) {
if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 0) {
if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 0)) {
break;
}
}
GdtEntry++;
}
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -343,12 +348,14 @@ GetProtectedModeCS (
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) {
if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) {
if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {
break;
}
}
GdtEntry++;
}
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -378,6 +385,7 @@ RelocateApLoop (
} else {
StackStart = mReservedTopOfApStack;
}
AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFunc;
AsmRelocateApLoopFunc (
MwaitSupport,
@@ -485,7 +493,7 @@ InitMpGlobalData (
//
CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; ++Index) {
if (CpuInfoInHob != NULL && CpuInfoInHob[Index].ApTopOfStack != 0) {
if ((CpuInfoInHob != NULL) && (CpuInfoInHob[Index].ApTopOfStack != 0)) {
StackBase = (UINTN)CpuInfoInHob[Index].ApTopOfStack - CpuMpData->CpuApStackSize;
} else {
StackBase = CpuMpData->Buffer + Index * CpuMpData->CpuApStackSize;
@@ -501,8 +509,12 @@ InitMpGlobalData (
);
ASSERT_EFI_ERROR (Status);
DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n",
(UINT64)StackBase, (UINT64)Index));
DEBUG ((
DEBUG_INFO,
"Stack Guard set at %lx [cpu%lu]!\n",
(UINT64)StackBase,
(UINT64)Index
));
}
}
@@ -514,9 +526,11 @@ InitMpGlobalData (
// Allocating it in advance since memory services are not available in
// Exit Boot Services callback function.
//
ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (
ApSafeBufferSize = EFI_PAGES_TO_SIZE (
EFI_SIZE_TO_PAGES (
CpuMpData->AddressMap.RelocateApLoopFuncSize
));
)
);
Address = BASE_4GB - 1;
Status = gBS->AllocatePages (
AllocateMaxAddress,
@@ -545,9 +559,11 @@ InitMpGlobalData (
);
}
ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (
ApSafeBufferSize = EFI_PAGES_TO_SIZE (
EFI_SIZE_TO_PAGES (
CpuMpData->CpuCount * AP_SAFE_STACK_SIZE
));
)
);
Address = BASE_4GB - 1;
Status = gBS->AllocatePages (
AllocateMaxAddress,

22
UefiCpuPkg/Library/MpInitLib/Microcode.c
View File

@@ -55,7 +55,8 @@ MicrocodeDetect (
BspData = &(CpuMpData->CpuData[CpuMpData->BspNumber]);
if ((BspData->ProcessorSignature == MicrocodeCpuId.ProcessorSignature) &&
(BspData->PlatformId == MicrocodeCpuId.PlatformId) &&
(BspData->MicrocodeEntryAddr != 0)) {
(BspData->MicrocodeEntryAddr != 0))
{
LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN)BspData->MicrocodeEntryAddr;
LatestRevision = LatestMicrocode->UpdateRevision;
goto LoadMicrocode;
@@ -84,6 +85,7 @@ MicrocodeDetect (
Microcode = (CPU_MICROCODE_HEADER *)((UINTN)Microcode + SIZE_1KB);
continue;
}
LatestMicrocode = Microcode;
LatestRevision = LatestMicrocode->UpdateRevision;
@@ -109,6 +111,7 @@ LoadMicrocode:
//
LoadMicrocode (LatestMicrocode);
}
//
// It's possible that the microcode fails to load. Just capture the CPU microcode revision after loading.
//
@@ -167,7 +170,9 @@ ShadowMicrocodePatchWorker (
DEBUG ((
DEBUG_INFO,
"%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
__FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize
__FUNCTION__,
CpuMpData->MicrocodePatchAddress,
CpuMpData->MicrocodePatchRegionSize
));
return;
@@ -277,6 +282,7 @@ ShadowMicrocodePatchByPcd (
if (PatchInfoBuffer == NULL) {
goto OnExit;
}
MaxPatchNumber = MaxPatchNumber * 2;
}
@@ -299,7 +305,9 @@ ShadowMicrocodePatchByPcd (
DEBUG ((
DEBUG_INFO,
"%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n",
__FUNCTION__, PatchCount, TotalLoadSize
__FUNCTION__,
PatchCount,
TotalLoadSize
));
ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, TotalLoadSize);
@@ -309,6 +317,7 @@ OnExit:
if (PatchInfoBuffer != NULL) {
FreePool (PatchInfoBuffer);
}
FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDKII_PEI_MICROCODE_CPU_ID)));
}
@@ -366,8 +375,11 @@ GetMicrocodePatchInfoFromHob (
*RegionSize = MicrocodePathHob->MicrocodePatchRegionSize;
DEBUG ((
DEBUG_INFO, "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n",
__FUNCTION__, *Address, *RegionSize
DEBUG_INFO,
"%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n",
__FUNCTION__,
*Address,
*RegionSize
));
return TRUE;

105
UefiCpuPkg/Library/MpInitLib/MpLib.c
View File

@@ -15,7 +15,6 @@
EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;
/**
The function will check if BSP Execute Disable is enabled.
@@ -239,8 +238,9 @@ RestoreVolatileRegisters (
AsmWriteGdtr (&VolatileRegisters->Gdtr);
AsmWriteIdtr (&VolatileRegisters->Idtr);
if (VolatileRegisters->Tr != 0 &&
VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {
if ((VolatileRegisters->Tr != 0) &&
(VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit))
{
Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +
VolatileRegisters->Tr);
if (Tss->Bits.P == 1) {
@@ -355,6 +355,7 @@ SortApicId (
ApicId = CpuInfoInHob[Index2].ApicId;
}
}
if (Index3 != Index1) {
CopyMem (&CpuInfo, &CpuInfoInHob[Index3], sizeof (CPU_INFO_IN_HOB));
CopyMem (
@@ -525,6 +526,7 @@ CollectProcessorCount (
while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {
CpuPause ();
}
//
// Enable x2APIC on BSP
//
@@ -536,6 +538,7 @@ CollectProcessorCount (
SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);
}
}
DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ()));
//
// Sort BSP/Aps by CPU APIC ID in ascending order
@@ -618,13 +621,16 @@ GetProtectedMode16CS (
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0 &&
GdtEntry->Bits.DB == 0 &&
GdtEntry->Bits.Type > 8) {
if ((GdtEntry->Bits.L == 0) &&
(GdtEntry->Bits.DB == 0) &&
(GdtEntry->Bits.Type > 8))
{
break;
}
GdtEntry++;
}
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -651,13 +657,16 @@ GetProtectedMode32CS (
GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0 &&
GdtEntry->Bits.DB == 1 &&
GdtEntry->Bits.Type > 8) {
if ((GdtEntry->Bits.L == 0) &&
(GdtEntry->Bits.DB == 1) &&
(GdtEntry->Bits.Type > 8))
{
break;
}
GdtEntry++;
}
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -828,8 +837,9 @@ ApWakeupFunction (
ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;
CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;
} else {
if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () ||
CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()) {
if ((CpuInfoInHob[ProcessorNumber].ApicId != GetApicId ()) ||
(CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()))
{
if (CurrentApicMode != GetApicMode ()) {
//
// If APIC mode change happened during AP function execution,
@@ -847,6 +857,7 @@ ApWakeupFunction (
}
}
}
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateFinished);
}
}
@@ -928,9 +939,11 @@ ApWakeupFunction (
} else {
CpuSleep ();
}
CpuPause ();
}
}
while (TRUE) {
DisableInterrupts ();
if (CpuMpData->ApLoopMode == ApInMwaitLoop) {
@@ -984,7 +997,8 @@ WaitApWakeup (
(UINT32 *)ApStartupSignalBuffer,
WAKEUP_AP_SIGNAL,
WAKEUP_AP_SIGNAL
) != 0) {
) != 0)
{
CpuPause ();
}
}
@@ -1054,11 +1068,12 @@ FillExchangeInfoData (
Selector = (IA32_SEGMENT_DESCRIPTOR *)ExchangeInfo->GdtrProfile.Base;
Size = ExchangeInfo->GdtrProfile.Limit + 1;
while (Size > 0) {
if (Selector->Bits.L == 0 && Selector->Bits.Type >= 8) {
if ((Selector->Bits.L == 0) && (Selector->Bits.Type >= 8)) {
ExchangeInfo->ModeTransitionSegment =
(UINT16)((UINTN)Selector - ExchangeInfo->GdtrProfile.Base);
break;
}
Selector += 1;
Size -= sizeof (IA32_SEGMENT_DESCRIPTOR);
}
@@ -1228,6 +1243,7 @@ AllocateResetVector (
}
}
}
BackupAndPrepareWakeupBuffer (CpuMpData);
}
@@ -1348,7 +1364,8 @@ WakeUpAP (
ResetVectorRequired = FALSE;
if (CpuMpData->WakeUpByInitSipiSipi ||
CpuMpData->InitFlag != ApInitDone) {
(CpuMpData->InitFlag != ApInitDone))
{
ResetVectorRequired = TRUE;
AllocateResetVector (CpuMpData);
AllocateSevEsAPMemory (CpuMpData);
@@ -1375,7 +1392,7 @@ WakeUpAP (
// the AP procedure will be skipped for disabled AP because AP state
// is not CpuStateReady.
//
if (GetApState (CpuData) == CpuStateDisabled && !WakeUpDisabledAps) {
if ((GetApState (CpuData) == CpuStateDisabled) && !WakeUpDisabledAps) {
continue;
}
@@ -1387,6 +1404,7 @@ WakeUpAP (
}
}
}
if (ResetVectorRequired) {
//
// For SEV-ES, the initial AP boot address will be defined by
@@ -1402,6 +1420,7 @@ WakeUpAP (
//
SendInitSipiSipiAllExcludingSelf ((UINT32)ExchangeInfo->BufferStart);
}
if (CpuMpData->InitFlag == ApInitConfig) {
if (PcdGet32 (PcdCpuBootLogicalProcessorNumber) > 0) {
//
@@ -1503,6 +1522,7 @@ WakeUpAP (
(UINT32)ExchangeInfo->BufferStart
);
}
//
// Wait specified AP waken up
//
@@ -1628,25 +1648,30 @@ CheckTimeout (
if (Timeout == 0) {
return FALSE;
}
GetPerformanceCounterProperties (&Start, &End);
Cycle = End - Start;
if (Cycle < 0) {
Cycle = -Cycle;
}
Cycle++;
CurrentTime = GetPerformanceCounter ();
Delta = (INT64)(CurrentTime - *PreviousTime);
if (Start > End) {
Delta = -Delta;
}
if (Delta < 0) {
Delta += Cycle;
}
*TotalTime += Delta;
*PreviousTime = CurrentTime;
if (*TotalTime > Timeout) {
return TRUE;
}
return FALSE;
}
@@ -1683,7 +1708,8 @@ TimedWaitForApFinish (
&CpuMpData->CurrentTime,
&CpuMpData->TotalTime,
CpuMpData->ExpectedTime
)) {
))
{
CpuPause ();
}
@@ -1724,6 +1750,7 @@ ResetProcessorToIdleState (
while (CpuMpData->FinishedCount < 1) {
CpuPause ();
}
CpuMpData->InitFlag = ApInitDone;
SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);
@@ -1794,6 +1821,7 @@ CheckThisAP (
if (CpuData->Finished != NULL) {
*(CpuData->Finished) = TRUE;
}
SetApState (CpuData, CpuStateIdle);
return EFI_SUCCESS;
} else {
@@ -1804,6 +1832,7 @@ CheckThisAP (
if (CpuData->Finished != NULL) {
*(CpuData->Finished) = FALSE;
}
//
// Reset failed AP to idle state
//
@@ -1812,6 +1841,7 @@ CheckThisAP (
return EFI_TIMEOUT;
}
}
return EFI_NOT_READY;
}
@@ -1893,8 +1923,10 @@ CheckAllAPs (
if (CheckTimeout (
&CpuMpData->CurrentTime,
&CpuMpData->TotalTime,
CpuMpData->ExpectedTime)
) {
CpuMpData->ExpectedTime
)
)
{
//
// If FailedCpuList is not NULL, record all failed APs in it.
//
@@ -1903,6 +1935,7 @@ CheckAllAPs (
AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN));
ASSERT (*CpuMpData->FailedCpuList != NULL);
}
ListIndex = 0;
for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {
@@ -1920,11 +1953,14 @@ CheckAllAPs (
}
}
}
if (CpuMpData->FailedCpuList != NULL) {
(*CpuMpData->FailedCpuList)[ListIndex] = END_OF_CPU_LIST;
}
return EFI_TIMEOUT;
}
return EFI_NOT_READY;
}
@@ -1971,6 +2007,7 @@ MpInitLibInitialize (
} else {
MaxLogicalProcessorNumber = OldCpuMpData->CpuCount;
}
ASSERT (MaxLogicalProcessorNumber != 0);
AsmGetAddressMap (&AddressMap);
@@ -2039,8 +2076,10 @@ MpInitLibInitialize (
//
// Make sure no memory usage outside of the allocated buffer.
//
ASSERT ((CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) ==
Buffer + BufferSize);
ASSERT (
(CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) ==
Buffer + BufferSize
);
//
// Duplicate BSP's IDT to APs.
@@ -2076,6 +2115,7 @@ MpInitLibInitialize (
CpuMpData->CpuData[Index].StartupApSignal =
(UINT32 *)(MonitorBuffer + MonitorFilterSize * Index);
}
//
// Enable the local APIC for Virtual Wire Mode.
//
@@ -2108,7 +2148,8 @@ MpInitLibInitialize (
if (!GetMicrocodePatchInfoFromHob (
&CpuMpData->MicrocodePatchAddress,
&CpuMpData->MicrocodePatchRegionSize
)) {
))
{
//
// The microcode patch information cache HOB does not exist, which means
// the microcode patches data has not been loaded into memory yet
@@ -2137,6 +2178,7 @@ MpInitLibInitialize (
//
CpuMpData->InitFlag = ApInitReconfig;
}
WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE);
//
// Wait for all APs finished initialization
@@ -2144,9 +2186,11 @@ MpInitLibInitialize (
while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {
CpuPause ();
}
if (OldCpuMpData != NULL) {
CpuMpData->InitFlag = ApInitDone;
}
for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);
}
@@ -2158,6 +2202,7 @@ MpInitLibInitialize (
DEBUG_CODE_BEGIN ();
UINT32 ThreadId;
UINT32 ExpectedMicrocodeRevision;
CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;
for (Index = 0; Index < CpuMpData->CpuCount; Index++) {
GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId);
@@ -2170,12 +2215,17 @@ MpInitLibInitialize (
if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) {
ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision;
}
DEBUG ((
DEBUG_INFO, "CPU[%04d]: Microcode revision = %08x, expected = %08x\n",
Index, CpuMpData->CpuData[Index].MicrocodeRevision, ExpectedMicrocodeRevision
DEBUG_INFO,
"CPU[%04d]: Microcode revision = %08x, expected = %08x\n",
Index,
CpuMpData->CpuData[Index].MicrocodeRevision,
ExpectedMicrocodeRevision
));
}
}
DEBUG_CODE_END ();
//
// Initialize global data for MP support
@@ -2245,9 +2295,11 @@ MpInitLibGetProcessorInfo (
if (ProcessorNumber == CpuMpData->BspNumber) {
ProcessorInfoBuffer->StatusFlag |= PROCESSOR_AS_BSP_BIT;
}
if (CpuMpData->CpuData[ProcessorNumber].CpuHealthy) {
ProcessorInfoBuffer->StatusFlag |= PROCESSOR_HEALTH_STATUS_BIT;
}
if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateDisabled) {
ProcessorInfoBuffer->StatusFlag &= ~PROCESSOR_ENABLED_BIT;
} else {
@@ -2405,6 +2457,7 @@ SwitchBSPWorker (
} else {
SetApState (&CpuMpData->CpuData[CallerNumber], CpuStateIdle);
}
//
// Save new BSP number
//
@@ -2569,6 +2622,7 @@ MpInitLibGetNumberOfProcessors (
if (NumberOfProcessors != NULL) {
*NumberOfProcessors = ProcessorNumber;
}
if (NumberOfEnabledProcessors != NULL) {
*NumberOfEnabledProcessors = EnabledProcessorNumber;
}
@@ -2576,7 +2630,6 @@ MpInitLibGetNumberOfProcessors (
return EFI_SUCCESS;
}
/**
Worker function to execute a caller provided function on all enabled APs.
@@ -2635,7 +2688,7 @@ StartupAllCPUsWorker (
*FailedCpuList = NULL;
}
if (CpuMpData->CpuCount == 1 && ExcludeBsp) {
if ((CpuMpData->CpuCount == 1) && ExcludeBsp) {
return EFI_NOT_STARTED;
}
@@ -2719,6 +2772,7 @@ StartupAllCPUsWorker (
if (ProcessorNumber == CallerNumber) {
continue;
}
if (CpuMpData->CpuData[ProcessorNumber].Waiting) {
WakeUpAP (CpuMpData, FALSE, ProcessorNumber, Procedure, ProcedureArgument, TRUE);
break;
@@ -2875,6 +2929,7 @@ GetCpuMpDataFromGuidedHob (
DataInHob = GET_GUID_HOB_DATA (GuidHob);
CpuMpData = (CPU_MP_DATA *)(*(UINTN *)DataInHob);
}
return CpuMpData;
}

1
UefiCpuPkg/Library/MpInitLib/MpLib.h
View File

@@ -406,7 +406,6 @@ SaveCpuMpData (
IN CPU_MP_DATA *CpuMpData
);
/**
Get available system memory below 1MB by specified size.

28
UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
View File

@@ -31,7 +31,6 @@ NotifyOnS3SmmInitDonePpi (
IN VOID *InvokePpi
);
//
// Global function
//
@@ -76,7 +75,6 @@ NotifyOnS3SmmInitDonePpi (
return EFI_SUCCESS;
}
/**
Enable Debug Agent to support source debugging on AP function.
@@ -112,6 +110,7 @@ GetCpuMpData (
AsmReadIdtr (&Idtr);
CpuMpData = (CPU_MP_DATA *)(Idtr.Base + Idtr.Limit + 1);
}
return CpuMpData;
}
@@ -126,6 +125,7 @@ SaveCpuMpData (
)
{
UINT64 Data64;
//
// Build location of CPU MP DATA buffer in HOB
//
@@ -176,8 +176,10 @@ CheckOverlapWithAllocatedBuffer (
break;
}
}
Hob.Raw = GET_NEXT_HOB (Hob);
}
return Overlapped;
}
@@ -217,13 +219,15 @@ GetWakeupBuffer (
EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED |
EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED
)) == 0)
) {
)
{
//
// Need memory under 1MB to be collected here
//
WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;
if (PcdGetBool (PcdSevEsIsEnabled) &&
WakeupBufferEnd > mSevEsPeiWakeupBuffer) {
(WakeupBufferEnd > mSevEsPeiWakeupBuffer))
{
//
// SEV-ES Wakeup buffer should be under 1MB and under any previous one
//
@@ -234,6 +238,7 @@ GetWakeupBuffer (
//
WakeupBufferEnd = BASE_1MB;
}
while (WakeupBufferEnd > WakeupBufferSize) {
//
// Wakeup buffer should be aligned on 4KB
@@ -242,6 +247,7 @@ GetWakeupBuffer (
if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) {
break;
}
if (CheckOverlapWithAllocatedBuffer (WakeupBufferStart, WakeupBufferEnd)) {
//
// If this range is overlapped with existing allocated buffer, skip it
@@ -250,8 +256,13 @@ GetWakeupBuffer (
WakeupBufferEnd -= WakeupBufferSize;
continue;
}
DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart, WakeupBufferSize));
DEBUG ((
DEBUG_INFO,
"WakeupBufferStart = %x, WakeupBufferSize = %x\n",
WakeupBufferStart,
WakeupBufferSize
));
if (PcdGetBool (PcdSevEsIsEnabled)) {
//
@@ -265,6 +276,7 @@ GetWakeupBuffer (
}
}
}
//
// Find the next HOB
//
@@ -739,7 +751,9 @@ PlatformShadowMicrocode (
DEBUG ((
DEBUG_INFO,
"%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",
__FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize
__FUNCTION__,
CpuMpData->MicrocodePatchAddress,
CpuMpData->MicrocodePatchRegionSize
));
return EFI_SUCCESS;

4
UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
View File

@@ -103,9 +103,11 @@ MpInitLibGetProcessorInfo (
if (ProcessorInfoBuffer == NULL) {
return EFI_INVALID_PARAMETER;
}
if (ProcessorNumber != 0) {
return EFI_NOT_FOUND;
}
ProcessorInfoBuffer->ProcessorId = 0;
ProcessorInfoBuffer->StatusFlag = PROCESSOR_AS_BSP_BIT |
PROCESSOR_ENABLED_BIT |
@@ -123,6 +125,7 @@ MpInitLibGetProcessorInfo (
HealthData->Uint32 = 0;
}
}
return EFI_SUCCESS;
}
@@ -402,6 +405,7 @@ MpInitLibWhoAmI (
if (ProcessorNumber == NULL) {
return EFI_INVALID_PARAMETER;
}
*ProcessorNumber = 0;
return EFI_SUCCESS;
}

391
UefiCpuPkg/Library/MtrrLib/MtrrLib.c
View File

File diff suppressed because it is too large Load Diff

85
UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
View File

@@ -87,6 +87,7 @@ VerifyMemoryRanges (
)
{
UINTN Index;
UT_ASSERT_EQUAL (ExpectedMemoryRangeCount, ActualRangeCount);
for (Index = 0; Index < ExpectedMemoryRangeCount; Index++) {
UT_ASSERT_EQUAL (ExpectedMemoryRanges[Index].BaseAddress, ActualRanges[Index].BaseAddress);
@@ -110,6 +111,7 @@ DumpMemoryRanges (
)
{
UINTN Index;
for (Index = 0; Index < RangeCount; Index++) {
UT_LOG_INFO ("\t{ 0x%016llx, 0x%016llx, %a },\n", Ranges[Index].BaseAddress, Ranges[Index].Length, mCacheDescription[Ranges[Index].Type]);
}
@@ -210,11 +212,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
GenerateRandomMemoryTypeCombination (
SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),
&UcCount, &WtCount, &WbCount, &WpCount, &WcCount
&UcCount,
&WtCount,
&WbCount,
&WpCount,
&WcCount
);
GenerateValidAndConfigurableMtrrPairs (
SystemParameter->PhysicalAddressBits, RawMtrrRange,
UcCount, WtCount, WbCount, WpCount, WcCount
SystemParameter->PhysicalAddressBits,
RawMtrrRange,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
);
ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;
@@ -222,13 +233,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
GetEffectiveMemoryRanges (
SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits,
RawMtrrRange, ExpectedVariableMtrrUsage,
ExpectedMemoryRanges, &ExpectedMemoryRangesCount
RawMtrrRange,
ExpectedVariableMtrrUsage,
ExpectedMemoryRanges,
&ExpectedMemoryRangesCount
);
UT_LOG_INFO (
"Total MTRR [%d]: UC=%d, WT=%d, WB=%d, WP=%d, WC=%d\n",
ExpectedVariableMtrrUsage, UcCount, WtCount, WbCount, WpCount, WcCount
ExpectedVariableMtrrUsage,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
);
UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);
DumpMemoryRanges (ExpectedMemoryRanges, ExpectedMemoryRangesCount);
@@ -249,16 +267,23 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
Scratch = realloc (Scratch, ScratchSize);
Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);
}
UT_ASSERT_STATUS_EQUAL (Status, RETURN_SUCCESS);
if (Mtrrs[MtrrIndex] == NULL) {
ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));
MtrrGetAllMtrrs (&LocalMtrrs);
}
ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
CollectTestResult (
SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount,
&LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage
SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits,
SystemParameter->VariableMtrrCount,
&LocalMtrrs,
ActualMemoryRanges,
&ActualMemoryRangesCount,
&ActualVariableMtrrUsage
);
UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);
@@ -313,7 +338,9 @@ UnitTestInvalidMemoryLayouts (
Ranges[Index].Type = GenerateRandomCacheType ();
Status = MtrrSetMemoryAttribute (
Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type
Ranges[Index].BaseAddress,
Ranges[Index].Length,
Ranges[Index].Type
);
UT_ASSERT_TRUE (RETURN_ERROR (Status));
}
@@ -594,6 +621,7 @@ UnitTestMtrrGetFixedMtrr (
for (ByteIndex = 0; ByteIndex < sizeof (UINT64); ByteIndex++) {
MsrValue = MsrValue | LShiftU64 (GenerateRandomCacheType (), ByteIndex * 8);
}
ExpectedFixedSettings.Mtrr[MsrIndex] = MsrValue;
AsmWriteMsr64 (mFixedMtrrsIndex[MsrIndex], MsrValue);
}
@@ -652,6 +680,7 @@ UnitTestMtrrGetAllMtrrs (
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableMtrr[Index].Base);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableMtrr[Index].Mask);
}
Result = MtrrGetAllMtrrs (&Mtrrs);
UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);
UT_ASSERT_MEM_EQUAL (Mtrrs.Variables.Mtrr, VariableMtrr, sizeof (MTRR_VARIABLE_SETTING) * SystemParameter.VariableMtrrCount);
@@ -717,6 +746,7 @@ UnitTestMtrrSetAllMtrrs (
for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {
GenerateRandomMtrrPair (SystemParameter.PhysicalAddressBits, GenerateRandomCacheType (), &Mtrrs.Variables.Mtrr[Index], NULL);
}
Result = MtrrSetAllMtrrs (&Mtrrs);
UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);
@@ -770,6 +800,7 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting[Index].Base);
AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting[Index].Mask);
}
Result = MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr);
UT_ASSERT_EQUAL (Result, SystemParameter.VariableMtrrCount);
@@ -929,11 +960,20 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;
GenerateRandomMemoryTypeCombination (
SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),
&UcCount, &WtCount, &WbCount, &WpCount, &WcCount
&UcCount,
&WtCount,
&WbCount,
&WpCount,
&WcCount
);
GenerateValidAndConfigurableMtrrPairs (
SystemParameter->PhysicalAddressBits, RawMtrrRange,
UcCount, WtCount, WbCount, WpCount, WcCount
SystemParameter->PhysicalAddressBits,
RawMtrrRange,
UcCount,
WtCount,
WbCount,
WpCount,
WcCount
);
ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;
@@ -941,8 +981,10 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
GetEffectiveMemoryRanges (
SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits,
RawMtrrRange, ExpectedVariableMtrrUsage,
ExpectedMemoryRanges, &ExpectedMemoryRangesCount
RawMtrrRange,
ExpectedVariableMtrrUsage,
ExpectedMemoryRanges,
&ExpectedMemoryRangesCount
);
UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);
@@ -964,7 +1006,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
ExpectedMemoryRanges[Index].Type
);
UT_ASSERT_TRUE (Status == RETURN_SUCCESS || Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL);
if (Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL) {
if ((Status == RETURN_OUT_OF_RESOURCES) || (Status == RETURN_BUFFER_TOO_SMALL)) {
return UNIT_TEST_SKIPPED;
}
}
@@ -973,10 +1015,16 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));
MtrrGetAllMtrrs (&LocalMtrrs);
}
ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);
CollectTestResult (
SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount,
&LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage
SystemParameter->DefaultCacheType,
SystemParameter->PhysicalAddressBits,
SystemParameter->VariableMtrrCount,
&LocalMtrrs,
ActualMemoryRanges,
&ActualMemoryRangesCount,
&ActualVariableMtrrUsage
);
UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);
DumpMemoryRanges (ActualMemoryRanges, ActualMemoryRangesCount);
@@ -989,7 +1037,6 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
return UNIT_TEST_PASSED;
}
/**
Prep routine for UnitTestGetFirmwareVariableMtrrCount().
@@ -1077,6 +1124,7 @@ UnitTestingEntry (
Status = EFI_OUT_OF_RESOURCES;
goto EXIT;
}
AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context);
AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext);
@@ -1095,6 +1143,7 @@ UnitTestingEntry (
AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributesInMtrrSettings", "MtrrSetMemoryAttributesInMtrrSettings", UnitTestMtrrSetMemoryAttributesInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);
}
}
//
// Execute the tests.
//

1
UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
View File

@@ -192,4 +192,5 @@ GenerateRandomNumbers (
CHAR8 *FilePath,
UINTN Count
);
#endif

60
UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
View File

@@ -78,8 +78,10 @@ GenerateRandomNumbers (
if (Index % 10 == 0) {
fprintf (File, "\n ");
}
fprintf (File, " %d,", rand ());
}
fprintf (File, "\n};\n");
fclose (File);
}
@@ -124,18 +126,21 @@ UnitTestMtrrLibAsmCpuid (
if (Edx != NULL) {
*Edx = mCpuidVersionInfoEdx.Uint32;
}
return Index;
break;
case CPUID_EXTENDED_FUNCTION:
if (Eax != NULL) {
*Eax = CPUID_VIR_PHY_ADDRESS_SIZE;
}
return Index;
break;
case CPUID_VIR_PHY_ADDRESS_SIZE:
if (Eax != NULL) {
*Eax = mCpuidVirPhyAddressSizeEax.Uint32;
}
return Index;
break;
}
@@ -176,7 +181,8 @@ UnitTestMtrrLibAsmReadMsr64(
}
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) {
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
{
if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
return mVariableMtrrsPhysBase[Index].Uint64;
@@ -235,7 +241,8 @@ UnitTestMtrrLibAsmWriteMsr64(
}
if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) {
(MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))
{
if (MsrIndex % 2 == 0) {
Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;
mVariableMtrrsPhysBase[Index].Uint64 = Value;
@@ -468,7 +475,6 @@ GenerateRandomMtrrPair (
}
}
/**
Check whether the Range overlaps with any one in Ranges.
@@ -491,11 +497,13 @@ RangesOverlap (
// 1. range#2.base is in the middle of range#1
// 2. range#1.base is in the middle of range#2
//
if ((Range->BaseAddress <= Ranges[Count].BaseAddress && Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length)
|| (Ranges[Count].BaseAddress <= Range->BaseAddress && Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)) {
if ( ((Range->BaseAddress <= Ranges[Count].BaseAddress) && (Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length))
|| ((Ranges[Count].BaseAddress <= Range->BaseAddress) && (Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)))
{
return TRUE;
}
}
return FALSE;
}
@@ -591,6 +599,7 @@ CompareFuncUint64 (
)
{
INT64 Delta;
Delta = (*(UINT64 *)Left - *(UINT64 *)Right);
if (Delta > 0) {
return 1;
@@ -618,6 +627,7 @@ DetermineMemoryCacheType (
)
{
UINT32 Index;
Range->Type = CacheInvalid;
for (Index = 0; Index < RangeCount; Index++) {
if (RangesOverlap (Range, &Ranges[Index], 1)) {
@@ -649,10 +659,12 @@ GetNextDifferentElementInSortedArray (
)
{
UINT64 CurrentElement;
CurrentElement = Array[Index];
while (CurrentElement == Array[Index] && Index < Count) {
Index++;
}
return Index;
}
@@ -678,6 +690,7 @@ RemoveDuplicatesInSortedArray (
NewCount++;
Index = GetNextDifferentElementInSortedArray (Index, Array, *Count);
}
*Count = NewCount;
}
@@ -713,6 +726,7 @@ GetOverlapBitFlag (
{
UINT64 OverlapBitFlag;
UINT32 Index;
OverlapBitFlag = 0;
for (Index = 0; Index < RawMemoryRangeCount; Index++) {
if (AddressInRange (Address, RawMemoryRanges[Index])) {
@@ -740,9 +754,18 @@ CheckOverlapBitFlagsRelation (
IN UINT64 Flag2
)
{
if (Flag1 == Flag2) return 0;
if ((Flag1 | Flag2) == Flag2) return 1;
if ((Flag1 | Flag2) == Flag1) return 2;
if (Flag1 == Flag2) {
return 0;
}
if ((Flag1 | Flag2) == Flag2) {
return 1;
}
if ((Flag1 | Flag2) == Flag1) {
return 2;
}
return 3;
}
@@ -764,15 +787,16 @@ IsEndpointInRanges (
)
{
UINT32 Index;
for (Index = 0; Index < RangeCount; Index++) {
if (AddressInRange (Endpoint, Ranges[Index])) {
return TRUE;
}
}
return FALSE;
}
/**
Compact adjacent ranges of the same type.
@@ -815,21 +839,22 @@ CompactAndExtendEffectiveMtrrMemoryRanges (
while (OldRangesIndex < *EffectiveMtrrMemoryRangesCount) {
CurrentRangeTypeInOldRanges = OldRanges[OldRangesIndex].Type;
CurrentRangeInNewRanges = NULL;
if (NewRangesCountActual > 0) // We need to check CurrentNewRange first before generate a new NewRange.
{
if (NewRangesCountActual > 0) {
// We need to check CurrentNewRange first before generate a new NewRange.
CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1];
}
if (CurrentRangeInNewRanges != NULL && CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges) {
if ((CurrentRangeInNewRanges != NULL) && (CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges)) {
CurrentRangeInNewRanges->Length += OldRanges[OldRangesIndex].Length;
} else {
NewRanges[NewRangesCountActual].BaseAddress = OldRanges[OldRangesIndex].BaseAddress;
NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;
NewRanges[NewRangesCountActual].Type = CurrentRangeTypeInOldRanges;
while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges)
{
while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) {
OldRangesIndex++;
NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;
}
NewRangesCountActual++;
}
@@ -955,18 +980,23 @@ GetEffectiveMemoryRanges (
AllRangePieces[AllRangePiecesCountActual].Length = 1;
AllRangePiecesCountActual++;
}
break;
case 3: // (1, 2)
AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index] + 1;
AllRangePieces[AllRangePiecesCountActual].Length = (AllEndPointsInclusive[Index + 1] - 1) - (AllEndPointsInclusive[Index] + 1) + 1;
if (AllRangePieces[AllRangePiecesCountActual].Length == 0) // Only in case 3 can exists Length=0, we should skip such "segment".
if (AllRangePieces[AllRangePiecesCountActual].Length == 0) {
// Only in case 3 can exists Length=0, we should skip such "segment".
break;
}
AllRangePiecesCountActual++;
if (!IsEndpointInRanges (AllEndPointsInclusive[Index], AllRangePieces, AllRangePiecesCountActual)) {
AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index];
AllRangePieces[AllRangePiecesCountActual].Length = 1;
AllRangePiecesCountActual++;
}
break;
default:
ASSERT (FALSE);

44
UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
View File

@@ -71,7 +71,7 @@ FillProcessorInfo (
}
DisplayedModel = Eax.Bits.Model;
if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {
if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {
DisplayedModel |= (Eax.Bits.ExtendedModelId << 4);
}
@@ -143,6 +143,7 @@ CpuInitDataInitialize (
if (CpuFeature->GetConfigDataFunc != NULL) {
CpuFeature->ConfigData = CpuFeature->GetConfigDataFunc (NumberOfCpus);
}
Entry = Entry->ForwardLink;
}
@@ -182,12 +183,14 @@ CpuInitDataInitialize (
if (Package < ProcessorInfoBuffer.Location.Package) {
Package = ProcessorInfoBuffer.Location.Package;
}
//
// Collect CPU max core count info.
//
if (Core < ProcessorInfoBuffer.Location.Core) {
Core = ProcessorInfoBuffer.Location.Core;
}
//
// Collect CPU max thread count info.
//
@@ -195,13 +198,17 @@ CpuInitDataInitialize (
Thread = ProcessorInfoBuffer.Location.Thread;
}
}
CpuStatus->PackageCount = Package + 1;
CpuStatus->MaxCoreCount = Core + 1;
CpuStatus->MaxThreadCount = Thread + 1;
DEBUG ((DEBUG_INFO, "Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n",
DEBUG ((
DEBUG_INFO,
"Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n",
CpuStatus->PackageCount,
CpuStatus->MaxCoreCount,
CpuStatus->MaxThreadCount));
CpuStatus->MaxThreadCount
));
//
// Collect valid core count in each package because not all cores are valid.
@@ -228,7 +235,10 @@ CpuInitDataInitialize (
for (CoreIndex = 0; CoreIndex < CpuStatus->MaxCoreCount; CoreIndex++) {
if (ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex] != 0) {
DEBUG ((
DEBUG_INFO, " P%02d C%04d, Thread Count = %d\n", PackageIndex, CoreIndex,
DEBUG_INFO,
" P%02d C%04d, Thread Count = %d\n",
PackageIndex,
CoreIndex,
ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex]
));
}
@@ -300,6 +310,7 @@ CpuInitDataInitialize (
if (Location->Core == FirstCore[Location->Package]) {
CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Core = 1;
}
if (Location->Thread == FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]) {
CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Thread = 1;
}
@@ -416,6 +427,7 @@ IsBitMaskMatch (
return TRUE;
}
}
return FALSE;
}
@@ -462,6 +474,7 @@ CollectProcessorData (
CpuFeaturesData->BitMaskSize
);
}
Entry = Entry->ForwardLink;
}
}
@@ -626,6 +639,7 @@ AnalysisProcessorFeatures (
//
SupportedMaskAnd (CpuFeaturesData->CapabilityPcd, CpuInitOrder->FeaturesSupportedMask, CpuFeaturesData->BitMaskSize);
}
//
// Calculate the last setting
//
@@ -650,9 +664,11 @@ AnalysisProcessorFeatures (
} else {
DEBUG ((DEBUG_INFO, "[Unsupport] "));
}
DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize);
Entry = Entry->ForwardLink;
}
DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));
DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize);
DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n"));
@@ -680,8 +696,10 @@ AnalysisProcessorFeatures (
ASSERT (CpuFeatureInOrder != NULL);
InsertTailList (&CpuInitOrder->OrderList, &CpuFeatureInOrder->Link);
}
Entry = Entry->ForwardLink;
}
//
// Go through ordered feature list to initialize CPU features
//
@@ -742,6 +760,7 @@ AnalysisProcessorFeatures (
AfterDep = NoneDepType;
NoneNeibAfterDep = NoneDepType;
}
//
// Check whether current feature has Before type dependence with none neighborhood
// CPU features in after Cpu features.
@@ -839,6 +858,7 @@ ReadWriteCr (
} else {
AsmWriteCr0 (*CrValue);
}
break;
case 2:
if (Read) {
@@ -846,6 +866,7 @@ ReadWriteCr (
} else {
AsmWriteCr2 (*CrValue);
}
break;
case 3:
if (Read) {
@@ -853,6 +874,7 @@ ReadWriteCr (
} else {
AsmWriteCr3 (*CrValue);
}
break;
case 4:
if (Read) {
@@ -860,9 +882,10 @@ ReadWriteCr (
} else {
AsmWriteCr4 (*CrValue);
}
break;
default:
return EFI_UNSUPPORTED;;
return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
@@ -906,7 +929,6 @@ ProgramProcessorRegister (
RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
for (Index = 0; Index < RegisterTable->TableLength; Index++) {
RegisterTableEntry = &RegisterTableEntryHead[Index];
//
@@ -921,6 +943,7 @@ ProgramProcessorRegister (
if (EFI_ERROR (Status)) {
break;
}
if (RegisterTableEntry->TestThenWrite) {
CurrentValue = BitFieldRead64 (
Value,
@@ -931,6 +954,7 @@ ProgramProcessorRegister (
break;
}
}
Value = (UINTN)BitFieldWrite64 (
Value,
RegisterTableEntry->ValidBitStart,
@@ -981,6 +1005,7 @@ ProgramProcessorRegister (
RegisterTableEntry->Value
);
}
break;
//
// MemoryMapped operations
@@ -1007,6 +1032,7 @@ ProgramProcessorRegister (
} else {
AsmEnableCache ();
}
break;
case Semaphore:
@@ -1054,12 +1080,14 @@ ProgramProcessorRegister (
for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {
LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
}
//
// Second, check whether all VALID THREADs (not all threads) in current core are ready.
//
for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {
LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);
}
break;
case PackageDepType:
@@ -1092,17 +1120,20 @@ ProgramProcessorRegister (
for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {
LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
}
//
// Second, check whether VALID THREADS (not all threads) in current package are ready.
//
for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {
LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);
}
break;
default:
break;
}
break;
default:
@@ -1146,6 +1177,7 @@ SetProcessorRegister (
break;
}
}
ASSERT (RegisterTable != NULL);
ProgramProcessorRegister (

2
UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
View File

@@ -263,6 +263,7 @@ CpuFeaturesInitialize (
do {
Status = gBS->CheckEvent (MpEvent);
} while (Status == EFI_NOT_READY);
ASSERT_EFI_ERROR (Status);
}
@@ -273,4 +274,3 @@ CpuFeaturesInitialize (
SwitchNewBsp (CpuFeaturesData->BspNumber);
}
}

1
UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
View File

@@ -306,4 +306,3 @@ CpuFeaturesInitialize (
SwitchNewBsp (CpuFeaturesData->BspNumber);
}
}

99
UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
View File

@@ -28,6 +28,7 @@ DumpCpuFeatureMask (
for (Index = 0; Index < BitMaskSize; Index++) {
DEBUG ((DEBUG_INFO, " %02x ", *Data8++));
}
DEBUG ((DEBUG_INFO, "\n"));
}
@@ -44,7 +45,6 @@ DumpCpuFeature (
IN UINT32 BitMaskSize
)
{
if (CpuFeature->FeatureName != NULL) {
DEBUG ((DEBUG_INFO, "FeatureName: %a\n", CpuFeature->FeatureName));
} else {
@@ -82,6 +82,7 @@ IsBitMaskMatchCheck (
return TRUE;
}
}
return FALSE;
}
@@ -185,17 +186,20 @@ DetectFeatureScope (
if (Before) {
if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask)) {
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask))
{
return PackageDepType;
}
if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask)) {
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask))
{
return CoreDepType;
}
if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask)) {
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask))
{
return ThreadDepType;
}
@@ -203,17 +207,20 @@ DetectFeatureScope (
}
if ((CpuFeature->PackageAfterFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask)) {
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask))
{
return PackageDepType;
}
if ((CpuFeature->CoreAfterFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask)) {
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask))
{
return CoreDepType;
}
if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) &&
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask)) {
IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask))
{
return ThreadDepType;
}
@@ -238,17 +245,20 @@ DetectNoneNeighborhoodFeatureScope (
{
if (Before) {
if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask)) {
FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask))
{
return PackageDepType;
}
if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask)) {
FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask))
{
return CoreDepType;
}
if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask)) {
FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask))
{
return ThreadDepType;
}
@@ -256,17 +266,20 @@ DetectNoneNeighborhoodFeatureScope (
}
if ((CpuFeature->PackageAfterFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask)) {
FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask))
{
return PackageDepType;
}
if ((CpuFeature->CoreAfterFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask)) {
FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask))
{
return CoreDepType;
}
if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) &&
FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask)) {
FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask))
{
return ThreadDepType;
}
@@ -363,7 +376,6 @@ AdjustEntry (
if (Before) {
PreviousEntry = GetPreviousNode (FeatureList, FindEntry);
} else {
PreviousEntry = GetNextNode (FeatureList, FindEntry);
}
@@ -407,7 +419,6 @@ AdjustEntry (
}
}
/**
Checks and adjusts current CPU features per dependency relationship.
@@ -441,6 +452,7 @@ InsertToBeforeEntry (
Swapped = TRUE;
break;
}
CheckEntry = CheckEntry->ForwardLink;
}
@@ -480,6 +492,7 @@ InsertToAfterEntry (
Swapped = TRUE;
break;
}
CheckEntry = CheckEntry->ForwardLink;
}
@@ -526,8 +539,10 @@ CheckCpuFeaturesDependency (
Swapped = TRUE;
break;
}
CheckEntry = CheckEntry->ForwardLink;
}
if (Swapped) {
CurrentEntry = NextEntry;
continue;
@@ -553,8 +568,10 @@ CheckCpuFeaturesDependency (
Swapped = TRUE;
break;
}
CheckEntry = CheckEntry->ForwardLink;
}
if (Swapped) {
CurrentEntry = NextEntry;
continue;
@@ -643,6 +660,7 @@ RegisterCpuFeatureWorker (
FeatureExist = TRUE;
break;
}
Entry = Entry->ForwardLink;
}
@@ -661,55 +679,71 @@ RegisterCpuFeatureWorker (
if (CpuFeature->GetConfigDataFunc != NULL) {
CpuFeatureEntry->GetConfigDataFunc = CpuFeature->GetConfigDataFunc;
}
if (CpuFeature->SupportFunc != NULL) {
CpuFeatureEntry->SupportFunc = CpuFeature->SupportFunc;
}
if (CpuFeature->InitializeFunc != NULL) {
CpuFeatureEntry->InitializeFunc = CpuFeature->InitializeFunc;
}
if (CpuFeature->FeatureName != NULL) {
if (CpuFeatureEntry->FeatureName == NULL) {
CpuFeatureEntry->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE);
ASSERT (CpuFeatureEntry->FeatureName != NULL);
}
Status = AsciiStrCpyS (CpuFeatureEntry->FeatureName, CPU_FEATURE_NAME_SIZE, CpuFeature->FeatureName);
ASSERT_EFI_ERROR (Status);
FreePool (CpuFeature->FeatureName);
}
if (CpuFeature->ThreadBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->ThreadBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->ThreadBeforeFeatureBitMask);
}
CpuFeatureEntry->ThreadBeforeFeatureBitMask = CpuFeature->ThreadBeforeFeatureBitMask;
}
if (CpuFeature->ThreadAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->ThreadAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->ThreadAfterFeatureBitMask);
}
CpuFeatureEntry->ThreadAfterFeatureBitMask = CpuFeature->ThreadAfterFeatureBitMask;
}
if (CpuFeature->CoreBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->CoreBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->CoreBeforeFeatureBitMask);
}
CpuFeatureEntry->CoreBeforeFeatureBitMask = CpuFeature->CoreBeforeFeatureBitMask;
}
if (CpuFeature->CoreAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->CoreAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->CoreAfterFeatureBitMask);
}
CpuFeatureEntry->CoreAfterFeatureBitMask = CpuFeature->CoreAfterFeatureBitMask;
}
if (CpuFeature->PackageBeforeFeatureBitMask != NULL) {
if (CpuFeatureEntry->PackageBeforeFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->PackageBeforeFeatureBitMask);
}
CpuFeatureEntry->PackageBeforeFeatureBitMask = CpuFeature->PackageBeforeFeatureBitMask;
}
if (CpuFeature->PackageAfterFeatureBitMask != NULL) {
if (CpuFeatureEntry->PackageAfterFeatureBitMask != NULL) {
FreePool (CpuFeatureEntry->PackageAfterFeatureBitMask);
}
CpuFeatureEntry->PackageAfterFeatureBitMask = CpuFeature->PackageAfterFeatureBitMask;
}
@@ -719,6 +753,7 @@ RegisterCpuFeatureWorker (
FreePool (CpuFeature->FeatureMask);
FreePool (CpuFeature);
}
//
// Verify CPU features dependency can change CPU feature order
//
@@ -853,19 +888,27 @@ RegisterCpuFeature (
//
// It's invalid to require a feature is before AND after all other features.
//
ASSERT ((Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL))
!= (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL));
ASSERT (
(Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL))
!= (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)
);
//
// It's invalid to require feature A is before AND after before feature B,
// either in thread level, core level or package level.
//
ASSERT ((Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER))
!= (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER));
ASSERT ((Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER))
!= (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER));
ASSERT ((Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))
!= (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER));
ASSERT (
(Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER))
!= (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)
);
ASSERT (
(Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER))
!= (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)
);
ASSERT (
(Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))
!= (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)
);
if (Feature < CPU_FEATURE_THREAD_BEFORE) {
BeforeAll = ((Feature & CPU_FEATURE_BEFORE_ALL) != 0) ? TRUE : FALSE;
AfterAll = ((Feature & CPU_FEATURE_AFTER_ALL) != 0) ? TRUE : FALSE;
@@ -885,8 +928,10 @@ RegisterCpuFeature (
} else if ((Feature & CPU_FEATURE_PACKAGE_AFTER) != 0) {
SetCpuFeaturesBitMask (&PackageAfterFeatureBitMask, Feature & ~CPU_FEATURE_PACKAGE_AFTER, CpuFeaturesData->BitMaskSize);
}
Feature = VA_ARG (Marker, UINT32);
}
VA_END (Marker);
CpuFeature = AllocateZeroPool (sizeof (CPU_FEATURES_ENTRY));
@@ -952,8 +997,9 @@ GetAcpiCpuData (
AcpiCpuData->NumberOfCpus = (UINT32)NumberOfCpus;
}
if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0 ||
AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) {
if ((AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) ||
(AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0))
{
//
// Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for all CPUs
//
@@ -976,9 +1022,11 @@ GetAcpiCpuData (
RegisterTable[NumberOfCpus + Index].AllocatedSize = 0;
RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;
}
if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) {
AcpiCpuData->CpuFeatureInitData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;
}
if (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) {
AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);
}
@@ -1216,6 +1264,7 @@ IsCpuFeatureSetInCpuPcd (
if ((Feature >> 3) >= CpuBitMaskSize) {
return FALSE;
}
return ((*(CpuBitMask + (Feature >> 3)) & (1 << (Feature & 0x07))) != 0);
}

31
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
View File

@@ -86,7 +86,7 @@ CpuFeaturesLibInitialization (
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf;
if (FamilyId == 0x06 || FamilyId == 0x0f) {
if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
}
@@ -110,7 +110,7 @@ CpuFeaturesLibInitialization (
// SMRR Physical Base and SMM Physical Mask MSRs are not available.
//
if (FamilyId == 0x06) {
if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {
if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {
mSmrrSupported = FALSE;
}
}
@@ -123,7 +123,7 @@ CpuFeaturesLibInitialization (
// Processor Family MSRs
//
if (FamilyId == 0x06) {
if (ModelId == 0x17 || ModelId == 0x0f) {
if ((ModelId == 0x17) || (ModelId == 0x0f)) {
mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;
mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;
}
@@ -216,7 +216,7 @@ SmmCpuFeaturesInitializeProcessor (
// accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)
// is set, then the MSR is locked and can not be modified.
//
if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {
if (mSmrrSupported && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {
FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);
if ((FeatureControl & BIT3) == 0) {
if ((FeatureControl & BIT0) == 0) {
@@ -242,7 +242,8 @@ SmmCpuFeaturesInitializeProcessor (
//
if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||
(CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||
((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {
((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))
{
//
// Print message and halt if CPU is Monarch
//
@@ -263,7 +264,7 @@ SmmCpuFeaturesInitializeProcessor (
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf;
if (FamilyId == 0x06 || FamilyId == 0x0f) {
if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
}
@@ -276,10 +277,11 @@ SmmCpuFeaturesInitializeProcessor (
// Intel(R) Core(TM) Processor Family MSRs.
//
if (FamilyId == 0x06) {
if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||
ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F ||
ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C ||
ModelId == 0x8C) {
if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) ||
(ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) ||
(ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) ||
(ModelId == 0x8C))
{
//
// Check to see if the CPU supports the SMM Code Access Check feature
// Do not access this MSR unless the CPU supports the SmmRegFeatureControl
@@ -458,9 +460,10 @@ SmmCpuFeaturesIsSmmRegisterSupported (
IN SMM_REG_NAME RegName
)
{
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
return TRUE;
}
return FALSE;
}
@@ -483,9 +486,10 @@ SmmCpuFeaturesGetSmmRegister (
IN SMM_REG_NAME RegName
)
{
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);
}
return 0;
}
@@ -508,7 +512,7 @@ SmmCpuFeaturesSetSmmRegister (
IN UINT64 Value
)
{
if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {
if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {
AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);
}
}
@@ -610,4 +614,3 @@ SmmCpuFeaturesAllocatePageTableMemory (
{
return NULL;
}

36
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
View File

@@ -60,9 +60,6 @@ EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = {
GetMonitorState,
};
#define CPUID1_EDX_XD_SUPPORT 0x100000
//
@@ -162,6 +159,7 @@ SmmCpuFeaturesLibStmConstructor (
DEBUG ((DEBUG_ERROR, "Not enough SMRAM resource to allocate MSEG size %08x\n", PcdGet32 (PcdCpuMsegSize)));
}
}
if (mMsegBase > 0) {
DEBUG ((DEBUG_INFO, "MsegBase: 0x%08x, MsegSize: 0x%08x\n", mMsegBase, mMsegSize));
}
@@ -385,6 +383,7 @@ SmmEndOfDxeEventNotify (
break;
}
}
if (Rsdp == NULL) {
for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), &gEfiAcpi10TableGuid)) {
@@ -502,6 +501,7 @@ HandleSingleResource (
return FALSE;
}
}
break;
case IO_RANGE:
case TRAPPED_IO_RANGE:
@@ -512,12 +512,15 @@ HandleSingleResource (
break;
case PCI_CFG_RANGE:
if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) ||
(Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) {
(Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex))
{
return FALSE;
}
if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof (STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {
return FALSE;
}
ResourceLo = (UINT64)Resource->PciCfg.Base;
ResourceHi = (UINT64)Resource->PciCfg.Base + (UINT64)Resource->PciCfg.Length;
RecordLo = (UINT64)Record->PciCfg.Base;
@@ -530,6 +533,7 @@ HandleSingleResource (
return FALSE;
}
}
break;
case MACHINE_SPECIFIC_REG:
//
@@ -538,12 +542,14 @@ HandleSingleResource (
if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) {
return FALSE;
}
Record->Msr.ReadMask |= Resource->Msr.ReadMask;
Record->Msr.WriteMask |= Resource->Msr.WriteMask;
return TRUE;
default:
return FALSE;
}
//
// If resources are disjoint
//
@@ -557,6 +563,7 @@ HandleSingleResource (
if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) {
return TRUE;
}
//
// Resources are overlapping.
// Resource and record are merged.
@@ -606,6 +613,7 @@ AddSingleResource (
if (Record->Header.RscType == END_OF_RESOURCES) {
break;
}
//
// Go to next record if resource and record types don't match.
//
@@ -613,12 +621,14 @@ AddSingleResource (
Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);
continue;
}
//
// Record is handled inside of procedure - don't adjust.
//
if (HandleSingleResource (Resource, Record)) {
return;
}
Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);
}
@@ -672,9 +682,11 @@ AddResource (
if (Resource->Header.RscType == END_OF_RESOURCES) {
return;
}
AddSingleResource (Resource);
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
}
return;
}
@@ -726,6 +738,7 @@ ValidateResource (
if (Resource->Header.Length != sizeof (STM_RSC_END)) {
return FALSE;
}
//
// If we are passed actual number of resources to add,
// END_OF_RESOURCES structure between them is considered an
@@ -739,6 +752,7 @@ ValidateResource (
//
return TRUE;
}
break;
case MEM_RANGE:
@@ -750,6 +764,7 @@ ValidateResource (
if (Resource->Mem.RWXAttributes > FULL_ACCS) {
return FALSE;
}
break;
case IO_RANGE:
@@ -761,6 +776,7 @@ ValidateResource (
if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) {
return FALSE;
}
break;
case PCI_CFG_RANGE:
@@ -768,28 +784,34 @@ ValidateResource (
if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof (STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {
return FALSE;
}
for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) {
if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) {
return FALSE;
}
}
if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) {
return FALSE;
}
break;
case MACHINE_SPECIFIC_REG:
if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) {
return FALSE;
}
break;
default:
DEBUG ((DEBUG_ERROR, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType));
return FALSE;
}
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
}
return TRUE;
}
@@ -837,6 +859,7 @@ GetResourceSize (
if (Resource->Header.RscType == END_OF_RESOURCES) {
break;
}
Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);
}
@@ -925,6 +948,7 @@ AddPiResource (
if (EFI_ERROR (Status)) {
return Status;
}
CopyMem ((VOID *)(UINTN)NewResource, mStmResourcesPtr, mStmResourceSizeUsed);
mStmResourceSizeAvailable = NewResourceSize - mStmResourceSizeUsed;
@@ -975,6 +999,7 @@ DeletePiResource (
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
//
// Delete all
//
@@ -1251,10 +1276,10 @@ NotifyStmResourceChange (
Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);
Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
}
return;
}
/**
This is STM setup BIOS callback.
**/
@@ -1278,4 +1303,3 @@ SmmStmTeardown (
{
mStmState &= ~EFI_SM_MONITOR_STATE_ACTIVATED;
}

1
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
View File

@@ -45,7 +45,6 @@ SmmStmExceptionHandler (
IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context
);
/**
Get STM state.

2
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c
View File

@@ -206,6 +206,7 @@ InternalSmstGetVendorTableByGuid (
return (VOID *)(UINTN)SmmConfigurationTable64[Index].VendorTable;
}
}
return NULL;
} else {
DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmConfigurationTable: %x\n", Smst->SmmConfigurationTable));
@@ -217,6 +218,7 @@ InternalSmstGetVendorTableByGuid (
return (VOID *)SmmConfigurationTable[Index].VendorTable;
}
}
return NULL;
}
}

22
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
View File

@@ -99,6 +99,7 @@ EFIAPI
LoadMtrrData (
EFI_PHYSICAL_ADDRESS MtrrTable
)
/*++
Routine Description:
@@ -182,6 +183,7 @@ ReadWriteCr (
} else {
AsmWriteCr0 (*CrValue);
}
break;
case 2:
if (Read) {
@@ -189,6 +191,7 @@ ReadWriteCr (
} else {
AsmWriteCr2 (*CrValue);
}
break;
case 3:
if (Read) {
@@ -196,6 +199,7 @@ ReadWriteCr (
} else {
AsmWriteCr3 (*CrValue);
}
break;
case 4:
if (Read) {
@@ -203,9 +207,10 @@ ReadWriteCr (
} else {
AsmWriteCr4 (*CrValue);
}
break;
default:
return EFI_UNSUPPORTED;;
return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
@@ -249,7 +254,6 @@ ProgramProcessorRegister (
RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;
for (Index = 0; Index < RegisterTable->TableLength; Index++) {
RegisterTableEntry = &RegisterTableEntryHead[Index];
//
@@ -264,6 +268,7 @@ ProgramProcessorRegister (
if (EFI_ERROR (Status)) {
break;
}
if (RegisterTableEntry->TestThenWrite) {
CurrentValue = BitFieldRead64 (
Value,
@@ -274,6 +279,7 @@ ProgramProcessorRegister (
break;
}
}
Value = (UINTN)BitFieldWrite64 (
Value,
RegisterTableEntry->ValidBitStart,
@@ -327,6 +333,7 @@ ProgramProcessorRegister (
RegisterTableEntry->Value
);
}
break;
//
// MemoryMapped operations
@@ -353,6 +360,7 @@ ProgramProcessorRegister (
} else {
AsmEnableCache ();
}
break;
case Semaphore:
@@ -407,12 +415,14 @@ ProgramProcessorRegister (
for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {
S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
}
//
// Second, check whether all VALID THREADs (not all threads) in current core are ready.
//
for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {
S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
}
break;
case PackageDepType:
@@ -445,17 +455,20 @@ ProgramProcessorRegister (
for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {
S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);
}
//
// Second, check whether VALID THREADS (not all threads) in current package are ready.
//
for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {
S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);
}
break;
default:
break;
}
break;
default:
@@ -490,6 +503,7 @@ SetRegister (
} else {
RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->RegisterTable;
}
if (RegisterTables == NULL) {
return;
}
@@ -504,6 +518,7 @@ SetRegister (
break;
}
}
ASSERT (RegisterTable != NULL);
if (FeatureInitData->ApLocation != 0) {
@@ -639,6 +654,7 @@ InitializeCpuBeforeRebase (
} else {
ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
}
mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
mExchangeInfo->ApFunction = (VOID *)(UINTN)InitializeAp;
@@ -674,6 +690,7 @@ InitializeCpuAfterRebase (
} else {
ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);
}
mNumberToFinish = (UINT32)(mNumberOfCpus - 1);
//
@@ -928,6 +945,7 @@ InitSmmS3ResumeState (
if (sizeof (UINTN) == sizeof (UINT64)) {
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;
}
if (sizeof (UINTN) == sizeof (UINT32)) {
SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;
}

21
UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
View File

@@ -46,7 +46,7 @@ SmmGetProcessorInfo (
//
// Check parameter
//
if (ProcessorNumber >= mMaxNumberOfCpus || ProcessorInfoBuffer == NULL) {
if ((ProcessorNumber >= mMaxNumberOfCpus) || (ProcessorInfoBuffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -90,8 +90,9 @@ SmmSwitchBsp (
return EFI_NOT_FOUND;
}
if (gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone ||
gSmst->CurrentlyExecutingCpu == ProcessorNumber) {
if ((gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone) ||
(gSmst->CurrentlyExecutingCpu == ProcessorNumber))
{
return EFI_UNSUPPORTED;
}
@@ -132,7 +133,7 @@ SmmAddProcessor (
//
// Check parameter
//
if (ProcessorNumber == NULL || ProcessorId == INVALID_APIC_ID) {
if ((ProcessorNumber == NULL) || (ProcessorId == INVALID_APIC_ID)) {
return EFI_INVALID_PARAMETER;
}
@@ -151,8 +152,9 @@ SmmAddProcessor (
// of the APIC ID to SMBASE.
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (mCpuHotPlugData.ApicId[Index] == ProcessorId &&
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
if ((mCpuHotPlugData.ApicId[Index] == ProcessorId) &&
(gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID))
{
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
GetProcessorLocationByApicId (
@@ -197,8 +199,9 @@ SmmRemoveProcessor (
//
// Check parameter
//
if (ProcessorNumber >= mMaxNumberOfCpus ||
gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID) {
if ((ProcessorNumber >= mMaxNumberOfCpus) ||
(gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID))
{
return EFI_INVALID_PARAMETER;
}
@@ -259,6 +262,7 @@ SmmWhoAmI (
return EFI_SUCCESS;
}
}
//
// This should not happen
//
@@ -363,4 +367,3 @@ InitializeSmmCpuServices (
ASSERT_EFI_ERROR (Status);
return Status;
}

22
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
View File

@@ -72,7 +72,8 @@ SmmInitPageTable (
if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||
HEAP_GUARD_NONSTOP_MODE ||
NULL_DETECTION_NONSTOP_MODE) {
NULL_DETECTION_NONSTOP_MODE)
{
//
// Set own Page Fault entry instead of the default one, because SMM Profile
// feature depends on IRET instruction to do Single Step
@@ -98,6 +99,7 @@ SmmInitPageTable (
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
InitializeIDTSmmStackGuard ();
}
return Gen4GPageTable (TRUE);
}
@@ -143,13 +145,15 @@ SmiPFHandler (
// or SMM page protection violation.
//
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))
{
DumpCpuContext (InterruptType, SystemContext);
CpuIndex = GetCpuIndex ();
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize);
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(PFAddress >= GuardPageAddress) &&
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))
{
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else {
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
@@ -169,6 +173,7 @@ SmiPFHandler (
goto Exit;
}
}
CpuDeadLoop ();
goto Exit;
}
@@ -177,7 +182,8 @@ SmiPFHandler (
// If a page fault occurs in non-SMRAM range.
//
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))
{
if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));
@@ -191,8 +197,9 @@ SmiPFHandler (
//
// If NULL pointer was just accessed
//
if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&
(PFAddress < EFI_PAGE_SIZE)) {
if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&
(PFAddress < EFI_PAGE_SIZE))
{
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));
DEBUG_CODE (
@@ -283,6 +290,7 @@ SetPageTableAttributes (
//
DisableCet ();
}
AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
do {
@@ -309,10 +317,12 @@ SetPageTableAttributes (
// 2M
continue;
}
L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L1PageTable == NULL) {
continue;
}
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
}

2
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c
View File

@@ -188,6 +188,7 @@ InitShadowStack (
if (FeaturePcdGet (PcdCpuSmmStackGuard)) {
SmmShadowStackSize += EFI_PAGES_TO_SIZE (2);
}
mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));
PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
@@ -201,4 +202,3 @@ InitShadowStack (
}
}
}

85
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
View File

@@ -45,20 +45,22 @@ WaitForSemaphore (
for ( ; ;) {
Value = *Sem;
if (Value != 0 &&
InterlockedCompareExchange32 (
if ((Value != 0) &&
(InterlockedCompareExchange32 (
(UINT32 *)Sem,
Value,
Value - 1
) == Value) {
) == Value))
{
break;
}
CpuPause ();
}
return Value - 1;
}
/**
Performs an atomic compare exchange operation to release semaphore.
The compare exchange operation must be performed using
@@ -84,6 +86,7 @@ ReleaseSemaphore (
Value,
Value + 1
) != Value);
return Value + 1;
}
@@ -108,8 +111,10 @@ LockdownSemaphore (
Value = *Sem;
} while (InterlockedCompareExchange32 (
(UINT32 *)Sem,
Value, (UINT32)-1
Value,
(UINT32)-1
) != Value);
return Value;
}
@@ -178,21 +183,23 @@ AllCpusInSmmWithExceptions (
CpuData = mSmmMpSyncData->CpuData;
ProcessorInfo = gSmmCpuPrivate->ProcessorInfo;
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (!(*(CpuData[Index].Present)) && ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {
if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0) {
if (!(*(CpuData[Index].Present)) && (ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {
if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0)) {
continue;
}
if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0) {
if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0)) {
continue;
}
if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0) {
if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0)) {
continue;
}
return FALSE;
}
}
return TRUE;
}
@@ -288,7 +295,8 @@ SmmWaitForApArrival (
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) &&
!AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);
) {
)
{
CpuPause ();
}
@@ -313,7 +321,7 @@ SmmWaitForApArrival (
// Send SMI IPIs to bring outside processors in
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {
if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {
SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
}
}
@@ -324,7 +332,8 @@ SmmWaitForApArrival (
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) &&
!AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);
) {
)
{
CpuPause ();
}
}
@@ -332,7 +341,6 @@ SmmWaitForApArrival (
return;
}
/**
Replace OS MTRR's with SMI MTRR's.
@@ -499,8 +507,7 @@ BSPHandler (
//
// If Traditional Sync Mode or need to configure MTRRs: gather all available APs.
//
if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) {
if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Wait for APs to arrive
//
@@ -587,8 +594,7 @@ BSPHandler (
// make those APs to exit SMI synchronously. APs which arrive later will be excluded and
// will run through freely.
//
if (SyncMode != SmmCpuSyncModeTradition && !SmmCpuFeaturesNeedConfigureMtrrs()) {
if ((SyncMode != SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Lock the counter down and retrieve the number of APs
//
@@ -604,6 +610,7 @@ BSPHandler (
PresentCount++;
}
}
if (PresentCount > ApCount) {
break;
}
@@ -711,7 +718,8 @@ APHandler (
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) &&
!(*mSmmMpSyncData->InsideSmm);
) {
)
{
CpuPause ();
}
@@ -737,7 +745,8 @@ APHandler (
for (Timer = StartSyncTimer ();
!IsSyncTimerTimeout (Timer) &&
!(*mSmmMpSyncData->InsideSmm);
) {
)
{
CpuPause ();
}
@@ -768,7 +777,7 @@ APHandler (
//
*(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE;
if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) {
if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Notify BSP of arrival at this point
//
@@ -884,7 +893,6 @@ APHandler (
// Notify BSP the readiness of this AP to exit SMM
//
ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);
}
/**
@@ -926,6 +934,7 @@ Gen4GPageTable (
High2MBoundary = (mSmmStackArrayEnd - mSmmStackSize - mSmmShadowStackSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1);
PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1;
}
//
// Allocate the page table
//
@@ -947,6 +956,7 @@ Gen4GPageTable (
Pte[Index] = ((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAddressEncMask |
(Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);
}
Pte += EFI_PAGE_SIZE / sizeof (*Pte);
//
@@ -981,8 +991,10 @@ Gen4GPageTable (
} else {
Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
}
PageAddress += EFI_PAGE_SIZE;
}
Pages += EFI_PAGE_SIZE;
}
}
@@ -1076,6 +1088,7 @@ AllocateTokenBuffer (
DEBUG ((DEBUG_ERROR, "PcdCpuSmmMpTokenCountPerChunk should not be Zero!\n"));
CpuDeadLoop ();
}
DEBUG ((DEBUG_INFO, "CpuSmm: SpinLock Size = 0x%x, PcdCpuSmmMpTokenCountPerChunk = 0x%x\n", SpinLockSize, TokenCountPerChunk));
//
@@ -1125,6 +1138,7 @@ GetFreeToken (
if (gSmmCpuPrivate->FirstFreeToken == &gSmmCpuPrivate->TokenList) {
gSmmCpuPrivate->FirstFreeToken = AllocateTokenBuffer ();
}
NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken);
gSmmCpuPrivate->FirstFreeToken = GetNextNode (&gSmmCpuPrivate->TokenList, gSmmCpuPrivate->FirstFreeToken);
@@ -1210,28 +1224,36 @@ InternalSmmStartupThisAp (
DEBUG ((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));
return EFI_INVALID_PARAMETER;
}
if (CpuIndex == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
DEBUG ((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex));
return EFI_INVALID_PARAMETER;
}
if (gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId == INVALID_APIC_ID) {
return EFI_INVALID_PARAMETER;
}
if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {
if (mSmmMpSyncData->EffectiveSyncMode == SmmCpuSyncModeTradition) {
DEBUG ((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex));
}
return EFI_INVALID_PARAMETER;
}
if (gSmmCpuPrivate->Operation[CpuIndex] == SmmCpuRemove) {
if (!FeaturePcdGet (PcdCpuHotPlugSupport)) {
DEBUG ((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex));
}
return EFI_INVALID_PARAMETER;
}
if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {
return EFI_INVALID_PARAMETER;
}
if (Procedure == NULL) {
return EFI_INVALID_PARAMETER;
}
@@ -1262,6 +1284,7 @@ InternalSmmStartupThisAp (
*Token = (MM_COMPLETION)ProcToken->SpinLock;
}
}
mSmmMpSyncData->CpuData[CpuIndex].Status = CpuStatus;
if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) {
*mSmmMpSyncData->CpuData[CpuIndex].Status = EFI_NOT_READY;
@@ -1323,6 +1346,7 @@ InternalSmmStartupAllAPs (
if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {
return EFI_INVALID_PARAMETER;
}
if (Procedure == NULL) {
return EFI_INVALID_PARAMETER;
}
@@ -1339,9 +1363,11 @@ InternalSmmStartupAllAPs (
if (!AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) {
return EFI_NOT_READY;
}
ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);
}
}
if (CpuCount == 0) {
return EFI_NOT_STARTED;
}
@@ -1373,6 +1399,7 @@ InternalSmmStartupAllAPs (
if (ProcToken != NULL) {
mSmmMpSyncData->CpuData[Index].Token = ProcToken;
}
if (CPUStatus != NULL) {
mSmmMpSyncData->CpuData[Index].Status = &CPUStatus[Index];
if (mSmmMpSyncData->CpuData[Index].Status != NULL) {
@@ -1644,9 +1671,9 @@ SmiRendezvous (
while (*mSmmMpSyncData->AllCpusInSync) {
CpuPause ();
}
goto Exit;
} else {
//
// The BUSY lock is initialized to Released state.
// This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call.
@@ -1705,7 +1732,6 @@ SmiRendezvous (
// "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP
//
if (mSmmMpSyncData->BspIndex == CpuIndex) {
//
// Clear last request for SwitchBsp.
//
@@ -1847,13 +1873,16 @@ InitializeMpSyncData (
//
mSmmMpSyncData->BspIndex = (UINT32)-1;
}
mSmmMpSyncData->EffectiveSyncMode = mCpuSmmSyncMode;
mSmmMpSyncData->Counter = mSmmCpuSemaphores.SemaphoreGlobal.Counter;
mSmmMpSyncData->InsideSmm = mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm;
mSmmMpSyncData->AllCpusInSync = mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync;
ASSERT (mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL &&
mSmmMpSyncData->AllCpusInSync != NULL);
ASSERT (
mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL &&
mSmmMpSyncData->AllCpusInSync != NULL
);
*mSmmMpSyncData->Counter = 0;
*mSmmMpSyncData->InsideSmm = FALSE;
*mSmmMpSyncData->AllCpusInSync = FALSE;
@@ -1926,6 +1955,7 @@ InitializeMpServiceData (
} else {
VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
}
gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;
//
// Clear the low 12 bits
@@ -2013,9 +2043,10 @@ RegisterStartupProcedure (
IN OUT VOID *ProcedureArguments OPTIONAL
)
{
if (Procedure == NULL && ProcedureArguments != NULL) {
if ((Procedure == NULL) && (ProcedureArguments != NULL)) {
return EFI_INVALID_PARAMETER;
}
if (mSmmMpSyncData == NULL) {
return EFI_NOT_READY;
}

50
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
View File

@@ -21,7 +21,9 @@ SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData = {
NULL, // Pointer to Operation array
NULL, // Pointer to CpuSaveStateSize array
NULL, // Pointer to CpuSaveState array
{ {0} }, // SmmReservedSmramRegion
{
{ 0 }
}, // SmmReservedSmramRegion
{
SmmStartupThisAp, // SmmCoreEntryContext.SmmStartupThisAp
0, // SmmCoreEntryContext.CurrentlyExecutingCpu
@@ -236,6 +238,7 @@ SmmReadSaveState (
if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
}
//
// The SpeculationBarrier() call here is to ensure the above check for the
// CpuIndex has been completed before the execution of subsequent codes.
@@ -252,6 +255,7 @@ SmmReadSaveState (
if (Width != sizeof (UINT64)) {
return EFI_INVALID_PARAMETER;
}
//
// If the processor is in SMM at the time the SMI occurred,
// the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
@@ -273,6 +277,7 @@ SmmReadSaveState (
if (Status == EFI_UNSUPPORTED) {
Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);
}
return Status;
}
@@ -324,10 +329,10 @@ SmmWriteSaveState (
if (Status == EFI_UNSUPPORTED) {
Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);
}
return Status;
}
/**
C function for SMI handler. To change all processor's SMMBase Register.
@@ -384,6 +389,7 @@ SmmInitHandler (
return;
}
}
ASSERT (FALSE);
}
@@ -459,7 +465,8 @@ SmmRelocateBases (
//
// Wait for this AP to finish its 1st SMI
//
while (!mRebased[Index]);
while (!mRebased[Index]) {
}
} else {
//
// BSP will be Relocated later
@@ -477,7 +484,8 @@ SmmRelocateBases (
//
// Wait for the BSP to finish its 1st SMI
//
while (!mRebased[BspIndex]);
while (!mRebased[BspIndex]) {
}
//
// Restore contents at address 0x38000
@@ -599,9 +607,9 @@ PiCpuSmmEntry (
//
DEBUG_CODE_BEGIN ();
if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
}
DEBUG_CODE_END ();
//
@@ -625,6 +633,7 @@ PiCpuSmmEntry (
} else {
mMaxNumberOfCpus = mNumberOfCpus;
}
gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;
//
@@ -703,7 +712,7 @@ PiCpuSmmEntry (
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
FamilyId = (RegEax >> 8) & 0xf;
ModelId = (RegEax >> 4) & 0xf;
if (FamilyId == 0x06 || FamilyId == 0x0f) {
if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {
ModelId = ModelId | ((RegEax >> 12) & 0xf0);
}
@@ -712,6 +721,7 @@ PiCpuSmmEntry (
if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
}
//
// Determine the mode of the CPU at the time an SMI occurs
// Intel(R) 64 and IA-32 Architectures Software Developer's Manual
@@ -721,8 +731,9 @@ PiCpuSmmEntry (
if ((RegEdx & BIT29) != 0) {
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
}
if (FamilyId == 0x06) {
if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {
if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) {
mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;
}
}
@@ -739,6 +750,7 @@ PiCpuSmmEntry (
mCetSupported = FALSE;
PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);
}
if (mCetSupported) {
AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL);
DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx));
@@ -796,6 +808,7 @@ PiCpuSmmEntry (
} else {
Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);
}
ASSERT (Buffer != NULL);
DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages)));
@@ -842,7 +855,9 @@ PiCpuSmmEntry (
ASSERT_EFI_ERROR (Status);
mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;
DEBUG ((DEBUG_INFO, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
DEBUG ((
DEBUG_INFO,
"CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
Index,
(UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,
mCpuHotPlugData.SmBase[Index],
@@ -997,7 +1012,8 @@ PiCpuSmmEntry (
//
Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (
&gSmmCpuPrivate->SmmCpuHandle,
&gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,
&gEfiSmmConfigurationProtocolGuid,
&gSmmCpuPrivate->SmmConfiguration,
NULL
);
ASSERT_EFI_ERROR (Status);
@@ -1150,12 +1166,13 @@ FindSmramInfo (
do {
Found = FALSE;
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {
if ((mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase) &&
(*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)))
{
*SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
*SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE;
} else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
} else if (((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart) && (mSmmCpuSmramRanges[Index].PhysicalSize > 0)) {
*SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE;
}
@@ -1272,6 +1289,7 @@ ConfigSmmCodeAccessCheck (
//
continue;
}
//
// Acquire Config SMM Code Access Check spin lock. The AP will release the
// spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
@@ -1325,6 +1343,7 @@ AllocatePageTableMemory (
if (Buffer != NULL) {
return Buffer;
}
return AllocatePages (Pages);
}
@@ -1351,6 +1370,7 @@ AllocateCodePages (
if (EFI_ERROR (Status)) {
return NULL;
}
return (VOID *)(UINTN)Memory;
}
@@ -1385,6 +1405,7 @@ AllocateAlignedCodePages (
if (Pages == 0) {
return NULL;
}
if (Alignment > EFI_PAGE_SIZE) {
//
// Calculate the total number of pages since alignment is larger than page size.
@@ -1400,6 +1421,7 @@ AllocateAlignedCodePages (
if (EFI_ERROR (Status)) {
return NULL;
}
AlignedMemory = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;
UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);
if (UnalignedPages > 0) {
@@ -1409,6 +1431,7 @@ AllocateAlignedCodePages (
Status = gSmst->SmmFreePages (Memory, UnalignedPages);
ASSERT_EFI_ERROR (Status);
}
Memory = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);
UnalignedPages = RealPages - Pages - UnalignedPages;
if (UnalignedPages > 0) {
@@ -1426,8 +1449,10 @@ AllocateAlignedCodePages (
if (EFI_ERROR (Status)) {
return NULL;
}
AlignedMemory = (UINTN)Memory;
}
return (VOID *)AlignedMemory;
}
@@ -1447,6 +1472,7 @@ PerformRemainingTasks (
if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {
SmmProfileStart ();
}
//
// Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
//

2
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
View File

@@ -500,7 +500,6 @@ Gen4GPageTable (
IN BOOLEAN Is32BitPageTable
);
/**
Initialize global data for MP synchronization.
@@ -1080,7 +1079,6 @@ AllocateAlignedCodePages (
IN UINTN Alignment
);
//
// S3 related global variable and function prototype.
//

81
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
View File

@@ -62,11 +62,13 @@ PageAttributeToLength (
)
{
UINTN Index;
for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].Length;
}
}
return 0;
}
@@ -83,11 +85,13 @@ PageAttributeToMask (
)
{
UINTN Index;
for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {
if (PageAttribute == mPageAttributeTable[Index].Attribute) {
return (UINTN)mPageAttributeTable[Index].AddressMask;
}
}
return 0;
}
@@ -138,6 +142,7 @@ GetPageTableEntry (
} else {
L4PageTable = (UINT64 *)PageTableBase;
}
if (L4PageTable[Index4] == 0) {
*PageAttribute = PageNone;
return NULL;
@@ -147,10 +152,12 @@ GetPageTableEntry (
} else {
L3PageTable = (UINT64 *)PageTableBase;
}
if (L3PageTable[Index3] == 0) {
*PageAttribute = PageNone;
return NULL;
}
if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {
// 1G
*PageAttribute = Page1G;
@@ -162,6 +169,7 @@ GetPageTableEntry (
*PageAttribute = PageNone;
return NULL;
}
if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {
// 2M
*PageAttribute = Page2M;
@@ -174,6 +182,7 @@ GetPageTableEntry (
*PageAttribute = PageNone;
return NULL;
}
*PageAttribute = Page4K;
return &L1PageTable[Index1];
}
@@ -191,16 +200,20 @@ GetAttributesFromPageEntry (
)
{
UINT64 Attributes;
Attributes = 0;
if ((*PageEntry & IA32_PG_P) == 0) {
Attributes |= EFI_MEMORY_RP;
}
if ((*PageEntry & IA32_PG_RW) == 0) {
Attributes |= EFI_MEMORY_RO;
}
if ((*PageEntry & IA32_PG_NX) != 0) {
Attributes |= EFI_MEMORY_XP;
}
return Attributes;
}
@@ -232,6 +245,7 @@ ConvertPageEntryAttribute (
NewPageEntry |= IA32_PG_P;
}
}
if ((Attributes & EFI_MEMORY_RO) != 0) {
if (IsSet) {
NewPageEntry &= ~(UINT64)IA32_PG_RW;
@@ -250,6 +264,7 @@ ConvertPageEntryAttribute (
NewPageEntry |= IA32_PG_RW;
}
}
if ((Attributes & EFI_MEMORY_XP) != 0) {
if (mXdSupported) {
if (IsSet) {
@@ -259,6 +274,7 @@ ConvertPageEntryAttribute (
}
}
}
*PageEntry = NewPageEntry;
if (CurrentPageEntry != NewPageEntry) {
*IsModified = TRUE;
@@ -337,10 +353,12 @@ SplitPage (
if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64;
for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);
}
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
return RETURN_SUCCESS;
} else {
@@ -352,16 +370,18 @@ SplitPage (
// No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.
//
ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);
if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) {
if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) {
NewPageEntry = AllocatePageTableMemory (1);
DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));
if (NewPageEntry == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64;
for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);
}
(*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
return RETURN_SUCCESS;
} else {
@@ -431,9 +451,11 @@ ConvertMemoryPageAttributes (
if (BaseAddress > MaximumSupportMemAddress) {
return RETURN_UNSUPPORTED;
}
if (Length > MaximumSupportMemAddress) {
return RETURN_UNSUPPORTED;
}
if ((Length != 0) && (BaseAddress > MaximumSupportMemAddress - (Length - 1))) {
return RETURN_UNSUPPORTED;
}
@@ -443,6 +465,7 @@ ConvertMemoryPageAttributes (
if (IsSplitted != NULL) {
*IsSplitted = FALSE;
}
if (IsModified != NULL) {
*IsModified = FALSE;
}
@@ -455,6 +478,7 @@ ConvertMemoryPageAttributes (
if (PageEntry == NULL) {
return RETURN_UNSUPPORTED;
}
PageEntryLength = PageAttributeToLength (PageAttribute);
SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);
if (SplitAttribute == PageNone) {
@@ -464,6 +488,7 @@ ConvertMemoryPageAttributes (
*IsModified = TRUE;
}
}
//
// Convert success, move to next
//
@@ -474,12 +499,15 @@ ConvertMemoryPageAttributes (
if (RETURN_ERROR (Status)) {
return RETURN_UNSUPPORTED;
}
if (IsSplitted != NULL) {
*IsSplitted = TRUE;
}
if (IsModified != NULL) {
*IsModified = TRUE;
}
//
// Just split current page
// Convert success in next around
@@ -967,6 +995,7 @@ SetMemMapAttributes (
);
break;
}
MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);
}
@@ -1086,7 +1115,8 @@ MergeMemoryMapForNotPresentEntry (
MemoryBlockLength = (UINT64)(EFI_PAGES_TO_SIZE ((UINTN)MemoryMapEntry->NumberOfPages));
if (((UINTN)NextMemoryMapEntry < (UINTN)MemoryMapEnd) &&
IsUefiPageNotPresent (MemoryMapEntry) && IsUefiPageNotPresent (NextMemoryMapEntry) &&
((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart)) {
((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart))
{
MemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages;
if (NewMemoryMapEntry != MemoryMapEntry) {
NewMemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages;
@@ -1129,10 +1159,11 @@ GetGcdMemoryMap (
mGcdMemNumberOfDesc = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved &&
(MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
(EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)
) {
if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&
((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
(EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))
)
{
mGcdMemNumberOfDesc++;
}
}
@@ -1147,10 +1178,11 @@ GetGcdMemoryMap (
mGcdMemNumberOfDesc = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved &&
(MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
(EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)
) {
if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&
((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==
(EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))
)
{
CopyMem (
&mGcdMemSpace[mGcdMemNumberOfDesc],
&MemSpaceMap[Index],
@@ -1292,9 +1324,11 @@ SetUefiMemMapAttributes (
Status
));
}
MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize);
}
}
//
// Do not free mUefiMemoryMap, it will be checked in IsSmmCommBufferForbiddenAddress().
//
@@ -1318,6 +1352,7 @@ SetUefiMemMapAttributes (
));
}
}
//
// Do not free mGcdMemSpace, it will be checked in IsSmmCommBufferForbiddenAddress().
//
@@ -1328,7 +1363,7 @@ SetUefiMemMapAttributes (
if (mUefiMemoryAttributesTable != NULL) {
Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1);
for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) {
if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) {
if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {
if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {
Status = SmmSetMemoryAttributes (
Entry->PhysicalStart,
@@ -1344,9 +1379,11 @@ SetUefiMemMapAttributes (
));
}
}
Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize);
}
}
//
// Do not free mUefiMemoryAttributesTable, it will be checked in IsSmmCommBufferForbiddenAddress().
//
@@ -1376,10 +1413,12 @@ IsSmmCommBufferForbiddenAddress (
for (Index = 0; Index < MemoryMapEntryCount; Index++) {
if (IsUefiPageNotPresent (MemoryMap)) {
if ((Address >= MemoryMap->PhysicalStart) &&
(Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages)) ) {
(Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages)))
{
return TRUE;
}
}
MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize);
}
}
@@ -1387,7 +1426,8 @@ IsSmmCommBufferForbiddenAddress (
if (mGcdMemSpace != NULL) {
for (Index = 0; Index < mGcdMemNumberOfDesc; Index++) {
if ((Address >= mGcdMemSpace[Index].BaseAddress) &&
(Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length) ) {
(Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length))
{
return TRUE;
}
}
@@ -1396,17 +1436,20 @@ IsSmmCommBufferForbiddenAddress (
if (mUefiMemoryAttributesTable != NULL) {
Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1);
for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) {
if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) {
if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {
if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {
if ((Address >= Entry->PhysicalStart) &&
(Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT))) {
(Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT)))
{
return TRUE;
}
Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize);
}
}
}
}
return FALSE;
}
@@ -1516,7 +1559,7 @@ EdkiiSmmGetMemoryAttributes (
PAGE_ATTRIBUTE PageAttr;
INT64 Size;
if (Length < SIZE_4KB || Attributes == NULL) {
if ((Length < SIZE_4KB) || (Attributes == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -1524,9 +1567,8 @@ EdkiiSmmGetMemoryAttributes (
MemAttr = (UINT64)-1;
do {
PageEntry = GetPageTableEntry (BaseAddress, &PageAttr);
if (PageEntry == NULL || PageAttr == PageNone) {
if ((PageEntry == NULL) || (PageAttr == PageNone)) {
return EFI_UNSUPPORTED;
}
@@ -1535,7 +1577,7 @@ EdkiiSmmGetMemoryAttributes (
// share the same attribute. Return EFI_NO_MAPPING if not.
//
*Attributes = GetAttributesFromPageEntry (PageEntry);
if (MemAttr != (UINT64)-1 && *Attributes != MemAttr) {
if ((MemAttr != (UINT64)-1) && (*Attributes != MemAttr)) {
return EFI_NO_MAPPING;
}
@@ -1563,7 +1605,6 @@ EdkiiSmmGetMemoryAttributes (
}
MemAttr = *Attributes;
} while (Size > 0);
return EFI_SUCCESS;

1
UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c
View File

@@ -341,4 +341,3 @@ SmmMpWaitForProcedure (
return Status;
}

2
UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h
View File

@@ -31,7 +31,6 @@ SmmMpGetNumberOfProcessors (
OUT UINTN *NumberOfProcessors
);
/**
This service allows the caller to invoke a procedure one of the application processors (AP). This
function uses an optional token parameter to support blocking and non-blocking modes. If the token
@@ -182,7 +181,6 @@ SmmMpBroadcastProcedure (
IN OUT EFI_STATUS *CPUStatus
);
/**
This service allows the caller to set a startup procedure that will be executed when an AP powers
up from a state where core configuration and context is lost. The procedure is execution has the

78
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
View File

@@ -78,13 +78,17 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
// SMRAM range (to be fixed in runtime).
// It is always present and instruction fetches are allowed.
//
{{0x00000000, 0x00000000},TRUE,FALSE},
{
{ 0x00000000, 0x00000000 }, TRUE, FALSE
},
//
// SMM profile data range( to be fixed in runtime).
// It is always present and instruction fetches are not allowed.
//
{{0x00000000, 0x00000000},TRUE,TRUE},
{
{ 0x00000000, 0x00000000 }, TRUE, TRUE
},
//
// SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).
@@ -156,6 +160,7 @@ GetCpuIndex (
return Index;
}
}
ASSERT (FALSE);
return 0;
}
@@ -188,6 +193,7 @@ GetSourceFromDestinationOnBts (
CurrentBTSRecord = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[CpuIndex]->BTSAbsoluteMaximum - 1);
CurrentBTSRecord--;
}
if (CurrentBTSRecord->LastBranchTo == DestinationIP) {
//
// Good! find 1st one, then find 2nd one.
@@ -204,6 +210,7 @@ GetSourceFromDestinationOnBts (
return CurrentBTSRecord->LastBranchFrom;
}
}
CurrentBTSRecord--;
}
@@ -230,9 +237,11 @@ DebugExceptionHandler (
if (!mSmmProfileStart &&
!HEAP_GUARD_NONSTOP_MODE &&
!NULL_DETECTION_NONSTOP_MODE) {
!NULL_DETECTION_NONSTOP_MODE)
{
return;
}
CpuIndex = GetCpuIndex ();
//
@@ -276,12 +285,15 @@ IsInSmmRanges (
if ((Address >= mCpuHotPlugData.SmrrBase) && (Address < mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
return TRUE;
}
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
if (Address >= mSmmCpuSmramRanges[Index].CpuStart &&
Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) {
if ((Address >= mSmmCpuSmramRanges[Index].CpuStart) &&
(Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize))
{
return TRUE;
}
}
return FALSE;
}
@@ -310,14 +322,15 @@ IsAddressValid (
return mProtectionMemRange[Index].Present;
}
}
*Nx = TRUE;
return FALSE;
} else {
*Nx = TRUE;
if (IsInSmmRanges (Address)) {
*Nx = FALSE;
}
return TRUE;
}
}
@@ -355,6 +368,7 @@ IsAddressSplit (
}
}
}
//
// Return default
//
@@ -425,13 +439,15 @@ InitProtectedMemRange (
//
NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE);
for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
if (mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base &&
mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) {
if ((mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base) &&
(mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top))
{
//
// If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz
//
break;
}
mProtectionMemRange[NumberOfProtectRange].Range.Base = mSmmCpuSmramRanges[Index].CpuStart;
mProtectionMemRange[NumberOfProtectRange].Range.Top = mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize;
mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
@@ -446,6 +462,7 @@ InitProtectedMemRange (
if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) {
continue;
}
mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress;
mProtectionMemRange[NumberOfProtectRange].Range.Top = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length;
mProtectionMemRange[NumberOfProtectRange].Present = TRUE;
@@ -479,7 +496,8 @@ InitProtectedMemRange (
Top2MBAlignedAddress = ProtectEndAddress & ~(SIZE_2MB - 1);
Base2MBAlignedAddress = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
if ((Top2MBAlignedAddress > Base2MBAlignedAddress) &&
((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB)) {
((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB))
{
//
// There is an range which could be mapped by 2MB-page.
//
@@ -493,6 +511,7 @@ InitProtectedMemRange (
mSplitMemRange[NumberOfSpliteRange].Top = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);
NumberOfSpliteRange++;
}
if (Low4KBPageSize != 0) {
//
// Add not 2MB-aligned range to be mapped by 4KB-page.
@@ -519,6 +538,7 @@ InitProtectedMemRange (
DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base));
DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Top = %lx\n", Index, mProtectionMemRange[Index].Range.Top));
}
for (Index = 0; Index < mSplitMemRangeCount; Index++) {
DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base));
DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Top = %lx\n", Index, mSplitMemRange[Index].Top));
@@ -565,6 +585,7 @@ InitPaging (
} else {
Pml5 = (UINT64 *)(UINTN)mSmmProfileCr3;
}
SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;
//
// Calculate the table entries of PML4E and PDPTE.
@@ -604,6 +625,7 @@ InitPaging (
//
continue;
}
Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
@@ -612,6 +634,7 @@ InitPaging (
//
continue;
}
Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
if ((*Pdpt & IA32_PG_P) == 0) {
@@ -620,16 +643,19 @@ InitPaging (
//
continue;
}
if ((*Pdpt & IA32_PG_PS) != 0) {
//
// This is 1G entry, skip it
//
continue;
}
Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
if (Pd == 0) {
continue;
}
for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {
if ((*Pd & IA32_PG_P) == 0) {
//
@@ -637,6 +663,7 @@ InitPaging (
//
continue;
}
Address = (UINTN)LShiftU64 (
LShiftU64 (
LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
@@ -661,6 +688,7 @@ InitPaging (
for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++) {
Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
} // end for PT
*Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
} // end if IsAddressSplit
} // end for PD
@@ -679,6 +707,7 @@ InitPaging (
//
continue;
}
Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);
for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
@@ -687,6 +716,7 @@ InitPaging (
//
continue;
}
Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
if ((*Pdpt & IA32_PG_P) == 0) {
@@ -695,6 +725,7 @@ InitPaging (
//
continue;
}
if ((*Pdpt & IA32_PG_PS) != 0) {
//
// This is 1G entry, set NX bit and skip it
@@ -702,12 +733,15 @@ InitPaging (
if (mXdSupported) {
*Pdpt = *Pdpt | IA32_PG_NX;
}
continue;
}
Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
if (Pd == 0) {
continue;
}
for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {
if ((*Pd & IA32_PG_P) == 0) {
//
@@ -715,6 +749,7 @@ InitPaging (
//
continue;
}
Address = (UINTN)LShiftU64 (
LShiftU64 (
LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,
@@ -732,6 +767,7 @@ InitPaging (
//
*Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
if (Nx && mXdSupported) {
*Pd = *Pd | IA32_PG_NX;
}
@@ -741,13 +777,16 @@ InitPaging (
if (Pt == 0) {
continue;
}
for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++, Pt++) {
if (!IsAddressValid (Address, &Nx)) {
*Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
if (Nx && mXdSupported) {
*Pt = *Pt | IA32_PG_NX;
}
Address += SIZE_4KB;
} // end for PT
} // end if PS
@@ -866,10 +905,12 @@ InitSmmProfileInternal (
mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mMaxNumberOfCpus);
ASSERT (mPFEntryCount != NULL);
mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus);
sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus
);
ASSERT (mLastPFEntryValue != NULL);
mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (
sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus);
sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus
);
ASSERT (mLastPFEntryPointer != NULL);
//
@@ -1062,6 +1103,7 @@ ActivateSingleStepDB (
if ((Dr6 & DR6_SINGLE_STEP) != 0) {
return;
}
Dr6 |= DR6_SINGLE_STEP;
AsmWriteDr6 (Dr6);
}
@@ -1081,6 +1123,7 @@ ActivateLBR (
if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {
return;
}
DebugCtl |= MSR_DEBUG_CTL_LBR;
AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);
}
@@ -1173,7 +1216,8 @@ InitSmmProfile (
//
if (!FeaturePcdGet (PcdCpuSmmProfileEnable) &&
!HEAP_GUARD_NONSTOP_MODE &&
!NULL_DETECTION_NONSTOP_MODE) {
!NULL_DETECTION_NONSTOP_MODE)
{
return;
}
@@ -1411,13 +1455,14 @@ SmmProfilePFHandler (
} else {
RestorePageTableAbove4G (PageTable, RestoreAddress, CpuIndex, ErrorCode, &IsValidPFAddress);
}
RestoreAddress += EFI_PAGE_SIZE;
RestorePageNumber--;
}
if (!IsValidPFAddress) {
InstructionAddress = Rip;
if ((ErrorCode & IA32_PF_EC_ID) != 0 && (mBtsSupported)) {
if (((ErrorCode & IA32_PF_EC_ID) != 0) && (mBtsSupported)) {
//
// If it is instruction fetch failure, get the correct IP from BTS.
//
@@ -1440,6 +1485,7 @@ SmmProfilePFHandler (
if (EFI_ERROR (Status)) {
continue;
}
if (IoInfo.IoPort == mSmiCommandPort) {
//
// A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.
@@ -1459,19 +1505,22 @@ SmmProfilePFHandler (
(SmmProfileEntry[Index].Address == PFAddress) &&
(SmmProfileEntry[Index].CpuNum == (UINT64)CpuIndex) &&
(SmmProfileEntry[Index].Instruction == InstructionAddress) &&
(SmmProfileEntry[Index].SmiCmd == SmiCommand)) {
(SmmProfileEntry[Index].SmiCmd == SmiCommand))
{
//
// Same record exist, need not save again.
//
break;
}
}
if (Index == mSmmProfileBase->CurDataEntries) {
CurrentEntryNumber = (UINTN)mSmmProfileBase->CurDataEntries;
MaxEntryNumber = (UINTN)mSmmProfileBase->MaxDataEntries;
if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer)) {
CurrentEntryNumber = CurrentEntryNumber % MaxEntryNumber;
}
if (CurrentEntryNumber < MaxEntryNumber) {
//
// Log the new entry
@@ -1491,6 +1540,7 @@ SmmProfilePFHandler (
}
}
}
//
// Flush TLB
//

1
UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
View File

@@ -80,7 +80,6 @@ PageFaultIdtHandlerSmmProfile (
VOID
);
/**
Check if feature is supported by a processor.

15
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
View File

@@ -237,11 +237,13 @@ GetRegisterIndex (
UINTN Offset;
for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {
if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) {
return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
}
Offset += mSmmCpuRegisterRanges[Index].Length;
}
return 0;
}
@@ -325,6 +327,7 @@ ReadSaveStateRegisterByIndex (
CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
}
}
return EFI_SUCCESS;
}
@@ -407,14 +410,15 @@ ReadSaveStateRegister (
// Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS.
//
if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) &&
(mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) {
(mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT))
{
return EFI_NOT_FOUND;
}
//
// Compute index for the I/O Length and I/O Type lookup tables
//
if (mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0 || mSmmCpuIoType[IoMisc.Bits.Type] == 0) {
if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) {
return EFI_NOT_FOUND;
}
@@ -525,6 +529,7 @@ WriteSaveStateRegister (
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
return EFI_INVALID_PARAMETER;
}
//
// Write SMM State register
//
@@ -556,6 +561,7 @@ WriteSaveStateRegister (
CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
}
}
return EFI_SUCCESS;
}
@@ -615,6 +621,7 @@ HookReturnFromSmm (
} else {
CpuState->x64._RIP = (UINT32)NewInstructionPointer;
}
//
// Clear the auto HALT restart flag so the RSM instruction returns
// program control to the instruction following the HLT instruction.
@@ -623,6 +630,7 @@ HookReturnFromSmm (
CpuState->x64.AutoHALTRestart &= ~BIT0;
}
}
return OriginalInstructionPointer;
}
@@ -644,6 +652,7 @@ GetSmiHandlerSize (
if (Size != 0) {
return Size;
}
return gcSmiHandlerSize;
}

1
UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c
View File

@@ -58,7 +58,6 @@ StartSyncTimer (
return GetPerformanceCounter ();
}
/**
Check if the SMM AP Sync timer is timeout.

109
UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
View File

@@ -61,6 +61,7 @@ Is1GPageSupport (
return TRUE;
}
}
return FALSE;
}
@@ -88,14 +89,20 @@ Is5LevelPagingNeeded (
} else {
VirPhyAddressSize.Bits.PhysicalAddressBits = 36;
}
AsmCpuidEx (
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
NULL, NULL, &ExtFeatureEcx.Uint32, NULL
NULL,
NULL,
&ExtFeatureEcx.Uint32,
NULL
);
DEBUG ((
DEBUG_INFO, "PhysicalAddressBits = %d, 5LPageTable = %d.\n",
VirPhyAddressSize.Bits.PhysicalAddressBits, ExtFeatureEcx.Bits.FiveLevelPage
DEBUG_INFO,
"PhysicalAddressBits = %d, 5LPageTable = %d.\n",
VirPhyAddressSize.Bits.PhysicalAddressBits,
ExtFeatureEcx.Bits.FiveLevelPage
));
if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) {
@@ -126,6 +133,7 @@ GetPageTable (
Cr4.UintN = AsmReadCr4 ();
*FiveLevels = (BOOLEAN)(Cr4.Bits.LA57 == 1);
}
return;
}
@@ -205,6 +213,7 @@ CalculateMaximumSupportAddress (
PhysicalAddressBits = 36;
}
}
return PhysicalAddressBits;
}
@@ -240,7 +249,7 @@ SetStaticPageTable (
// when 5-Level Paging is disabled.
//
ASSERT (PhysicalAddressBits <= 52);
if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) {
if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) {
PhysicalAddressBits = 48;
}
@@ -273,11 +282,13 @@ SetStaticPageTable (
//
PageMapLevel5Entry = PageMap;
}
PageAddress = 0;
for ( IndexOfPml5Entries = 0
; IndexOfPml5Entries < NumberOfPml5EntriesNeeded
; IndexOfPml5Entries++, PageMapLevel5Entry++) {
; IndexOfPml5Entries++, PageMapLevel5Entry++)
{
//
// Each PML5 entry points to a page of PML4 entires.
// So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.
@@ -310,12 +321,13 @@ SetStaticPageTable (
if (m1GPageTableSupport) {
PageDirectory1GEntry = PageDirectoryPointerEntry;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
if (IndexOfPml4Entries == 0 && IndexOfPageDirectoryEntries < 4) {
if ((IndexOfPml4Entries == 0) && (IndexOfPageDirectoryEntries < 4)) {
//
// Skip the < 4G entries
//
continue;
}
//
// Fill in the Page Directory entries
//
@@ -324,12 +336,13 @@ SetStaticPageTable (
} else {
PageAddress = BASE_4GB;
for (IndexOfPdpEntries = 0; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
if (IndexOfPml4Entries == 0 && IndexOfPdpEntries < 4) {
if ((IndexOfPml4Entries == 0) && (IndexOfPdpEntries < 4)) {
//
// Skip the < 4G entries
//
continue;
}
//
// Each Directory Pointer entries points to a page of Page Directory entires.
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
@@ -455,7 +468,8 @@ SmmInitPageTable (
if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||
HEAP_GUARD_NONSTOP_MODE ||
NULL_DETECTION_NONSTOP_MODE) {
NULL_DETECTION_NONSTOP_MODE)
{
//
// Set own Page Fault entry instead of the default one, because SMM Profile
// feature depends on IRET instruction to do Single Step
@@ -570,6 +584,7 @@ GetAndUpdateAccNum (
SetAccNum (Entry, Acc - 1);
}
}
return Acc;
}
@@ -647,24 +662,26 @@ ReclaimPages (
// First, find the leaf entry has the smallest access record value
//
for (Pml5Index = 0; Pml5Index < (Enable5LevelPaging ? (EFI_PAGE_SIZE / sizeof (*Pml4)) : 1); Pml5Index++) {
if ((Pml5[Pml5Index] & IA32_PG_P) == 0 || (Pml5[Pml5Index] & IA32_PG_PMNT) != 0) {
if (((Pml5[Pml5Index] & IA32_PG_P) == 0) || ((Pml5[Pml5Index] & IA32_PG_PMNT) != 0)) {
//
// If the PML5 entry is not present or is masked, skip it
//
continue;
}
Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & gPhyMask);
for (Pml4Index = 0; Pml4Index < EFI_PAGE_SIZE / sizeof (*Pml4); Pml4Index++) {
if ((Pml4[Pml4Index] & IA32_PG_P) == 0 || (Pml4[Pml4Index] & IA32_PG_PMNT) != 0) {
if (((Pml4[Pml4Index] & IA32_PG_P) == 0) || ((Pml4[Pml4Index] & IA32_PG_PMNT) != 0)) {
//
// If the PML4 entry is not present or is masked, skip it
//
continue;
}
Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask);
PML4EIgnore = FALSE;
for (PdptIndex = 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); PdptIndex++) {
if ((Pdpt[PdptIndex] & IA32_PG_P) == 0 || (Pdpt[PdptIndex] & IA32_PG_PMNT) != 0) {
if (((Pdpt[PdptIndex] & IA32_PG_P) == 0) || ((Pdpt[PdptIndex] & IA32_PG_PMNT) != 0)) {
//
// If the PDPT entry is not present or is masked, skip it
//
@@ -674,8 +691,10 @@ ReclaimPages (
//
PML4EIgnore = TRUE;
}
continue;
}
if ((Pdpt[PdptIndex] & IA32_PG_PS) == 0) {
//
// It's not 1-GByte pages entry, it should be a PDPT entry,
@@ -685,7 +704,7 @@ ReclaimPages (
Pdt = (UINT64 *)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask);
PDPTEIgnore = FALSE;
for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof (*Pdt); PdtIndex++) {
if ((Pdt[PdtIndex] & IA32_PG_P) == 0 || (Pdt[PdtIndex] & IA32_PG_PMNT) != 0) {
if (((Pdt[PdtIndex] & IA32_PG_P) == 0) || ((Pdt[PdtIndex] & IA32_PG_PMNT) != 0)) {
//
// If the PD entry is not present or is masked, skip it
//
@@ -695,16 +714,19 @@ ReclaimPages (
//
PDPTEIgnore = TRUE;
}
continue;
}
if ((Pdt[PdtIndex] & IA32_PG_PS) == 0) {
//
// It's not 2 MByte page table entry, it should be PD entry
// we will find the entry has the smallest access record value
//
PDPTEIgnore = TRUE;
if (PdtIndex != PFAddressPdtIndex || PdptIndex != PFAddressPdptIndex ||
Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) {
if ((PdtIndex != PFAddressPdtIndex) || (PdptIndex != PFAddressPdptIndex) ||
(Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index))
{
Acc = GetAndUpdateAccNum (Pdt + PdtIndex);
if (Acc < MinAcc) {
//
@@ -721,13 +743,15 @@ ReclaimPages (
}
}
}
if (!PDPTEIgnore) {
//
// If this PDPT entry has no PDT entries pointer to 4 KByte pages,
// it should only has the entries point to 2 MByte Pages
//
if (PdptIndex != PFAddressPdptIndex || Pml4Index != PFAddressPml4Index ||
Pml5Index != PFAddressPml5Index) {
if ((PdptIndex != PFAddressPdptIndex) || (Pml4Index != PFAddressPml4Index) ||
(Pml5Index != PFAddressPml5Index))
{
Acc = GetAndUpdateAccNum (Pdpt + PdptIndex);
if (Acc < MinAcc) {
//
@@ -745,12 +769,13 @@ ReclaimPages (
}
}
}
if (!PML4EIgnore) {
//
// If PML4 entry has no the PDPT entry pointer to 2 MByte pages,
// it should only has the entries point to 1 GByte Pages
//
if (Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) {
if ((Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index)) {
Acc = GetAndUpdateAccNum (Pml4 + Pml4Index);
if (Acc < MinAcc) {
//
@@ -768,6 +793,7 @@ ReclaimPages (
}
}
}
//
// Make sure one PML4/PDPT/PD entry is selected
//
@@ -791,8 +817,9 @@ ReclaimPages (
Pml4 = (UINT64 *)(UINTN)(Pml5[MinPml5] & gPhyMask);
Pdpt = (UINT64 *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask);
SubEntriesNum = GetSubEntriesNum (Pdpt + MinPdpt);
if (SubEntriesNum == 0 &&
(MinPdpt != PFAddressPdptIndex || MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) {
if ((SubEntriesNum == 0) &&
((MinPdpt != PFAddressPdptIndex) || (MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index)))
{
//
// Release the empty Page Directory table if there was no more 4 KByte Page Table entry
// clear the Page directory entry
@@ -805,18 +832,20 @@ ReclaimPages (
MinPdt = (UINTN)-1;
continue;
}
//
// Update the sub-entries filed in PDPT entry and exit
//
SetSubEntriesNum (Pdpt + MinPdpt, (SubEntriesNum - 1) & 0x1FF);
break;
}
if (MinPdpt != (UINTN)-1) {
//
// One 2MB Page Table is released or Page Directory table is released, check the PML4 entry
//
SubEntriesNum = GetSubEntriesNum (Pml4 + MinPml4);
if (SubEntriesNum == 0 && (MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) {
if ((SubEntriesNum == 0) && ((MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index))) {
//
// Release the empty PML4 table if there was no more 1G KByte Page Table entry
// clear the Page directory entry
@@ -826,12 +855,14 @@ ReclaimPages (
MinPdpt = (UINTN)-1;
continue;
}
//
// Update the sub-entries filed in PML4 entry and exit
//
SetSubEntriesNum (Pml4 + MinPml4, (SubEntriesNum - 1) & 0x1FF);
break;
}
//
// PLM4 table has been released before, exit it
//
@@ -918,9 +949,11 @@ SmiDefaultPFHandler (
NumOfPages = 1;
PageAttribute = 0;
}
if (PageSize >= MaxSmmPageSizeType) {
PageSize = SmmPageSize2M;
}
if (NumOfPages > 512) {
NumOfPages = 512;
}
@@ -944,6 +977,7 @@ SmiDefaultPFHandler (
DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!"));
ASSERT (FALSE);
}
//
// BIT30 to BIT38 is Page Directory Pointer Table index
//
@@ -977,6 +1011,7 @@ SmiDefaultPFHandler (
//
UpperEntry = PageTable + PTIndex;
}
//
// BIT9 to BIT11 of entry is used to save access record,
// initialize value is 7
@@ -996,6 +1031,7 @@ SmiDefaultPFHandler (
DEBUG ((DEBUG_ERROR, "New page table overlapped with old page table!\n"));
ASSERT (FALSE);
}
//
// Fill the new entry
//
@@ -1004,6 +1040,7 @@ SmiDefaultPFHandler (
if (UpperEntry != NULL) {
SetSubEntriesNum (UpperEntry, (GetSubEntriesNum (UpperEntry) + 1) & 0x1FF);
}
//
// Get the next page address if we need to create more page tables
//
@@ -1049,19 +1086,22 @@ SmiPFHandler (
// or SMM page protection violation.
//
if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {
(PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))
{
DumpCpuContext (InterruptType, SystemContext);
CpuIndex = GetCpuIndex ();
GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));
ShadowStackGuardPageAddress = (mSmmStackArrayBase + mSmmStackSize + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));
if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(PFAddress >= GuardPageAddress) &&
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {
(PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))
{
DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));
} else if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&
(mSmmShadowStackSize > 0) &&
(PFAddress >= ShadowStackGuardPageAddress) &&
(PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE))) {
(PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE)))
{
DEBUG ((DEBUG_ERROR, "SMM shadow stack overflow!\n"));
} else {
if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {
@@ -1081,6 +1121,7 @@ SmiPFHandler (
goto Exit;
}
}
CpuDeadLoop ();
goto Exit;
}
@@ -1089,7 +1130,8 @@ SmiPFHandler (
// If a page fault occurs in non-SMRAM range.
//
if ((PFAddress < mCpuHotPlugData.SmrrBase) ||
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {
(PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))
{
if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%lx) out of SMM range after SMM is locked!\n", PFAddress));
@@ -1103,8 +1145,9 @@ SmiPFHandler (
//
// If NULL pointer was just accessed
//
if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&
(PFAddress < EFI_PAGE_SIZE)) {
if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&
(PFAddress < EFI_PAGE_SIZE))
{
DumpCpuContext (InterruptType, SystemContext);
DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));
DEBUG_CODE (
@@ -1177,12 +1220,15 @@ SetPageTableAttributes (
//
if (!mCpuSmmRestrictedMemoryAccess ||
((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) ||
FeaturePcdGet (PcdCpuSmmProfileEnable)) {
FeaturePcdGet (PcdCpuSmmProfileEnable))
{
//
// Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.
//
ASSERT (!(mCpuSmmRestrictedMemoryAccess &&
(PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0));
ASSERT (
!(mCpuSmmRestrictedMemoryAccess &&
(PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)
);
//
// Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.
@@ -1204,6 +1250,7 @@ SetPageTableAttributes (
//
DisableCet ();
}
AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
do {
@@ -1228,6 +1275,7 @@ SetPageTableAttributes (
} else {
L4PageTable = (UINT64 *)PageTableBase;
}
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
@@ -1245,6 +1293,7 @@ SetPageTableAttributes (
// 1G
continue;
}
L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L2PageTable == NULL) {
continue;
@@ -1258,10 +1307,12 @@ SetPageTableAttributes (
// 2M
continue;
}
L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);
if (L1PageTable == NULL) {
continue;
}
SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);
PageTableSplitted = (PageTableSplitted || IsSplitted);
}

6
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
View File

@@ -121,12 +121,14 @@ GetProtectedModeCS (
GdtEntry = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;
for (Index = 0; Index < GdtEntryCount; Index++) {
if (GdtEntry->Bits.L == 0) {
if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) {
if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {
break;
}
}
GdtEntry++;
}
ASSERT (Index != GdtEntryCount);
return Index * 8;
}
@@ -188,6 +190,7 @@ InitShadowStack (
//
SmmShadowStackSize += EFI_PAGES_TO_SIZE (1);
}
mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));
PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);
DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));
@@ -222,4 +225,3 @@ InitShadowStack (
DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSspTable));
}
}

8
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
View File

@@ -170,11 +170,13 @@ RestorePageTableAbove4G (
if (Enable5LevelPaging) {
PTIndex = BitFieldRead64 (PFAddress, 48, 56);
}
if ((!Enable5LevelPaging) || ((PageTable[PTIndex] & IA32_PG_P) != 0)) {
// PML5E
if (Enable5LevelPaging) {
PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
}
PTIndex = BitFieldRead64 (PFAddress, 39, 47);
if ((PageTable[PTIndex] & IA32_PG_P) != 0) {
// PML4E
@@ -217,7 +219,6 @@ RestorePageTableAbove4G (
// If page entry does not existed in page table at all, create a new entry.
//
if (!Existed) {
if (IsAddressValid (PFAddress, &Nx)) {
//
// If page fault address above 4GB is in protected range but it causes a page fault exception,
@@ -241,6 +242,7 @@ RestorePageTableAbove4G (
PTIndex = BitFieldRead64 (PFAddress, 48, 56);
PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
}
// PML4E
PTIndex = BitFieldRead64 (PFAddress, 39, 47);
PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
@@ -263,12 +265,15 @@ RestorePageTableAbove4G (
if (!IsAddressValid (Address, &Nx)) {
PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
if (Nx && mXdSupported) {
PageTable[Index] = PageTable[Index] | IA32_PG_NX;
}
if (Address == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {
PTIndex = Index;
}
Address += SIZE_4KB;
} // end for PT
} else {
@@ -281,6 +286,7 @@ RestorePageTableAbove4G (
//
PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
}
//
// Set XD bit to 1
//

5
UefiCpuPkg/SecCore/FindPeiCore.c
View File

@@ -43,7 +43,6 @@ FindImageBase (
// Loop through the FFS files in the Boot Firmware Volume
//
for (EndOfFile = CurrentAddress + FirmwareVolumePtr->HeaderLength; ; ) {
CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;
if (CurrentAddress > EndOfFirmwareVolume) {
return EFI_NOT_FOUND;
@@ -82,6 +81,7 @@ FindImageBase (
} else {
EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN)((UINT8 *)File + sizeof (EFI_FFS_FILE_HEADER));
}
for ( ; ;) {
CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;
Section = (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress;
@@ -106,7 +106,7 @@ FindImageBase (
//
// Look for executable sections
//
if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {
if ((Section->Type == EFI_SECTION_PE32) || (Section->Type == EFI_SECTION_TE)) {
if (File->Type == FileType) {
if (IS_SECTION2 (Section)) {
*CoreImageBase = (PHYSICAL_ADDRESS)(UINTN)((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
@@ -114,6 +114,7 @@ FindImageBase (
*CoreImageBase = (PHYSICAL_ADDRESS)(UINTN)((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
}
}
break;
}
}

5
UefiCpuPkg/SecCore/SecBist.c
View File

@@ -185,6 +185,7 @@ GetBistInfoFromPpi (
if (BistInformationSize != NULL) {
*BistInformationSize = InformationSize;
}
return EFI_SUCCESS;
}
}
@@ -232,7 +233,9 @@ RepublishSecPlatformInformationPpi (
SecInformationDescriptor,
&mPeiSecPlatformInformation2
);
} if (Status == EFI_NOT_FOUND) {
}
if (Status == EFI_NOT_FOUND) {
Status = GetBistInfoFromPpi (
PeiServices,
&gEfiSecPlatformInformationPpiGuid,

4
UefiCpuPkg/SecCore/SecMain.c
View File

@@ -279,7 +279,8 @@ SecStartupPhase2(
do {
if (CompareGuid (PpiList[Index].Guid, &gEfiPeiCoreFvLocationPpiGuid) &&
(((EFI_PEI_CORE_FV_LOCATION_PPI *)PpiList[Index].Ppi)->PeiCoreFvLocation != 0)
) {
)
{
//
// In this case, SecCore is in BFV but PeiCore is in another FV reported by PPI.
//
@@ -299,6 +300,7 @@ SecStartupPhase2(
}
} while ((PpiList[Index++].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
}
//
// If EFI_PEI_CORE_FV_LOCATION_PPI not found, try to locate PeiCore from BFV.
//

4
UefiCpuPkg/SecMigrationPei/SecMigrationPei.c
View File

@@ -26,7 +26,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInfo
SecPlatformInformationPostMemory
};
GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_DONE_PPI mSecTemporaryRamDonePostMemoryPpi = {
SecTemporaryRamDonePostMemory
};
@@ -151,7 +150,7 @@ GetPerformancePostMemory (
{
SEC_PLATFORM_INFORMATION_CONTEXT_HOB *SecPlatformInformationContexHob;
if (This == NULL || Performance == NULL) {
if ((This == NULL) || (Performance == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -330,6 +329,7 @@ RepublishSecPpis (
if (SecPlatformInformationContextHob->Context.PlatformInformationRecord == NULL) {
return EFI_OUT_OF_RESOURCES;
}
SecPlatformInformationContextHob->Context.StructureSize = SecStructureSize;
Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *)PeiPpi)->PlatformInformation (

62
UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
View File

@@ -166,6 +166,7 @@ typedef struct {
//
// Function prototypes
//
/**
a ASM function to transfer control to OS.
@@ -262,15 +263,33 @@ EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable = {
//
GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = {
/* selector { Global Segment Descriptor } */
/* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x08 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x10 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},
/* 0x18 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},
/* 0x20 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x28 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},
/* 0x30 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},
/* 0x38 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}},
/* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
/* 0x00 */ {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
},
/* 0x08 */ {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
},
/* 0x10 */ {
{ 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0 }
},
/* 0x18 */ {
{ 0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0 }
},
/* 0x20 */ {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
},
/* 0x28 */ {
{ 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0 }
},
/* 0x30 */ {
{ 0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0 }
},
/* 0x38 */ {
{ 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0 }
},
/* 0x40 */ {
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
},
};
#define DATA_SEGEMENT_SELECTOR 0x18
@@ -283,7 +302,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {
(UINTN)mGdtEntries
};
/**
The function will check if current waking vector is long mode.
@@ -302,20 +320,24 @@ IsLongModeWakingVector (
Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable));
if ((Facs == NULL) ||
(Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||
((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {
((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)))
{
// Something wrong with FACS
return FALSE;
}
if (Facs->XFirmwareWakingVector != 0) {
if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&
((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0))
{
// Both BIOS and OS wants 64bit vector
if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {
return TRUE;
}
}
}
return FALSE;
}
@@ -354,6 +376,7 @@ SignalToSmmByCommunication (
Header32.MessageLength = 0;
CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_32, Data);
}
CopyGuid (CommBuffer, HandlerType);
Status = PeiServicesLocatePpi (
@@ -440,7 +463,8 @@ S3ResumeBootOs (
if ((Facs == NULL) ||
(Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||
((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {
((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)))
{
//
// Report Status code that no valid vector is found
//
@@ -492,7 +516,8 @@ S3ResumeBootOs (
));
if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&
((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&
((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {
((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0))
{
//
// X64 long mode waking vector
//
@@ -646,6 +671,7 @@ RestoreS3PageTables (
PhysicalAddressBits = 32;
ZeroMem (PageMap, EFI_PAGES_TO_SIZE (2));
}
//
// Calculate the table entries needed.
//
@@ -714,6 +740,7 @@ RestoreS3PageTables (
}
}
}
return;
} else {
//
@@ -827,6 +854,7 @@ S3ResumeExecuteBootScript (
);
ASSERT (FALSE);
}
DEBUG ((DEBUG_INFO, "PeiS3ResumeState - %x\r\n", PeiS3ResumeState));
PeiS3ResumeState->ReturnCs = 0x10;
PeiS3ResumeState->ReturnEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)S3ResumeBootOs;
@@ -877,6 +905,7 @@ S3ResumeExecuteBootScript (
//
CpuDeadLoop ();
}
/**
Restores the platform to its preboot configuration for an S3 resume and
jumps to the OS waking vector.
@@ -1001,6 +1030,7 @@ S3RestoreConfig2 (
} else {
Build4GPageTableOnly = TRUE;
}
RestoreS3PageTables ((UINTN)AcpiS3Context->S3NvsPageTableAddress, Build4GPageTableOnly);
}
@@ -1057,6 +1087,7 @@ S3RestoreConfig2 (
(VOID *)(UINTN)(SmmS3ResumeState->SmmS3StackBase + SmmS3ResumeState->SmmS3StackSize)
);
}
if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {
//
// Switch to long mode to complete resume.
@@ -1085,6 +1116,7 @@ S3RestoreConfig2 (
Cr0.Bits.PG = 0;
AsmWriteCr0 (Cr0.UintN);
}
AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);
//
@@ -1102,12 +1134,12 @@ S3RestoreConfig2 (
SmmS3ResumeState->SmmS3StackBase + SmmS3ResumeState->SmmS3StackSize
);
}
}
S3ResumeExecuteBootScript (AcpiS3Context, EfiBootScriptExecutorVariable);
return EFI_SUCCESS;
}
/**
Main entry for S3 Resume PEIM.