MdeModulePkg: Add UFS (Universal Flash Storage) Stack
It includes 4 drivers: 1. UfsPassThruDxe, which is a UEFI driver and consumes EFI_UFS_HOST_CONTROLLER_PROTOCOL and produces EFI_EXT_SCSI_PASS_THRU_PROTOCOL 2. UfsPciHcDxe, which is specific for pci-based UFS HC implementation and is a UEFI driver to produce EFI_UFS_HOST_CONTROLLER_PROTOCOL. 3. UfsBlockIoPei, which is a PEI driver and consumes EFI_UFS_HOST_CONTROLLER_PPI and produces EFI_PEI_VIRTUAL_BLOCK_IO_PPI. 4. UfsPciHcPei, which is specific for pci-based UFS HC implementation and is a PEI driver to produce EFI_UFS_HOST_CONTROLLER_PPI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17246 6f19259b-4bc3-4df7-8a09-765794883524
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152
MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
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152
MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
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/** @file
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UfsPciHcPei driver is used to provide platform-dependent info, mainly UFS host controller
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MMIO base, to upper layer UFS drivers.
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Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "UfsPciHcPei.h"
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EDKII_UFS_HOST_CONTROLLER_PPI mUfsHostControllerPpi = { GetUfsHcMmioBar };
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EFI_PEI_PPI_DESCRIPTOR mPpiList = {
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(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
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&gEdkiiPeiUfsHostControllerPpiGuid,
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&mUfsHostControllerPpi
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};
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/**
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Get the MMIO base address of UFS host controller.
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@param[in] This The protocol instance pointer.
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@param[in] ControllerId The ID of the UFS host controller.
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@param[out] MmioBar Pointer to the UFS host controller MMIO base address.
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@retval EFI_SUCCESS The operation succeeds.
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@retval EFI_INVALID_PARAMETER The parameters are invalid.
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**/
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EFI_STATUS
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EFIAPI
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GetUfsHcMmioBar (
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IN EDKII_UFS_HOST_CONTROLLER_PPI *This,
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IN UINT8 ControllerId,
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OUT UINTN *MmioBar
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)
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{
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UFS_HC_PEI_PRIVATE_DATA *Private;
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if ((This == NULL) || (MmioBar == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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Private = UFS_HC_PEI_PRIVATE_DATA_FROM_THIS (This);
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if (ControllerId >= Private->TotalUfsHcs) {
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return EFI_INVALID_PARAMETER;
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}
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*MmioBar = (UINTN)Private->UfsHcPciAddr[ControllerId];
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return EFI_SUCCESS;
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}
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/**
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The user code starts with this function.
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@param FileHandle Handle of the file being invoked.
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@param PeiServices Describes the list of possible PEI Services.
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@retval EFI_SUCCESS The driver is successfully initialized.
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@retval Others Can't initialize the driver.
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**/
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EFI_STATUS
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EFIAPI
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InitializeUfsHcPeim (
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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EFI_BOOT_MODE BootMode;
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EFI_STATUS Status;
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UINT16 Bus;
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UINT16 Device;
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UINT16 Function;
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UINT32 Size;
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UINT8 SubClass;
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UINT8 BaseClass;
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UFS_HC_PEI_PRIVATE_DATA *Private;
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//
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// Shadow this PEIM to run from memory
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//
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if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {
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return EFI_SUCCESS;
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}
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Status = PeiServicesGetBootMode (&BootMode);
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///
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/// We do not export this in S3 boot path, because it is only for recovery.
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///
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if (BootMode == BOOT_ON_S3_RESUME) {
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return EFI_SUCCESS;
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}
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Private = (UFS_HC_PEI_PRIVATE_DATA *) AllocateZeroPool (sizeof (UFS_HC_PEI_PRIVATE_DATA));
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if (Private == NULL) {
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DEBUG ((EFI_D_ERROR, "Failed to allocate memory for UFS_HC_PEI_PRIVATE_DATA! \n"));
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return EFI_OUT_OF_RESOURCES;
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}
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Private->Signature = UFS_HC_PEI_SIGNATURE;
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Private->UfsHostControllerPpi = mUfsHostControllerPpi;
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Private->PpiList = mPpiList;
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Private->PpiList.Ppi = &Private->UfsHostControllerPpi;
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for (Bus = 0; Bus < 256; Bus++) {
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for (Device = 0; Device < 32; Device++) {
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for (Function = 0; Function < 8; Function++) {
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SubClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0A));
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BaseClass = PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, 0x0B));
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if ((SubClass == 0x09) && (BaseClass == PCI_CLASS_MASS_STORAGE)) {
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//
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// Get the Ufs Pci host controller's MMIO region size.
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//
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PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
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PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);
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Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET));
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//
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// Assign resource to the Ufs Pci host controller's MMIO BAR.
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// Enable the Ufs Pci host controller by setting BME and MSE bits of PCI_CMD register.
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//
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PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs));
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PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
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//
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// Record the allocated Mmio base address.
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//
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Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs;
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Private->TotalUfsHcs++;
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ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS);
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}
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}
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}
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}
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///
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/// Install Ufs Host Controller PPI
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///
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Status = PeiServicesInstallPpi (&Private->PpiList);
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ASSERT_EFI_ERROR (Status);
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return Status;
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}
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