ArmPlatformPkg/PL34xDmc: Remove DMC base address from the DMC configuration
By removing the DMC Base Address from the structure, we can reuse the same DMC configuration for two similar DMC controllers. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11960 6f19259b-4bc3-4df7-8a09-765794883524
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@@ -17,16 +17,14 @@
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typedef struct {
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UINTN base; // base address for the controller
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UINTN phy_ctrl_base; // DDR2 Phy control base
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UINTN HasQos; // has QoS registers
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UINTN MaxChip; // number of memory chips accessible
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BOOLEAN IsUserCfg;
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UINT32 User0Cfg;
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UINT32 User2Cfg;
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UINT32 refresh_prd;
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UINT32 cas_latency;
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UINT32 write_latency;
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UINT32 RefreshPeriod;
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UINT32 CasLatency;
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UINT32 WriteLatency;
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UINT32 t_mrd;
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UINT32 t_ras;
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UINT32 t_rc;
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@@ -245,16 +243,6 @@ typedef struct {
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#define PHY_PTM_REFCLK_DIV_200_400MHz 0x0
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#define PHY_PTM_REFCLK_DIV_400_800MHz 0x1
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// PHY Reset in SCC
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#define SCC_PHY_RST_REG_OFF 0xA0
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#define SCC_REMAP_REG_OFF 0x00
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#define SCC_PHY_RST0_MASK 1 // Active LOW PHY0 reset
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#define SCC_PHY_RST0_SHFT 0 // Active LOW PHY0 reset
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#define SCC_PHY_RST1_MASK 0x100 // Active LOW PHY1 reset
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#define SCC_PHY_RST1_SHFT 8 // Active LOW PHY1 reset
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#define TC_UIOLHNC_MASK 0x000003C0
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#define TC_UIOLHNC_SHIFT 0x6
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#define TC_UIOLHPC_MASK 0x0000003F
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@@ -331,8 +319,10 @@ typedef struct {
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#define DDR2_MR_WR_CYCLES_6 (5 << 9)
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VOID PL341DmcInit (
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IN PL341_DMC_CONFIG *config
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VOID
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PL341DmcInit (
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IN UINTN DmcBase,
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IN PL341_DMC_CONFIG* DmcConfig
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);
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VOID PL341DmcPhyInit (
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