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ArmPlatformPkg: Introduce Primary core macros

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On MpCore system, the primary core can now be any core of the system.

To identify the primary core, you can use 'gArmTokenSpaceGuid.PcdArmPrimaryCoreMask'
and 'gArmTokenSpaceGuid.PcdArmPrimaryCore'.
These PCDs by default use the ClusterId and CoreId to identify the core. And the
primary core is defined as the ClusetrId=0 and CoreId=0.

The helper macros are: IS_PRIMARY_CORE(MpId), GET_CORE_ID(MpId), GET_CLUSTER_ID(MpId),
GET_CORE_POS(MpId), PRIMARY_CORE_ID.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12412 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
2011-09-22 23:01:13 +00:00
parent 55a0d64b88
commit 0787bc6184
24 changed files with 95 additions and 60 deletions
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12
ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
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@@ -14,14 +14,14 @@
#include <PiPei.h>
#include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
#include <Library/DebugLib.h>
#include <Library/PcdLib.h>
#include <Library/PrintLib.h>
#include <Library/SerialPortLib.h>
#include <Chipset/ArmV7.h>
#define ARM_PRIMARY_CORE 0
#include <Chipset/ArmV7.h>
// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
@@ -38,7 +38,7 @@ NonSecureWaitForFirmware (
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
// Jump to secondary core entry point.
secondary_start ();
@@ -56,7 +56,7 @@ NonSecureWaitForFirmware (
**/
VOID
ArmPlatformSecExtraAction (
IN UINTN CoreId,
IN UINTN MpId,
OUT UINTN* JumpAddress
)
{
@@ -64,7 +64,7 @@ ArmPlatformSecExtraAction (
UINTN CharCount;
if (FeaturePcdGet (PcdStandalone) == FALSE) {
if (CoreId == ARM_PRIMARY_CORE) {
if (IS_PRIMARY_CORE(MpId)) {
UINTN* StartAddress = (UINTN*)PcdGet32(PcdNormalFvBaseAddress);
// Patch the DRAM to make an infinite loop at the start address
@@ -85,7 +85,7 @@ ArmPlatformSecExtraAction (
*JumpAddress = (UINTN)NonSecureWaitForFirmware;
}
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
if (CoreId == ARM_PRIMARY_CORE) {
if (IS_PRIMARY_CORE(MpId)) {
// Signal the secondary cores they can jump to PEI phase
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);